GB2377132A

GB2377132A - Interrupting erase operation in mobile telephone flash memory

Info

Publication number: GB2377132A
Application number: GB0210369A
Authority: GB
Inventors: Des Graviers Marc-Emm Coupvent
Original assignee: Sagem SA
Current assignee: Sagem SA
Priority date: 2001-05-07
Filing date: 2002-05-07
Publication date: 2002-12-31
Anticipated expiration: 2022-05-07
Also published as: GB2377132B; DE10220367B4; DE10220367A1; FR2824414B1; GB0210369D0; FR2824414A1

Abstract

Mobile telephones use block erasable/programmable flash type memories e.g. Flash EEPROM (FEEPROM), to store both applications and remanent (non volatile) data of the mobile phone. Classic one-bank flash memory cannot perform simultaneous read and erasure operations and if an application access is requested during a data erase procedure, there is a delay while the erase procedure is interrupted. If an application is required quickly, this delay can be problematic and the invention is directed to reducing this delay. The mobile telephone has a microprocessor, a particular memory register, a first flash type memory storing a first set of applications and a second flash type memory storing a second set of applications and remanent data. An attempt to access (203) the second set of applications during erasure (200) of the remanent data causes the microprocessor to read the particular register (208), which results in an erasure interrupt operation (211). In the particular embodiment, a chip select switch directs (208) the application access request to the register, which contains data that the microprocessor cannot interpret (i.e. an unknown opcode). The microprocessor reads the register and when it cannot interpret the data, an error is reported (209, 210). This error implements an application (e.g. a "trap" application in the first flash memory) which swiftly interrupts (211) the data erasure. Suspension of the erasure procedure is typically achieved 20 milliseconds after the start of the access attempt. Thus speedy access is achieved without having to use two-bank flash memories, which are more expensive and provide less flexibility in the definition of the size of the remanent data.

Description

23771 32

Method for the management of erasure operations in mobile telephone memories An object of the present invention is a method for the management of 5 erasure operations in mobile telephone memories. More particularly, the invention relates to a method for performing operations to erase data contained in a first memory module while at the same time leaving the possibility of accessing different applications that may be contained in this first memory module and/or in a second memory module, where the 10 applications of the second memory module may call up the applications of the first memory module.

The field of the invention, generally, is that of mobile telephony. In

recent years, this field has seen widespread success among the public, along

with major technological changes. The mobile telephones proposed to the 15 public perform increasingly well and offer growing numbers of different functions. Consequently, the number of applications that have to be programmed in mobile telephones has become considerable, requiring a significant increase in the memory space available for the storage of the computer codes of these different applications.

20 For reasons of speed of access to the information contained and because of the limited volume that they occupy, the storage memories of these different applications are FEEPROM (Flash Electrically Erasable and Programmable Read Only Memory) type memories, more commonly known as flash memories. The memories are non-volatile dynamic memories. They 25 are bloc-erasable and their contents can no longer be accessed when they are in erasure mode. In other words, it is not possible in such memories to carry out a simultaneous erasure and read operation for example.

Furthermore, this type of memory is also designed to store a set of data known as remanent (or non-volatile) data: this data represents all the 30 information that must not be lost when the mobile set is turned off. This data for example pertains to the numbers called, the setting up of a directory, a logo of the operator, or again the definition of a user profile for the user of the telephone set considered.

In the layout of these flash memories designed for the storage of the 35 different applications, the following developments have been observed:

initially, a single flash type memory module with a capacity of one megabyte and then two megabytes was used. A first problem appeared because of the coexistence of the remanent data and of the codes of the different applications in one in the same flash memory. Indeed, stored data may have 5 to be modified or even eliminated. This means that a microprocessor managing this memory module often has to carry out data erasure operations. However, as stated, it is not possible, in classic flash memories, to be simultaneously in erasure mode and in data access mode. Now the code 10 contained in this memory module contains especially applications known as interrupt applications which must be activated very speedily whenever a call link is set up or during a demand coming from the user and, most usually, the erasure operation is stopped far too slowly to be capable of activating these applications in good time.

15 The solution to this problem has lain in the use of flash memories known as two-bank memories. This type of memory consists of two distinct zones or banks: a first zone is designed for example for the code of the different applications and a second zone for the remanent data. It permits an erasure in the first zone, or bank, simultaneously with an operation to access 20 the code contained in the other zone of the memory. Naturally, for equal storage capacity, a two-bank flash memory is costlier than a classic one-bank flash memory. For equal storage capacity, it is however less costly than two separate flash memories.

Subsequently, as the different applications to be stored became more 25 numerous and complex, a single flash memory module, whether it was a onebank memory or a two-bank memory, became insufficient. It then became necessary to use two flash memories: a first one-bank flash memory containing exclusively codes associated with different applications and, for the reasons that have just been described, a second two-bank flash memory.

30 The drawback of such a solution was the high price of the components used, the two-bank flash memory itself being especially costly.

An answer has been proposed to this drawback: this is an entirely software-based solution in which a software application detects the fact that no application stored in one of the flash memories is active. As the case may 35 be, this software application organises and controls the different erasure

operations needed. This approach however has two major drawbacks: firstly it should be possible to detect the fact that no application of the flash memories is active; secondly, there must be the certainty that the different applications stored in the flash memories will not be called up during the 5 erasure operation. Indeed, if the user has just called up one of these applications during a data erasure phase, his waiting period may go up to about one second, which is far too great.

The erasure management method according to the invention provides a solution to the different problems that have just been explained. Thanks to 10 the invention, a two-bank flash memory used in the prior art is replaced by a

classic one-bank flash memory, and a specific mechanism is set up to respond speedily and favourably to any request for access to applications of either one of the flash memories, even when a operation for the erasure of data contained in the second flash memory is being executed. Furthermore, 15 the method of the invention prompts the reading of a preliminarily determined register when an operation for the erasure of data contained in the second flash memory is begun, the reading of this register leading to the appearance of an error that swiftly interrupts the erasure operation in progress. In a preferred embodiment, the method according to the invention puts a chip 20 select switch into action. This chip select switch orients or routes an attempt to access the applications of the second flash memory towards the preliminarily determined register.

The invention therefore relates to a method for the management of erasure operations in mobile telephony memories, the mobile telephone 25 comprising a microprocessor, a chip select switch, a first flash type memory containing a first set of applications and a second flash type memory comprising, firstly, a second set of applications and, secondly, remanent data of the mobile telephone, characterized in that the method comprises a step in which, during a phase for the erasure of data contained in the second flash 30 memory and during an attempt to access the second set of applications, the microprocessor is made to read a particular register to activate an erasure interrupt operation.

In a particular embodiment, the method comprises one additional step or the two additional steps in which the following operations are performed 35 prior to the step for reading the particular register:

- parametrizing the chip select switch so that any attempt to access the second set of applications contained in the second flash memory is routed to the particular register; - writing one or more pieces of data, not interpretable by the 5 microprocessor, to the register.

The totality of the particular register may contain data not interpretable by the microprocessor. These data may be similar and may have been written in the particular register during the manufacture of the mobile telephone. After the microprocessor has read a non- interpretable piece of 10 data of the particular register, an application to interrupt the first set of applications may be executed to suspend the erasure of the data of the second flash memory, the interrupt operation lasting about 20 milliseconds.

Various alternative embodiments of the method according to the invention provide for the additional steps of resuming the operation of 15 erasure at the end of a certain period of interrupt time preliminarily determined, and possibly the additional step in which the interruption is extended beyond the preliminarily determined interrupt time if applications of the second flash type memory are still active at this time.

A step of the method may be executed prior to the others steps. This 20 step consists of the distribution of the different applications so that they are in the first set of applications or in the second set of applications, depending on how essential they are to the management of a call link.

The invention and its different applications will be understood more clearly from the following description and the appended figures. These

25 figures are given purely by way of an application and in no way restrict the scope of the invention. Of these figures: Figure 1 shows a schematic view of the layout of the main components coming into play in the method according to the invention; Figure 2 is a flow chart illustrating different possible steps of the 30 method according to the invention.

Figure 1 shows a first flash memory F1 and a second flash memory F2 which are connected to a data bus 100. In practice, the first flash memory F1 has a storage capacity of about two megabytes, and the second flash memory F2 has a capacity that can vary from about one to two megabytes.

35 The method according to the invention could, however, also be implemented

with flash memories having other storage capacities. The first flash memory F1 contains exclusively computer code relating to a first set of applications 101. The second flash memory F2 contains, firstly, in a first memory zone 104, code pertaining to a second set of applications 102 and, in a second 5 memory zone 105, remanent data 103 which may be the object of erasure operations. However, contrary to two-bank flash memories, the different zones 104 and 105 are not permanently fixed and their size may evolve as a function of need and of the development of the number of applications and/or of the data. The first set of applications 101 comprises especially the 10 essential applications liable, as the case may be, to use applications of the second set of applications 102, which may be considered to be auxiliary applications. The data bus 100 is used to convey, firstly, data and, secondly, different commands coming from a microprocessor 106, also connected to 15 the data bus 100. Furthermore, in a simplified way, a data bus 107 is connected firstly to the microprocessor 106 and, secondly, to a programmable logic component 108, for example of the EPLD (Electrically Programmable Logical Device) type. The programmable logic device comes into play as a chip select switch. On the basis of the information that the 20 microprocessor 106 sends it through the address bus 107, this chip select switch performs an address decoding operation to determine the active component for which the different data elements actually flowing on the data bus 100 are intended. Thus, since they are all connected to the data bus 100, all the active components are liable to receive the data flowing on the 25 data bus 100, but only the one which has been selected by the chip select component 108 will effectively take account of the data that it will have received. To select a component, the chip select switch 108 sends an appropriate signal through a link 109 directly connecting a pin 110 of the switch 108 to a specific pin 111, called a chip select input, of the active 30 component considered.

In practice, a part of the addresses circulating on the address bus 107 is directly sent to the active components, the switch interpreting only the more significant bits of these addresses.

Finally, a memory register 112, hereinafter designated as a particular 35 memory register, is also connected to the data bus 100. This particular

register may, for example, be associated (but this is not a requirement) with an ASIC ( Application Specific Integrated Circuit) 113 already present inside the mobile telephone. The particular register could also be contained in any buffer memory of the mobile telephone. It preferably has a limited 5 addressable size, in the range of one byte.

A possible implementation and operation of the method according to the invention, in the architecture just presented, are described in detail in the flow chart of Figure 2.

A first step 200 of this flow chart is marked by the execution of an 10 operation for the erasure of certain remanent data 103. As soon as such an operation begins, a step 201 for switching the chip select switch 108 is implemented. In this step 201, the chip select switch 108 is parametrized in such a way that, when an attempt to access applications 102 of the second flash memory F2, which takes the form of a command to read the code 15 pertaining to one or more desired applications, reaches the switch 108, this switch routes the read instruction to the particular register 112. The switch has been subjected to preliminary programming so that the step 201 is implemented automatically as soon as the second flash memory F2 is in erasure mode.

20 Immediately after the step 201 for the flip-over of the switch 108, there is a write operation 202 for writing to the particular register 112. In this step 202, an operational code, or opcode, unknown to the microprocessor, is written in the particular register. In general, an opcode is a number representing an instruction that the microprocessor 106 must understand and 25 execute. An unknown opcode is precisely a number that does not correspond to any instruction from the list of the instructions that the microprocessor is supposed to recognise. In other modes of implementation of the method according to the invention, the step 202 could be performed before the step 201, or it could even be totally ignored if the particular 30 register 112 has undergone this write operation beforehand, for example during the manufacture of the mobile telephone, and if this register 112 not have been modified ever since. In any case, it is possible to write one or more unknown opcodes, preferably in the entire particular register. In certain variants, the same unknown opcode is written to all the memory registers of 35 the particular register 112.

The mobile telephone is then in a state where it can efficiently manage any attempt to access the applications 102 of the second flash memory F2.

In a decision step 203, it is determined whether there is an access attempt such as this. So long as this is not the case, the different erasure operations 5 may continue in a step 204. In a decision step 205, it is then determined whether the erasure operation or operations are completed. If this is not the case, the different operations are resumed at the decision step 203.

However, if the erasure operations are completed, a step 206, called a switch-back step, is then carried out. In this step 206, the switch 108 is 10 parametrized to retrieve the operating parameters that it had before the step 201. Thus, when an attempt to access applications 102 of the second flash memory F2 reaches the switch 108, this switch 108 effectively routes the read instruction to the second flash memory F2. If necessary, the unknown opcode is erased from the particular register 112.

15 When an attempt to access the applications 102 of the second flash memory F2 appears at the decision step 203, there is a step 208 in which said read instruction corresponding to the access attempt is routed by the switch 108 to the particular register 112. The step 208 is preferably preceded by a storage step 207, in which the information on the diverted access data 20 are stored, and especially the targeted address in the second flash memory F2. At least one unknown opcode is then read by the microprocessor 106.

Now, when the microprocessor 106 is asked to interpret an unknown opcode, it detects and reports an error in a step 209 and interrupts the program in 25 progress, in this case the operations for the erasure of the remanent data 103. To this end, the microprocessor 106 activates an error- processing operation in a step 210. This error-processing operation has the effect, especially, of implementing an application for the interruption of the erasure operations. This application may be, for example, a routine application called 30 a "trap", contained in the first flash memory F1.

The erasure operations are effectively suspended in a step 211, typically about 20 milliseconds after the start of the attempt to access the applications 102 of the second flash memory F2. Naturally, if a particular application of the first flash memory F1 is called up, especially for a priority 35 running of a call link, the data erasure interrupt mechanism is suspended to

be subsequently resumed, when the particular application is no longer active.

In this case, the erasure may be continued during the suspension of the interrupt mechanism.

Once the erasure operations are suspended, it is possible, in a step 5 212, to access and activate the initially desired applications of the second flash memory F2. To this end, the invention uses the information on the access attempt diverted to the particular register, which had been stored.

In certain modes of implementation of the method according to the invention, it is possible to bring into play a limit duration of erasure of the 10 remanent data. In this case, a decision step 213 verifies if this maximum duration has been reached. If this is not so, the step 212 is continued. If the maximum duration is reached, there is a decision step 214 in which the microprocessor 106 determines whether the step 212 has reached its term, namely if the applications 102 that have been accessed are no longer active.

15 If this is the case, the method is resumed at the step 204 in which the erasure operations are continued. If not, the method is resumed at the step 212 in which the applications 102 are active.

The method according to the invention therefore relies especially on a combination of the programming of the chip select switch 108 used to 20 designate the chip select inputs 111 to be activated, the use of a smallsized memory component 112 containing an opcode unknown to the microprocessor 106, and the use of an interrupt mechanism. One of the advantages of the present invention is that it gives operation comparable to that of an architecture using a two-bank flash memory for a lower cost.

25 Finally, it must be noted that the modification of the select switch to adapt it to the method according to the invention is light. A hundred lines of codes are enough. It must also be noted that flexibility is obtained in the definition of the size of the remanent data. This was not achieved with a two-bank flash memory.

Claims

1. Method for the management of erasure operations in mobile telephony memories, the mobile telephone comprising a microprocessor, a 5 chip select switch, a first flash type memory containing a first set of applications and a second flash type memory comprising, firstly, a second set of applications and, secondly, remanent data of the mobile telephone, characterised in that the method comprises a step in which, during a phase for the erasure of data contained in the second flash memory and during an 10 attempt to access the second set of applications, the microprocessor is made to read a particular register to activate an erasure interrupt operation.

2. Method according to the claim 1 characterised in that it comprises the additional step in which, prior to the step for reading the particular register, the chip select switch is parametrized to route any attempt 15 to access the second set of applications contained in the second flash memory to the particular register.

3. Method according to any one of claims 1 or 2, characterised in that it comprises the additional step in which, prior to the step for reading the particular register, one or more data not interpretable by the microprocessor 20 are written in the particular register.

4. Method according to the claim 3, characterised in that the totality of the particular register contains data not interpretable by the microprocessor.

5. Method according to any one of claims 3 or 4, characterised in 25 that all the data written in the particular register are similar.

6. Method according to any one of the claims 3 to 5, characterised in that each piece of data not interpretable by the microprocessor is written to the particular register during the manufacture of the mobile telephone.

7. Method according to any one of the claims 4 to 6, characterised 30 in that it comprises the additional step in which, after the reading by the microprocessor of a piece of data not interpretable by the particular register, an application is executed to interrupt the first set of applications to suspend the erasure of the data of the second flash memory.

8. Method according to any one of the preceding claims, 35 characterised in that the particular register is the register of an ASIC.

9. Method according to any one of the preceding claims, characterized in that the duration of the erasure interrupt operation is in the range of 20 milliseconds.

10. Method according to any one of the preceding claims, 5 characterized in that it comprises the additional step in which the erasure operation is resumed at the end of a certain period of interrupt time that is preliminarily determined.

11. Method according to claim 11, characterized in that it comprises the additional step in which the interruption is prolonged beyond the 10 preliminarily determined interrupt time if applications of the second flash time memory are still active at this point in time.

12. Method according to any one of the preceding claims, characterized in that it comprises the additional step in which the different applications are distributed between the first set of applications and the 15 second set of applications, depending on how essential they are to the management of a call link.

13. A method for the management of erasure operations in mobile telephony memories as substantially herein described.

14. A method for the management of erasure operations in mobile 20 telephony memories as substantially herein described with reference to, and as shown in the accompanying drawings.