GB2377041A - Programming memory devices via IEEE 1149.1 - Google Patents

Abstract

A method of programming memory devices, including non- IEEE 1149.1 (JTAG) compliant devices, via IEEE 1149.1, whilst reducing the number of TCK cycles required per memory location, is disclosed. A memory write control line is used instead of Shift-DR sequences to set the memory write line active and then false.. The tester device is separated from the PCBA so that the user can selectively connect the PCB IEEE 1149.1 bus to the host tester, so as to use a number of local IEEE 1149.1 scan chains. Thus only five wires are necessary in the process. The chain splitting aids PCBA diagnosis.

Description

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DESCRIPTION This document describes a device, that over comes the excessive time required to program non IEEE 1149 1 compliant memory devices A typical implementation for programming non IEE1149 1 memory devices, is to have a IEEE1149 1"scan chain"of all supporting devices driven by a tester Then ever I/O pin on the memory device (also the memory could be embedded in another such as FPGA for example) is connected to an I/O pin of a device that does support the IEEE1149. 1 standard (see Figure 1 for typical interconnection scheme) The sequence for programming a memory location is then to set up the data and address with one IEEE1149 1 Shift-DR sequence which would require x TCK cycles Followed by another Shift-DR sequence to set the memory write line active which again requires x TCK cycles. The final stage is to set the memory write signal false by yet another Shift-DR sequence again taking x TCK cycles. It can be seen that to program a single memory location three times the number of TCK's to set the actual address and data of the flash location is required. As in a production environment Fmax for TCK is approx 10Mhz, this is due to degradation of the TCK signal as it passes through a test fixture on an ATE and is received at the PCBA under test. For this reasons memory programming times is excessive for programming non IEEE1149. 1 devices and is impracticable for high volume production lines.

The goal for programming memory devices via IEEE1149. 1 is to reduce the number of TCK cycles required per memory location. This is what the device aims to solve in a totally programmable fashion so that it is memory vendor timing independent. The device's solution is achieved by separating the tester device that is providing the stimuli for the IEEE1149. 1 signal from the PBCA. Under the total control of IEEE1149 1 signal it is capable of being addressed and by using the standard Instruction/Data register protocol of the IEEE1149. 1 standard the user is able to selectively connect the PCB IEEE 1149. 1 bus to the host tester. The number of these "Local IEEE 1149. 1 scan chains" is programmable when the device is implemented These Local chains are then connected in the required configuration under real time software control using the IEEE1149. 1 protocol, into a single IEEE 1149.1 chain. Each of the Local IEEE1149. 1 chains has an additional signal pin that is generated under software control within the device that can be used as the write signal to non IEEE1149 1 memory devices.

This additional memory write (MEMWR) signal is generated as pulse which is totally configurable via the internal registers of the device which are controlled by the incoming

IEEE1149. 1 standard 5 signal wires. During the normal Shift-DR sequence when all the data is valid and stable on the I/O of the memory device. See figure 2. for interconnection scheme. The memory write signal goes active during the Run-Test-Idle state of the IEEE1149. 1 state machine if it has been enabled by it control registers. These control registers are set up using the standard Shift-DR after the required instruction register has been selected. By performing a memory write signal automatically when the IEEE1149. 1

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state machine enters the Run-Test-Idle state. Only the Shift-DR sequence to setup the address and data on the memory is required The tester device will wait in the Run-Test- idle phase for the required amount of time to complete the operation The advantage of supporting individual local IEEE 1 149 1 scan chins on the PCBA is that multiple different blocks of memory can each be provided with an individual memory write signal Additionally the device provides a means to individually address a particular PCBA printed circuit assembly within the System back plane or stand alone PCBA That enables the user to selectively program Non IEEE1149 1 programmable memory devices mounted to a PCBA in a system configuration or stand alone, in a reduced amount of time compared to before. All access to the device is via the IEEE 1149 1 standard interface of 5 wires, with no jumpers required if PCBA's are added or removed from the system back plane.

Further additional benefits of the device, due to chain splitting on the PCBA's includes the fact that it aids for PCBA diagnosis If the PCBA had a single large IEEE1149 1 chain then any failure on that IEEE1149. 1 chain would render the PCBA un-testable via the IEEE 1149. 1 protocol.

It must be noted that the memory write signal is generated during the Run-Test-Idle phase of the IEEE 1 149. 1 state machine (see figure 3). When a memory write operation is to occur after the setting up of the data on the pins the IEEE1149 1 state machine must flow through the Run-Test-Idle state and wait in the Run-Test-Idle state for the write to complete. The shape and time duration which all are derived from the incoming TCK signal from the host tester are totally programmable by setting up the content of the devices internal registers during a normal Shift-IR/DR sequence

Claims (1)

1. Claims 1/Provide approx 3: 1 reduction in the programming of non IEEE 1149 1 compliant memory using only the standard 5 wire interface of the EEE1149 1 standard 2/A method of providing the ability to address the device using the IEEE1149. 1 and segment the memory into different blocks for writing to.