GB2375196A - Method for optimisation of memory storage by measuring filling - Google Patents

Abstract

A method for optimisation of memory storage measures filling rate or filling status of the storage which is particularly a FIFO. The method uses a filling rate or status flag which is modified when the data in the storage fulfils a predetermined condition such as the end of transmission of a packet. The modification of the flag value preferably leads to a data transfer to or from the storage means activated by pipelined logic control.

Description

1 2375196

METHOD FOR THE OPTIMIZATION OF THE USE OF A STORAGE

METHOD, SWITCHING DEVICE, SIGNAL AND CORRESPONDING

APPLICATION

BACKGROUND OF THE INVENTION

5 1. Field of the Invention

The field of the invention is that of an implementation of storage

means, especially, but not exclusively in the context of systems for the switching, transmission and/or reception of digital data.

More specifically, the invention relates to the optimizing of the use of 10 storage means supplied with data that are received and have to be transferred to an addressee element.

These storage means may be especially a FIFO (first-in-first-out) memories associated with input ports of a switching device that transfers sets of data, for example in the form of packets. In particular, storage means of 15 this kind may be implemented in high-bit-rate switching systems, enabling especially the real-time exchange of moving pictures, for example for a distribution within a dwelling.

2. Description of the Prior Art

Most known selection switching systems have FIFO type buffer 20 memories. In general, the role of these buffer memories is to temporarily preserve the data received in such a way that the control means optimize the switching, namely the transfer of data towards the appropriate output port.

Of course, the capacity of these buffer memories is limited and their space capacity has to be managed. If not, there is a risk of coming up 25 against problems of congestion, blocking and loss of data.

This problem may be resolved by means of a flag encoded on one or more bits, known as an <<almost full>> flag. When the buffer memory has a filling rate above a predetermined threshold (conventionally in the range of N x, where N represents the size of the buffer memory and x the pipeline 30 depth), the "almost full" flag passes to the true value (1 if the <<almost full'> flag is a binary flag). The switching management means take account of this information to process the corresponding buffer memory as a priority. Once this operation is performed, the "almost full" flag is repositioned on the false value (0 if the "almost full" flag is binary).

Another major problem, especially in systems for the asynchronous transfer of packet-based data (or any other type of set of data), is that the switching must be done in packets. It is therefore necessary to manage the reception of these packets and see to their switching.

5 This management is especially important in systems using means to control data between FIFO type memories and FOAM (random access memory) type memories based on burst transfer techniques. According to these techniques, the transfer of data starts and stops as a function of the "almost full" flag.

10 If furthermore the control means work according to a pipeline logic mode it must be noted that this logic needs a predetermined number of supplementary clock strokes or clock periods sequencing the control means and the exchange to provide for the transfer.

If the quantity of information present in the FIFO memory is 15 insufficient, namely if the FIFO has a filling rate below the predetermined threshold N-x, it will not be possible to transfer this quantity of information to the RAM.

This is of course particularly penalizing if the information contained in the FIFO corresponds to the end of a packet. Indeed, in order that the 20 packet may be processed by another element of the switching device, the end of the packet must be transferred from the FIFO to the RAM.

This therefore assumes the existence of relatively complicated systems for the control and management of switching.

The firm ST Microelectronics (trademark) has thus imagined an 25 interface component C101 comprising FlFOs, whose management is done conventionally, namely without the FIFO filling rate flag taking account of the presence of an end of packet marker or end of message marker in the FIFO.

The firm VLSI Technology (registered mark) subsequently devised the implementation of a method for the detection of an end of packet in a FIFO 30 as described in the American patent document US 5 860 119.

However, to date there is no known system that can be used to efficiently manage the transfer of data outside a storage means, for example of the FIFO type, in the context of a packet transfer.

It is a goal of the invention especially to overcome these drawbacks 35 and therefore to provide a method for the optimizing of the use of the storage

means as a function of its filler (the "container'' aspect) and the data received (the "contents" aspect).

More specifically, a goal of the invention is to provide a method of this kind used to efficiently manage the switching of asynchronously received 5 sets of data such as packets.

A particular goal of the invention is to provide a method of this kind that does not introduce any particular complexity, especially in terms of the wiring and operation of the known and available means (FIFO, processors, controllers, switches, etc.).

10 Another goal of the invention is to provide a method of this kind that does not give rise to any excess cost, as compared with systems for managing the filling rate of a FIFO.

SUMMARY OF THE INVENTION

These goals as well as others that shall appear hereinafter are 15 achieved by means of a method for optimizing the use of a storage means implementing at least one full flag modified when the storage space available in said storage means crosses at least one predetermined threshold.

According to the invention, said flag is modified also when the data contained in said storage means fulfill at least one predetermined condition.

20 Thus, the invention relies on a novel and inventive approach to the management of the filling of a means for the storage and generation of corresponding filling rate flags. Indeed, the invention relies especially on the generation of filling rate flags of a storage means as a function firstly of its filling ("container aspect) and secondly of the stored data (the "contents" 25 aspect).

Conventionally, the filling rate of a storage means is assessed by means of a flag that can take a first "true" value when the storage means is substantially full and a second "false" value if not. According to the invention, it is advantageously planned that a filling rate flag of this kind can assume a 30 first "true" value even when the storage value is substantially empty if it contains certain predetermined data. A filling rate flag of this kind is thus associated in a novel and inventive manner not only with a piece of information pertaining to the available space in the storage means ("container" aspect) but also with a piece of information pertaining to the data 35 contained in the storage means ("contents" aspect).

The invention can be applied especially to systems using means for the control of the transfer of data between FIFO type memories and RAM type memories based on burst transfer techniques and in pipeline mode.

Thus, even if the quantity of information present in the FIFO memory is 5 smaller than a predetermined threshold of the filling rate flag, for which the value of the flag is conventionally positioned at "false", it will be possible according to the invention to transfer this quantity of information to another storage means, for example a RAM memory.

It will be noted that this characteristic is particularly advantageous 10 when this information represents the end of a packet. In other words, one of said predetermined conditions is advantageously the reception, in said storage means, of a piece of information on the end of transmission of a set of data.

Said sets of data may belong especially to the group comprising: 15 packets; - protocol units; - frames; - messages.

As already mentioned, the invention can be applied advantageously 20 when said storage means comprises at least one FIFO type memory and especially when said FIFO memory or memories are associated with input ports of switching means.

Advantageously, the modification of said value leads to the transfer of at least one part of said data contained in said storage means.

25 According to a preferred embodiment of the invention, said transfer is activated by pipelined logic control means.

Advantageously in this case, the value of said flag is a function of a reaction time of said control means.

According to a preferred aspect of the invention, the value of said flag 30 is also modified when said storage means is "almost full" in a manner known per se.

In particular, the value of said flag is modified when the filling rate of said storage means is greater than N-x, where: - N represents the size of said storage means;

s - x represents the depth of the pipeline, said transfer relying on a pipelined logic.

According to an advantageous embodiment of the invention, the method comprises the following steps: S - monitoring of the filling rate of said storage means; - modification of the value of said flag if said data supplying the storage means fulfill at least one predetermined condition; - taking into account of said modification of said value leading to a transfer of at least a part of the data contained in said storage means.

10 Advantageously, said invention is implemented in a device comprising at least two storage means as presented here above, such as for example a switching node, the method comprising a step for the transfer of data between two storage means according to a mode combining burst transfer techniques and pipeline techniques as a function of the value of said flag.

15 The invention also relates to devices for optimizing the use of a storage means implementing the method described here above as well as switching devices comprising one (or more) such optimizing devices.

The invention also relates to a signal implemented by this method, this signal representing a filling rate flag of a storage means capable of conveying 20 at least two distinct values, at least one first value associated with a substantially empty state of said storage means and at least one second value associated with a substantially full state of said storage means, and also taking said second value when the data contained in said storage means fulfill at least one predetermined condition.

25 The invention also relates to the switching nodes comprising at least two storage means and a means of transfer between at least two of said storage means and means for the generation of at least one filling rate flag and means to modify the value of said flag when the storage space available in at least one of said storage means exceeds at least one predetermined 30 threshold, and furthermore comprising means to modify the value of said flag when the data elements contained in said storage means fulfill at least one predetermined condition.

Advantageously, a node of this kind comprises a control means that activates the transfer of data between two of said storage means according

to a mode combining the techniques of burst transfer and pipeline transfer according to the value of said flag.

Furthermore, of course, a node of this kind advantageously comprises at least one device to optimize the use of a storage means as described here 5 above.

Finally, the invention relates to the different applications of the method, devices, signal and switching node presented here above and especially the applications of at least one of the fields belonging to the group comprising:

- high bit rate switching; 10 - digital data transmission; - digital data reception; - audio applications; - real-time image transmission.

BRIEF DESCRIPTION OF THE DRAWINGS

15 Other features and advantages of the invention shall appear more clearly from the following description of a preferred embodiment, given as a

simple illustrative and non-restrictive example, and from the appended drawings, of which: - Figure 1 shows a block diagram of the different steps implemented 20 according to the invention during the reception, by storage means, of data fulfilling at least one predetermined condition; Figure 2 illustrates an exemplary embodiment of a device for the generation of a filling rate flag implemented according to the method of Figure 1; 25 - Figures 3 to 9 describe an exemplary implementation of the method in the context of a high bit rate switching system designed for domestic applications. More specifically, Figure 3 illustrates the general architecture of a high bit rate switching system of this kind. Figure 4 shows the different devices connected to the selector switch of such a system. Figure 5 30 illustrates the internal architecture of the selector switch. Figures 6 and 7 provide a more detailed description of the architecture of a block known as

an D-FIFO block of a switch of this kind. Finally, Figures 8 to 9 illustrate special elements of the D-FIFO block.

l

The general principle of the invention relies on the generation of a flag for the filling of a storage means that simultaneously signifies information pertaining to the "container" and to the "contents" of this storage means.

With reference to Figure 1, we shall present the steps implemented S according to the invention during the reception, in the storage means, of data fulfilling a predetermined condition.

We shall consider a FIFO (first-in-first-out) type storage means that is initially in an empty state. The value of a filling rate flag of this FIFO is then positioned (311) at"false". As and when data supplying the storage means to are received, the FIFO filling rate is monitored (312).

During the reception of data by the FIFO, it is furthermore ascertained (313) that this data fulfills at least one predetermined condition. A condition of this kind, according to a preferred embodiment of the invention, is verified if the data received constitute the end of a set of data. For example, during a 15 transmission in burst mode, the data verify a condition of this kind if they constitute an end of packet.

If the data received by the FIFO verifies the predetermined condition or conditions, the FIFO filling rate flag then takes (314) the "true" value. If not, the FIFO filling rate continues to be monitored (312) and, according to a 20 standard method not shown in Figure 1, the FIFO filling rate flag takes the "true" value when the FIFO filling rate is greater than a predetermined threshold. When the value of the FIFO filling rate flag is positioned at "true", then at least a part of the data contained in the FIFO is transferred (315) to an 25 addressee element. An addressee element of this kind may be, for example, a DPRAM (dual port random access memory).

Referring to Figure 2, an exemplary embodiment is now described of a device for the generation of a filling rate flag for a storage means implemented according to the method of Figure 1.

30 A device of this kind comprises a first module 221 to detect the end of packet in the FIFO. A module 221 of this kind is used to detect the presence of the end of a set of data (of the packet or message type for example) in the FIFO. A module 221 of this kind is supplied with control and data signals 220 and generates a flag 224 Eop_in_fifo which takes the first "true" value when

the end of a packet is present in the FIFO and, if not, takes a second "false" value. The device of Figure 2 also comprises a second module 222 for the control of the FIFO, supplied with control and data signals 220 and 5 generating a filling rate flag 223 for the FIFO, called an Almost_full flag. A flag 223 of this kind takes at least two distinct values indicating the FIFO filling rate.

For example, according to a preferred embodiment of the invention implementing a pipelined logic, the flag 223 is a binary flag taking the "true" 10 value when the FIFO filling rate is greater than a predetermined threshold (namely when the FIFO is almost full) and the "false" value when this rate is below the predetermined threshold (namely when the FIFO is not almost full).

This predetermined threshold is equal to N-x, where the value x then represents the number of clock cycles needed for the pipelined logic to react 1S to a given event, and where N is the size of the FIFO, for example N=16.

The device of Figure 2 also comprises a module 225 supplied with the flags Eop_in_fifo 224 and Almost_full 223 and generating a third flag Almost_full 226. A module 225 of this kind therefore performs a logic OR function of the incoming flags 223 and 224 to deliver the final filling rate flag 20 of the FIFO 226. A flag 226 of this kind thus makes possible the activation of the transfer of data contained in the FIFO to an addressee element, firstly when the FIFO is full (with the value of the Almost_full flag at 223 "true") and secondly when it contains an end of packet (value of the Eop_in_fifo flag 224 at "true").

25 Thus, according to the invention, even if the memory FIFO is not "almost full" and contains only information representing an end of packet, it could nevertheless very simply be transferred to a RAM memory for example.

The method of Figure 1 and the device of Figure 2 can be applied in many fields, and can be applied especially in the context of:

30 - high bit rate switching; - the transmission and/or reception of digital data; - audio applications; - real time image transmission.

A preferred field of application of the invention is that of domestic

35 applications for high bit rate transfers but it is clear that the invention could be

implemented in any system requiring the transfer of information, and especially the transfer of packets in pipelined mode. Hereinafter, we shall describe an exemplary system implementing the invention, used to interconnect a plurality of audio, video devices or to transfer information of S the type transferred between a computer and a printer, a scanner or a digital camera. The invention can of course be applied to any other type of system in which it is advantageous to optimize the filling of the storage means and the transfer of data corresponding to the storage means to an addressee 10 element.

The standards IEEE 1394 and IEEE 1355 have already been developed. These standards are respectively adapted to serial communications and to unicast communications. The system presented hereinafter in the document is a switched packet federating system used to 15 achieve high transmission capacities (typically in the range of 1 Gbit) and corresponding to the great need for interfacing the two types of standard mentioned here above.

Figure 3 is a block diagram of a switching node 90 connected to two serial communication buses according to the IEEE standards 1394 and IEEE 20 1 355.

The node shown in figure 3 is also connected to one or more other switching nodes of the switched network to which it belongs.

A switching node comprises: - a switching device 90; and 25 - a dataprocessing apparatus 92 associated with said switching device. As a variant, the data-processing apparatus may itself constitute or include the switching device 90.

The device 90 comprises: 30 - a central processing unit CPU 93; - a ROMtype permanent storage means 94; and - a RAM-type temporary storage means 95 associated with the central processing unit 93, a software architecture being loaded into the means 95 at initialization.

The storage means 95 is able to store data packets of different types, especially: - asynchronous packets of the type conforming to the IEEE 1394 standard, 5 - packets constituting messages in non-connected mode (asynchronous messages), of the type conforming to the IEEE 1355 standard, - control packets of the type conforming to the IEEE 1355 standard.

- stream (isochronous) packets of the type conforming to the IEEE 10 1355 standard.

The type of packets conforming to the IEEE 1355 standard actually have an existence in the component 104 that will be mentioned later, but they are not stored in this form in the RAM storage means 95. It should be noted that the storage means 95 contain the information necessary to generate the 15 IEEE 1355 packets.

The routing of such packets to the storage means 95 coming either from the 1394 bus or from the switched network constituted by IEEE 1355 links will be described in detail later.

The routing of such packets from the storage means 95 until they are 20 transmitted by the switching node, either to the IEEE 1394 bus or to the switched network consisting of IEEE 1355 links, will be described in detail later. These three elements 93, 94 and 95 communicate by means of respective data and address buses referenced 96, 97 and 98, with a block 25 referenced 99 and known to those skilled in the as a bus controller.

This block 99 is especially used to exchange data by means of a main bus 100 with at least one bus-interface component 101. Should the bus 100 be a PCI ("Peripheral Component Interconnect") standard bus, the component 101 may be a component referenced AMCC 5933QC, 30 commercially distributed by the company Applied Micro-Circuits Corporation (registered mark).

The bus 100 may also interconnect other elements, not shown in figure 1, to one another. These elements are themselves provided with a bus interface and are capable, for example, of implementing data-processing 3s functions.

For example, should the bus 100 be a PCI-standard bus, the block 99 is actually a set of PCI components such as the Intel 440LX AGP set, commercially distributed by the INTEL Company.

Hence, the block 99 comprises, for example, an 82443LX component 5 which provides the interface with the memory 95 via the memory bus 98 and with the central processing unit CPU 93 via the local bus 96. The 82443LX component is itself linked to an 82371AB component which provides an interface with the ISA bus 97 linked to the memory 94. An Intel 82093M IOAPIC interrupt controller connected to the central processing unit CPU 93 10 manages the interrupts that may occur in the system.

As shown in Figure 1, the device 90 also includes a bus interface 102 which may be similar to the bus interface 101, thus allowing the data processing apparatus or peripheral 92 to access the switching device.

Such an interface is made, for example, in the form of a SEDNET PCI 15 card commercially distributed by the company SEDERTA under the reference SD-PCI-200 and can be used for the connection thereto of any existing data-processing apparatus designed to operate in conformity with the 1394 standard.

It is clearly possible to use an adapter specific to the data-processing 20 apparatus which has to be connected thereto. The adapter 102 essentially comprises an interface component similar to the bus-interface component 101. Depending on the type of data-processing apparatus, the principal bus 100, as well as the bus-interFace component 101 and buscontroller 25 component 99, may be adapted to the architecture of the type of apparatus.

The same goes for the set of elements, CPU 93, RAM 95 and ROM 94.

As shown in Figure 1, the node according to the invention also includes two interfacing means 103 and 104.

The means 103 is intended to provide the interface between the node 30 90 and the serial communications bus designed to operate according to the IEEE 1394 standard to which the said node is attached.

The interfacing means 103 consists of a set of 1394 PHY/LINK components comprising, for example, a TSB21 LV03A PHY component and a TSB1 2LV01A LINK component that are commercially distributed by Texas 35 Instruments (registered mark), and 1384 standard connectors, for example

those marketed by the Company Molex (registered mark), for example under reference 53462.

The interfacing means 103 include at least one external port designed to be connected to a data-processing apparatus or peripheral that is attached S to the 1394 standard serial communications bus.

The means 103 includes means for counting the number of pulses as a function of a clock signal generated by the control module 107 which will be defined later. This clock signal is synchronized with the "Cycle Master" of the serial communications bus with which it is related, by means of packets ID called cycle-start packets. The frequency of the clock signal generated by the control module 107 is equal-to 24.576 MHz -+ l100 ppm. This signal is represented as being one of the signals denoted ctrl3 in Figure 3.

On each serial communications bus of the network, one of the nodes is called the "Cycle Master" and the "Cycle Master" node of the "root" bus is 15 called the "Net Cycle Master".

Moreover, all the "Net Cycle Masters" exhibit a characteristic specific to them, since they depend on the frequency of the internal clock, on the basis of which the duration of one "reference period" or "cycle" is defined.

The duration of the cycle denoted T is equal to an integer number non', 20 of clock pulses that is or is not common to all the buses and is multiplied by the inverse of the frequency of the internal clock specific to the "Cycle Master" node.

The duration of the cycle T is thus equal to 125 microseconds, for example.

25 When two serial communications buses are linked by a bridge, the "Cycle Master" of one of the buses has to synchronize its cycles with respect to the cycles generated by the "Cycle Master" of the adjacent bus.

Generally, the communications networks formed by serial communications buses allow packet transmission that is synchronized on the 30 basis of the cycles of the buses in question. The buses are, for example, used to transmit audio/video type data packets in real time.

The counting means, such as those of the interfacing means 103 referred to here above, takes for example the form of a register.

The interfacing means 104 mentioned here above consists of an IEEE 35 1355 interface component with three ports. It has especially a component

C113 commercially distributed by the company 4LINKS as well as three interface components LUC1 141MK commercially distributed by the company LUCENT (registered trademark). These components are themselves connected to IEEE 1355 connectors, for example commercially distributed by 5 the firm HARTING (registered trademark). The component C113 is itself made out of an FPGA (field programmable gate array) type programmable

component, namely a component such as the Spartan XCS30XL commercially distributed by the firm XILINX (registered trademark).

The three external ports of the interfacing means 104 are designed to 10 be connected to ports of the same type on another switching node of the switched network, thus enabling the device 90 to communicate with another node of this network.

The device 90 also has a data flow control means 105 that is used to transfer data between the different interface components 101, 103 and 104.

15 This means 105 is formed by programmable logic means executed by an FPGA type component, for example the component referenced VIRTEX, commercially distributed by the company XILINX.

This means 105 especially implements a dual port storage unit 106 used to store data addressed to or coming from the 1355 standard switched 20 network.

The dual port storage unit has a storage capacity of less than 2 Mbits and is made for example in a form of a 32-bit access DPRAM type memory.

The initials DPRAM refer to "dual port random access memory".

The storage unit 106 has a plurality of memory zones managed as 25 individual FIFO (first-in first-out) type memories.

A memory zone of this kind corresponds to a memory in which the data elements are read in the order in which they are written beforehand.

These memory zones each comprise a read pointer and a write pointer that are associated with each other.

30 Since each memory zone is managed as a FIFO type memory, its filling and emptying can be done at the same time and independently. This desynchronizes the data read and write operations, performed by aswitching unit 108 that will be defined here below, from the data read and write operations performed by the control module 107.

Indeed, the occupancy rate of the memory zone considered is managed circularly and it is known, at all times, whether the data contained in a memory zone have been read or not. When these data have been read, then new data can be written in their place.

5 The dual port memory unit is, so to speak, a queue for the packets and the storage function is carried out independently, according to the port by which the packets reach the memory unit.

In general, all the isochronous or asynchronous data coming from the switched network is stored in the storage unit 106.

10 This storage is temporary for the asynchronous data packets (namely packets constituting a message transmitted in non-connected mode) and for the control packets which are then transferred into the RAM storage means 95 for storage for a longer duration.

However, the isochronous data packets (stream type packets, namely 15 packets transmitted in connected mode) are stored only in this storage unit 106 before being transmitted on the communications bus to which the switching node 90 is connected or on the switched network.

This can be explained by the fact that this type of data must be transferred as speedily as possible from the switched network to the bus and 20 must therefore be stored in an easily and swiftly accessible storage means.

Similarly, the isochronous data packets that come from the communications bus to which the switching node 90 is connected and that are designed for the switched network, are stored only in the storage unit 106 and not in the storage means 95 for the same reasons as those referred to 25 here above.

Thus, as shown in Figure 1, the data flow control means 105 comprises several other elements, including a control module 107 (already mentioned here above) that carries out a function of checking the storage unit 106, a switching unit 108 (already mentioned further above) in 30 communication with the interfacing means 104, with the storage unit 106 and with the control module 107 as well as a unit for arranging the data packets 109 that is linked to the control module 107.

It will also be noted that the control module 107 communicates with the interfacing means 103 and 104 as well as with the bus interface 35 component referenced 101.

The control module 107 has the function of multiplexing the read or write accesses to registers of other modules from the main bus referenced 100. The module 107 also controls the bus interface component 101 for the 5 read and write operations on the main bus 100, including especially the burst mode. The control module 107 is also responsible for activating interruptions on the main bus 100 as a function of particular communications events.

This module exchanges data elements with the component 101 on an 10 additional bus 110 (known as an add-on bus) following the control signals referenced ctrl1.

As indicated here above, the module 107 is responsible for controlling the storage unit 106 with respect to the read and write operations in FIFO mode, in the special case where the bus interface component 101 is an 15 AMCC, by means of a data bus 111 and control signals ctr/2.

The interfacing means 103 contain FIFO type memories used during the transfer of data packets of the type conforming to the IEEE 1394 standard. It has two transmission FIFO memories known as an ATE (asynchronous transfer FIFO) and an ITF (isochronous transfer FIFO) and 20 one reception FIFO memory known as a GRF (general receive FIFO). These FIFO memories are extensively described in the literature associated with the component LINK TSB12LVO1A.

The control module 107 and the interfacing means 103 manage the data transfer on a bus 1 12 according to the control signals cttl3.

25 Furthermore, the control module 107 controls the switching unit 108 by means of control signals ctr/4 in order to transfer data from the switching unit to the storage unit 106 by means of a data bus 113 and vice versa.

The switching unit 108 is connected to the interfacing unit 104 by means of a data bus 114 and control signals ctrl5.

30 The data packet arranging unit 109, also known as an SAR (segmentation and reassembling) unit, informs the control module 107 of the next data packet or packets to be transmitted, by means of control signals ctr/6.

Furthermore, the SAR unit 109 verifies the reception of the data packets and manages the allocation and the releasing of memory zones (known as buffers) of the storage unit 106.

The control signals ctrl7 exchanged between the interfacing means s 104 and the control module 107 comprise especially the clock signals regenerated from the reception of the packets 1355 on each of the three ports of the interfacing means 104.

A quartz crystal at 49.152 MHz (not shown) is connected both to the means 104 for the sending of the 1355 standard packets and to the control 10 module 107 which generates a clock signal at 24.576 MHz i 100 ppm, firstly for the segmentation and reassembling unit 1 09 in order to set the rate of the 1355 standard packet transmission and secondlyfor the interfacing means 103 to set the 1394 standard packet transmission.

Figure 4 shows a detailed diagrammatic view of the data flux control 15 means 105 and the interface 104 illustrated with reference to Figure 3 as well as their interconnections.

Some details on the serial interface 104 will provide for an understanding of how the packets are multiplexed on the data bus 114.

The serial interface 104 comprises especially: 20 - FIFO control means 120 described here above with reference to Figure 3; - three input FlFOs 121 (InPort0_FIFO), 122 (InPort1_FIFO) and 123 (InPort2_FIFO); - a multiplexer 127; and 25 output FlFOs 124 (OutPortO_FIFO), 125 (OutPort1_FIFO) and 126 (OutPort2_FIFO).

The FlFOs 121, 122 and 123 are used to store incoming packets while the FlFOs 124 to 126 are used to store outgoing packets.

A pair of FlFOs is connected to each port of the IEEE 1355 interface 30 104. Thus,for example: - the FlFOs 121 and 124 are used for the port 0; the FlFOs 122 and 125 for the port 1; and - the FlFOs 123and 126 for the port 2.

The data bus 114 illustrated with reference to Figure 3 can be 35 subdivided into two buses in Figure 4:

- a bus 44 RxDI[17:0] of links in data reception designed for the switching unit 108 and transmitted by the interface 104; and - a bus 41 TxDI[17:0] of links in transmission of data from the switching unit 108 to the interlace 104.

5 After they have been written in one of the input FlFOs 121, 122 and 123, the incoming packets are multiplexed through the multiplexer 127 before they are sent to the switching unit 108 through the bus 44.

The outgoing data from the switching unit 108 are sent through the data bus 41 to be stored in one of the output FlFOs 124, 125 or 126.

10 It may be recalled that the data flux control means 105 comprises especially: - the control module 107; - the switching unit 108; and - the dual port memory unit or DPRAM 106.

15 The control signal Ctrl5 illustrated with reference to Figure 3 can be split up into three signals in Figure 2: - a control signal 51; - a control signal 43 TxFIFOfu11[0:2]; and - a control signal 42 Write TxFlFO[0:2].

20 The control signals 42 TxFIFOfull[O:2] and Write TxFlFO[O:2] 43 are used by the control means 120 of the FIFO to manage the transfer of the data packets between the switching unit 108 and a serial link interface 104 through the data buses 44 and 41.

The processing of the control signals in the switching unit 108 will be 25 described further below with reference to Figure 5.

The signal Ctrl4 illustrated with reference to Figure 3 between the switching unit 108 and the control module 107 can be split up into at least four signals in Figure 4: - two control signals 53 and 54; 30 - a control signal 45a IntRxTxEOP[1: O]; - a data signal 45b IntRx_TX[31: 0].

The signal 45b is a data bus connecting the elements 106, 107 and 108. The control module reads the packet headers from this bus 45b.

The control signals 53, 54 and 45a are used for the management of data transfer 45b IntRx_T)<[31: O] between the dual port memory 106 and the switching unit 108.

In certain cases, especially during the packet header processing, the 5 data of the packets are sent to the control module 107 rather than to the storage unit 106 for subsequent analysis.

The data bus 45b is shown in Figure 3 by the data bus 113.

Figure 5 shows an electronic diagram of the switching module 108 of Figure 2.

l0 The switching module 108 comprises especially: - an arbitration means 60; - a cycle generation means 20; - means responsible for the reception and transmission of data from or to the interface 104 (namely data coming from or 15 addressed to an IEEE 1355 switched network); and - means responsible for the reception of data coming from the DPRAM memory 106 (namely data coming from an IEEE 1394 bus); and - means responsible for sending data to the DPRAM memory 20 106 (namely data sent to an IEEE 1394 bus).

The means responsible for the reception and sending of data from or to the interface 104 comprise especially: - a header modification means 18; - a means 19 for the analysis of headers at reception; 25 - two reception FlAMs 15 and 16 arranged as FlFOs; and - a means 17 for controlling reception FlFOs 15 and 16.

The means responsible for data reception from the memory DPRAM 106 comprise especially: - four input FIFOs 9, 1 0,1 1 and 1 2; 30 - one means 130 for the control of the input FlFOs; - one multiplexer 50; and - one transmission header analysis means 13.

The means responsible for the transmission of data to the DPRAM memory 106 comprise especially: 35 - three assembling memories 22, 23 or 24;

- three output FlFOs 25, 26 and 27; - a means of control 84 of the output FlFOs; and - a multiplexer 28.

These elements, which form part of the switching module 108, are 5 connected by linking elements described here below. It can be seen nevertheless that most of the exchanges are made around the arbitration means 60 with the use of two main data buses TxBus 70 and RxBus 80 whose accesses are managed by the arbitration means 60.

The use of the two internal buses, the transmission bus TxBus 70 and 10 the reception bus RxBus 80 which are used to process the data transfers between the ports shall now be described in detail.

The outgoing packets towards the bus 41 are sent through the transmission bus TxBus 70.

The outgoing packets towards the bus 45 are sent through the internal IS reception bus RxBus 80.

The arbitration means 60 is responsible for managing write accesses on the bus TxBus 70 controlling the opening: - three-state registers 1, 2, 3 and 4 by means of signals 40 Open TxTS[O:3Lon Rx for data coming from the input FlFOs 9, 20 10, 11 and 12; and - three-state registers 14 by means of control signals OpenRxTS_on Rx 33 for the data coming from the memory 16.

The operations of reading of the bus TxBus 70 for writing to an output port of the interface 104 are managed by the arbitration means 60 as a 25 function of the control signal to the FlFOs associated with each port, namely the signal 43 TxFlFOfu11[0:2] and the signal 42 Write TxFlFO[0:2].

The arbitration means 60 also manages the write access towards the bus RxBus 80 in controlling the opening: - of three-state registers 5, 6, 7 and 8 through signals 39 30 Open TxTs[0:3Lon Rx for data coming from the input FlFOs 9, 10,11 and 12; and - a three-state register 21 through the control signals 34 OpenRxTs_on Rx for the data coming from the memory 15.

The arbitration means 60 also performs the operations of data 35 reading on the RxBus 80 for writing towards one of the assembly

buffers 22, 23 or 24. The assembly buffer is used as a buffer for the conversion of data between the bus 80, on which the data are expressed on 18 bits (16 data bits and 2 check bits) and the O_FIFOs 25, 26 and 27 in which the data is expressed on 34 bits) (32 data bits 5 and 2 check bits).

These bus sizes are related to physical constraints. The module 84 sends the arbitration means 60 a control signal 83 Rx FlFOfu11[0:2], indicating the degree of filling of the FlFOs 25, 26 and 27. The arbitration means 60 generates a control signal 35 WnteO_FlFO[2:0] sent to a control 10 module 84 of the output FlFOs as a function of the degree of filling of the FlFOs 25, 26 and 27.

The arbitration means 60 for data multiplexing on the transmission bus TxBus 70 and the reception bus RxBus 80 uses signals 46 with a cycle EN_cycle[0:21. It is the cycle generation means 20, for example a Johnson 1S counter, that generates these signals 46.

The processing of incoming data shall now be described in detail according to the origin of these data, namely: - the bus 44; - the bus 45.

20 The incoming data coming from the bus 44 RxDI[17:0] or the bus 45 will be routed towards the selection switch to go: - towards the bus 41 TxD0[17:0] or towards the bus 44, namely in the direction of the interface 104; or - towards the bus 45, namely in the direction of the DPRAM 106.

25 The processing of the incoming data from the bus 44 shall now be described. The data exchanges on the bus 44 are managed through the header modification means 18 and the FIFO control means 120 of the serial interface, by means of the control signals 51. The control signals 51 include 30 a write signal sent towards the header modification means 18 and signals to control the flux of the means 18, each corresponding to input ports of the interfacing means 104.

The pieces of packets incoming from the bus 44 first of all reach a header modification means 18 for a processing of packet headers.

35 The pieces of packets are then stored:

- in the memory 15 when they are addressed to the reception bus 80 RxBus; and - in the memory 16 when they are addressed to the transmission bus 70 TxBus.

5 When they are sent to the two buses, the pieces of packets are sent to the two buses simultaneously to be stored in two storage means simultaneously. Similarly, the reception FIFO control means 17 control the storage operations in two memories 15 and 16.

to The memories 15 and 16 are dual port memories subdivided into three independent zones, each managed as a FIFO.

The synchronous signals are managed at a certain rate corresponding to a succession of phases constituted by four clock cycles.

In a four-cycle phase, during each of the first three clock cycles of the 15 phase, both a write operation and a read operation are performed towards two addresses of each of the RAMs (volatile memories) 15 or 16. These addresses respectively point towards: - the last element (tail) of one of the FlFOs in each of the RAMs 15 and 16; and 20 - the first element (head) of one of the FlFOs in each of the RAMs 15 and 16.

No read or write operation towards the RAM 15 and 16 is performed during the fourth clock cycle in a four-cycle phase.

Each effective FIFO read operation (defined when the output signal 32 25 Rx[Lread is activated during a cycle and followed by an input signal AllData used[i] activated during a cycle, i corresponding to a number of the input FIFO) modifies the address pointing to the FIFO header.

Effective FIFO write operations (based on the same mechanism as the read operations herein using the signal 52 illustrated with respect to Figure 3) 30 modify the address pointing to the tail of the FIFO.

Thus, during three cycles, each FIFO part corresponding to each of the input ports is processed: the data writing operations performed by the header modification means 18 are sequentially addressed towards the corresponding parts 15 and 16, each of the pieces of packets entering each 35 of the input ports 121, 122 and 123 of the interface 104.

Similarly, the data elements read from the memories 15 and 16 are processed respectively by the buses RxBus 80 and TxBus 70.

The reception FIFO control means 17 is responsible for the reading and effective writing of the FlFOs contained in the memories 15 and 16.

5 The control signal 52 informs the header modification means 18 that a FIFO is full in one of the memories 15 or 16 and that there is also a write request for a FIFO in one of the memories 15 or 16.

The reception FIFO control means informs the arbitration module 60 that a new data element has been read from one of the memories 15 or 16 10 through the signal 32 Rx[0:2]read.

The same data elements are read at each four-cycle phase when they are not read effectively by placing them simply, either on the bus RxBus or on the bus TxBus or on both of the buses as a function of the routing of the packet. 15 Thus, the same data elements are presented every four cycles until they have been really read by the destination or destinations.

The arbitration means 60 manages the opening of the three-state register 14 through the control signals 33 OpenRxTs_onTx to place the data that have been read of the memory 16 on the transmission bus TxBus 70.

20 The means 60 also manages the opening of the three-state register 21 through the control signals 34 OpenTxTs_onRx to place the data that have been read of the memory 15 on the reception bus RxBus 80.

The arbitration means 60 also manage the control of the signals allRxData_used[0:2]to inform the control means 17 of the reception FlFOs 25 that the next data element will be read on a corresponding part in one of the memories 15 or 16.

The received packet header analysis means 19 control the shape of the signal 47 towards the arbitration means 60.

When a new packet coming from one of the input ports 121, 122 or 30 123 is processed by the header modification means 18, the signal 47 Rx[0:21Want[0:3] provides for the request of a connection: - to one of the output ports of the interface 104 through the multiplexed bus 41; or - to one of the internal FlFOs 25, 26 or 27 through the 35 multiplexed bus 45.

When the end of the packet is processed by the header modification means 18, the signal 47 Rx E O. P[0:2] informs the arbitration means 60 of the end of a connection. It will be noted that the header modification means 18 sends a signal 5 representing a piece of routing information to the reception header analysis means 19.

With respect to connection and disconnection with the IEEE 1355 serial interface, the arbitration means 60 manages the signals 81 Rx[0:2L connected sent to the reception FIFO control means 17 to indicate 10 the status of the connection associated with each port.

Similarly, the arbitration means 60 manages the signals 82 Tx[0:2L connected to the control means 1 Goof the input FlFOs 9, 10, 11 and 12 for the data coming from the DPRAM 106.

The data exchanged on the bus 45 are managed: 15 - by means 84 for the control of the output FlFOs 0_FIF O and the control module 107 by means of the signal 53; and - by the means 13 for the control of the input FlFOs l-FIF O and the control module 107 by means of the signal 54.

The multiplexer 28 authorizes the selection of an output FIFO 0_FIF O 20 among the three FlFOs 25, 26 or 27 for operations of reading FlFOs containing data intended for the dual port storage memory 106. This selection operation is managed by the output FIFO 0_FIF O control means 84 through a signal 85.

Furthermore, the input FIFO I FIR O control means 130 control write 25 operations of the storage memory 106 to one of the four input FlFOs I FIR O referenced 9, 10, 11 or 12 through the signals 90.

This is only the case for the bus 42 where the control signals 43 and 42 attached to the storage means of the output ports are directly connected to the arbitration means 60.

30 In other words, the bus 41 is the only bus whose control signals (42 and 43) are directly connected to the arbitrator 60.

The processing of incoming data from the bus 45 shall now be described in detail.

The packet pieces coming from the bus 45 are demultiplexed towards each input FIFO 9, 10, 11 and 12. Thus, four packets (one per input FIFO) can be processed simultaneously.

Each input FIFO is connected to two internal buses 70 and 80 through S the three-state registers 1 to 8.

The arbitration means 60 is responsible for managing: - the write access on the bus TxBus 70 alternately controlling the opening of the threestate registers 1 to 4 through the signals OpenTxTs[0:3LonTx referenced 40, each of the registers 1 to 4 10 being assigned to an input FIFO 9 to 12; and - the write access on the bus RxBus referenced 80 alternately controlling the opening of the three-state registers 5 to 8 though the signals 39 OpenTxTs[0:3LonRx, each of the registers 5 to 8 being assigned to an input FIFO 9 to 12.

15 The write operations on the bus RxBus 70 are independent of the write operations on the bus TxBus 80.

The arbitration means 60 also generate control signals 37 allTxData used[O:3] that permit the reading on one of the input FlFOs 9 to 12 through the control means of the input FIFO 130.

20 The control means 130 of the input FlFOs informs the arbitration means 60 of the success of a read operation performed by one of the input FlFOs through the control signal Tx[0:3LRead referenced 38 The packet header data elements are multiplexed by a multiplexer 50 of one of the output FlFOs 9 to 12 to be sent to the header analysis means 25 13.

The transmitted packet header analysis means 13 analyzes the data coming from the input FlFOs 9, 10, 11 and 12 to generate the signal 36 Tx[0:3] Want[0:3] addressed to the arbitration means 60.

When a new packet is processed in one of the input FlFOs 9 to 12, the 30 signal 36 Tx[0:3] Want[0:3] requests a connection: - to one of the output ports of the interfacing means 104 by a multiplexed bus 41; and - to one of the output FlFOs 25, 26 or 27 through a multiplexed bus 45.

l

When the end of the packet is processed in one of the input FlFOs 9 to 12, the signal 36 TxEOP[0:3] is used to inform the arbitration means 60 of an end of connection.

Figure 6 shows the architecture of the D-FIFO block shown in figure 5.

5 The O_FIFO block implements three output FlFOs 25, 26 and 27, one for each internal port. An output FIFO O_FIFO will be described further below with reference to figure 7.

Control signals 203 coming from the reception bus 80 Rx_bus are processed through the RXBUS20F logic means 204. These logic means are 10 responsible for addressing one of the three FlFOs 25 to 27, depending on the control signals 203. The RXBUS20F logic 204 is also in charge of converting the data from 16 bits to 32 bits. This kind of conversion is achieved through the we_low and we_high commands of the FlFOs. An additional function of this logic is that of decoding the eop/eom (end of packeVend of message) 15 flags coming from the reception bus 80 Rx_bus, and generating the we_eop command 228 of the FlFOs.

The multiplexer 28 feeds the intrx_tx_data bus 45 with data from one o, the FlFOs, depending on the intrx_datarequest[2:0] signal. The multiplexer 28 also detects the reading of an end of packet or an end of message 20 (eop/eom) from the FlFOs so as to generate the signal eop_at_out ins 205.

Figure 7 shows the architecture of an output FIFO O_FIFO 25, 26 or 27. An O_FIFO is made with two counters 206 and 207, a dual port RAM 210 to 212, a flag generator 208 that shall be described in greater detail with 25 reference to Figure 9, and an end of packet or end of message (eop/eom) detector 209 which will be described in greater detail with reference to Figure 8. The write counter 206 is used to generate write addresses in the dual port RAMs 210 to 212, when the data come by the reception bus 80 Rx_bus.

30 This counter 206 is controlled by the push signal 213 generated by the RXBUS20F logic 204 as shown in Figure 6. This push signal is generated whenever two 1 6-bit words and one 2-bit control word are written in the dual port RAMs, namely whenever a 34-bit word is written.

The read counter 207 is used to generate read addresses in the dual port RAMs 210 to 212 when data is requested through the intrx_datarequest signal 214.

The almost full signal 226 is obtained through a logic "OR" between S the almost_full signal generated by the flag generator flag_gen 208 and the signal eop_in_fffo generated by the end of packet detection module eop_detect 209 as illustrated here above with reference to figure 2.

Figures 8 and 9 provide a more detailed illustration of the possible embodiments of the end of packet (cop) detector 209 and of the flag 10 generator flag_gen 208.

The module eop_detect 209 is a counter 227 that counts the number of occurrences of and end of packet or end of message (eop/eom) in the FIFO. This counter 227 is incremented when the signal we_eop 228 is validated, namely during a write operation in the 32 and 33 bit dpram 212.

15 This counter 227 is decremented when the signal eop_at out_pins 205 is validated. A signal 205 of this kind is generated by the multiplexer when an end of packet or end of message (eop/eom) is read from the FIFO.

It is clear that when both conditions are true (namely when eop_at outpins 205 and whop 228 are validated simultaneously) the 20 counter remains unchanged.

As illustrated in Figure 9, the flag generator 208 is also a counter. It counts the number of sets of 34 bits in the O_FIFO.

Claims (39)

WHAT IS CLAIMED IS:

1. A method for optimizing the use of a storage means implementing at least one filling rate flag, the value of said filling rate flag being modified when the storage space available in said storage means crosses at least one 5 predetermined threshold wherein the value of said flag is modified also when the data contained in said storage means fulfill at least one predetermined condition.

2. A method according to claim 1, wherein one of said predetermined condition is the reception, in said storage means, of a piece of information on 10 the end of transmission of a set of data.

3. A method according to claim 2, wherein said sets of data belong to the group comprising: - packets; - protocol units; 15 - frames; - messages.

4. A method according to any of the claims 1 to 3, wherein said storage means comprises at least one FIFO type memory.

5. A method according to claim 4, wherein said FIFO memory or 20 memories are associated with input ports of switching means.

6. A method according to any of the claims 1 to 5, wherein said modification of said value leads to the transfer of at least one part of said data contained in said storage means.

7. A method according to claim 6, wherein said transfer is activated by 25 pipelined logic control means.

8. A method according to claim 7, wherein the value of said flag is a function of a reaction time of said control means.

9. A method according to any of the claims 1 to 7,-wherein the value of said flag is modified when said storage means is "almost full".

30

10. A method according to claim 8, wherein the value of said flag is modified when the filling rate of said storage means is greater than N-x, where: - N represents the size of said storage means; - x represents the depth of the pipeline, said transfer relying on a 35 pipelined logic.

11. A method according to any of the claims 1 to 10, comprising the following steps: - the monitoring of the filling rate of said storage means; - the modification of the value of said flag if said data supplying the S storage means fulfill at least one predetermined condition; - the taking into account of said modification of said value leading to a transfer of at least a part of the data contained in said storage means.

12. A method according to any of the claims 1 to 11, comprising a step for the transfer of data between two storage means according to a mode 10 combining burst transfer techniques and pipeline techniques as a function of the value of said flag.

13. A device for optimizing the use of a storage means, comprising means for the generation of at least one filling rate flag, and means for the modification of the value of said flag when the storage space available in said 15 storage means crosses at least one predetermined threshold, wherein the device furthermore comprises means to modify the value of said flag when the data contained in said storage means fulfill at least one predetermined condition.

14. A device according to claim 13, wherein one of said 20 predetermined conditions is the reception, in said storage means, of a piece of information on the end of transmission of a set of data.

15. A device according to any of the claims 13 and 14, wherein said storage means comprises at least one FIFO type memory.

16. A device according to claim 15, wherein said FIFO memory or 25 memories are associated with input ports of switching means.

17. A device according to any of the claims 13 to 16, comprising pipelined logic control means providing for the transfer of at least one part of said data contained in said storage means, when said value is modified.

18. A device according to claim 17, wherein the value of said flag is a 30 function of a reaction time of said control means.

19. A device according to any of the claims 13 to 18, wherein the value of said flag is modified when said storage means is "almost full".

20. A switching device comprising means for optimizing the use of an 35 internal storage means,

said optimizing means comprising means for the generation of at least one filling rate flag, and means for the modification of the value of said flag when the storage space available in said storage means crosses at least one predetermined threshold, and/or when the data contained in said storage S means fulfill at least one predetermined condition.

21. A switching device according to claim 20, comprising a device for optimizing the use of a storage means according to any of the claims 13 to 20.

22. A switching device according to any of the claims 20 and 21, 10 wherein one of said predetermined conditions is the reception, in said storage means, of a piece of information on the end of transmission of a set of data.

23. A switching device according to any of the claims 20 to 22, wherein said storage means comprises at least one FIFO type memory.

15

24. A switching device according to any of the claims 20 to 23, comprising pipelined logic control means providing for the transfer of at least one part of said data contained in said storage means, when said value is modified.

25. A switching device according to claim 24, wherein the value of 20 said flag is a function of a reaction time of said control means.

26. A switching device according to any of the claims 20 to 25, wherein the value of said flag is modified when said storage means is "almost full".

27. A signal representing a filling rate flag of a storage means capable 25 of conveying at least two distinct values, at least one first value associated with a substantially empty state of said storage means and at least one second value associated with a substantially full state of said storage means, wherein said signal also takes said second value when the data contained in said storage means fulfill at least one predetermined condition.

30

28. A signal according to claim 27, wherein one of said predetermined conditions is the reception, in said storage means, of a piece of information on the end of transmission of a set of data.

29. A signal according to one of the claims 27 and 28, wherein said storage means comprises at least one FIFO type memory.

30. A signal according to one of the claims 27 to 28, wherein the modification of said value leads to the transfer of at least one part of said data contained in said storage means.

31. A signal according to one of the claims 27 to 30, wherein the 5 value of said flag is a function of a reaction time of said control means.

32. A signal according to any of the claims 27 to 31, wherein the value of said flag is modified when said storage means is "almost full".

33. A signal according to claim 32' wherein the value of said flag is modified when the filling rate of said storage means is greater than N-x, 10 where: - N represents the size of said storage means; - x represents the depth of the pipeline, said transfer relying on a pipelined logic.

34. A switching node comprising at least two storage means and a 15 means of transfer between at least two of said storage means and means for the generation of at least one filling rate flag and means to modify the value of said flag when the storage space available in at least one of said storage means exceeds at least one predetermined threshold, wherein the node furthermore comprises means to modify the value of said 20 flag when the data elements contained in said storage means fulfill at least one predetermined condition.

35. A switching node according to any of the claims 34 and 35, comprising a control means activating the transfer of data between two of said storage means according to a mode combining the techniques of burst 25 transfer and pipeline transfer according to the value of said flag.

36. A switching node according to any of the claims 34 and 35, comprising at least one device for optimizing the use of a storage means according to any of the claims 13 to 20.

37. An application of the method according to any of the claims 1 to 30 12 to at least one of the fields belonging to the group comprising:

- high bit rate switching; - digital data transmission; - digital data reception; - audio applications; 35 - real-time image transmission.

38. Apparatus substantially as hereinbefore disclosed with reference to and as shown in any one of the accompanying drawings.

5

39. A method substantially as hereinbefore disclosed with reference to and as shown in any one of the accompanying drawings.