FR2820845A1 - METHOD OF OPTIMIZING THE USE OF A STORAGE MEDIA, SWITCHING DEVICE, SIGNAL, AND CORRESPONDING APPLICATIONS - Google Patents

Abstract

The invention relates to a method for optimizing the use of a storage means, implementing at least one filling indicator modified when the storage space available in said storage means exceeds at least one predetermined threshold. According to the invention, said indicator is also modified when the data contained in said storage means fulfill at least one predetermined condition.

Description

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 Method for optimizing the use of a storage medium, switching device, signal, and corresponding applications.

 The field of the invention is that of the implementation of storage means, in particular, but not exclusively, in the context of switching, transmission and / or reception systems of digital data.

 More specifically, the invention relates to the optimization of the use of storage means supplied with received data and having to be transferred to at least one recipient element.

 These storage means can in particular be FIFO memories (First In First Out) associated with input ports of a switching device ensuring the transfer of data sets, for example in the form of packets. In particular, such storage means can be implemented in high speed switching systems, in particular allowing the real-time exchange of moving images, for example for distribution in the context of a dwelling.

 Most known switching systems include buffer memories, of the FIFO type. In general, the role of these buffers is to temporarily store the data received, so that control means optimize the switching, that is to say the transfer of data to the appropriate output port.

 Of course, the capacity of these buffer memories is limited, and it is necessary to manage their size. Otherwise, there is a risk of encountering problems of congestion, blocking, or loss of data.

 This problem can be solved using an indicator coded on one or more bits, called almost full (in French, almost full). When the buffer has a filling rate greater than a predetermined threshold (conventionally of the order of Nx, where N represents the size of the buffer and where x the pipeline depth), the almost full indicator goes to the true value (1 if the "almost full" indicator is a binary indicator). The switching management means take this information into account, to

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 give priority to the corresponding buffer memory. Once this operation has been carried out, the almost full indicator is repositioned at the value "false" (0 if the "almost full" indicator is binary).

 Another important problem encountered, in particular in the context of asynchronous data transfer systems grouped in packets (or in any other type of data set), is that the switching must be carried out in packets. It is therefore necessary to manage the reception of these packets, and to ensure the switching.

 This management is all the more important in the case of systems using means for controlling the transfer of data between memories of FIFO type and memories of RAM type (in English "Random Access Memory") based on transfer techniques in burst. According to these techniques, the data transfer starts and stops according to the "almost full" indicator.

 If, moreover, the control means operate according to a pipeline logic mode (in French "cascade logic"), it should be noted that this logic needs a predetermined number of additional clock ticks, or periods of clock, sequencing the control means and the exchange, to ensure the transfer.

 If the quantity of information present in the FIFO memory is insufficient, that is to say if the FIFO has a filling rate below the predetermined threshold Nx, it will not be possible to transfer this quantity of information to the memory RAM.

 This is, of course, particularly disadvantageous if the information contained in the FIFO corresponds to the end of a packet. Indeed, for this packet to be processed by another element of the switching device, the end of the packet must be transferred from the FIFO to the RAM memory.

 This therefore requires relatively complex systems for controlling switching management.

 The company ST Microelectronics (registered trademark) has thus imagined a Clou interface component, comprising FIFOs, the management of which is carried out in a conventional manner, that is to say without the indicator of filling rate of

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 FIFO takes into account the presence of an end of packet or end of message marker in FIFO.

 The company VLSI Technology (registered trademark) then imagined implementing a method for detecting an end of packet in a FIFO, as described in the US patent document US 5,860,119.

 However, to date there is no known system for efficiently managing the transfer of data outside of a storage means, of the FIFO type for example, within the framework of a packet transfer.

 The invention aims in particular to overcome these drawbacks, and therefore to provide a method for optimizing the use of a storage means, as a function of its filling (container aspect) and of the data received (content aspect).

 More specifically, an object of the invention is to provide such a method, which makes it possible to efficiently manage the switching of data sets, such as packets, received asynchronously.

 A particular objective of the invention is to provide such a method, which does not introduce any particular complexity, in particular in terms of cabling and exploitation of known and available means (FIFO, processors, controllers, switches, etc.) .

 Another objective of the invention is to provide such a method, which does not entail any particular additional cost, compared with the filling rate management systems of a FIFO.

 These objectives, as well as others which will appear subsequently, are achieved using a method for optimizing the use of a storage means, using at least one filling indicator modified when the storage space available in said storage means exceeds at least a predetermined threshold.

 According to the invention, said indicator is also modified when the data contained in said storage means meet at least one predetermined condition.

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 Thus, the invention is based on a completely new and inventive approach to managing the filling of a storage means and the generation of corresponding filling flags. Indeed, the invention is based in particular on the generation of filling indicators for a storage means, as a function of its filling (container aspect) on the one hand and of the stored data (content aspect) on the other hand.

 Conventionally, the filling rate of a storage means is evaluated using an indicator which can take a first "true" value when the storage means is substantially full, and a second "false" value in the opposite case. According to the invention, it is advantageously provided that such a filling indicator can take the first "true" value, even when the storage means is substantially empty, if it contains certain predetermined data. Such a filling indicator is thus associated, in a new and inventive manner, not only with information relating to the space available in the storage means ("container" aspect) but also with information relating to the data contained in the means of storage ("content" aspect).

 The invention is particularly applicable to systems using means for controlling the transfer of data between memories of the FIFO type and memories of the RAM type, based on techniques of transfer in burst (in English "burst") and in pipeline mode. .

 Thus, even if the quantity of information present in a FIFO memory is less than a predetermined threshold of the filling indicator, for which the value of the indicator is conventionally positioned at "false", it will be possible, depending on the invention, to transfer this quantity of information to another storage means, for example a RAM memory.

 It will be noted that this characteristic is particularly advantageous when this information is representative of the end of a packet. In other words, one of said predetermined conditions is advantageously the reception, in said storage means, of information on the end of transmission of a

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 dataset.

 Said data sets can in particular belong to the group comprising: packets; protocol units; frames; messages.

 As already mentioned, the invention finds in particular an advantageous application in the case where said storage means comprises at least one memory of the FIFO type, and in particular when the said FIFO memory or memories are associated with input ports of switching means .

d'au moins une partie desdites données contenues dans ledit moyen de stockage. Advantageously, the modification of said value results in the transfer

at least part of said data contained in said storage means.

 According to a preferred embodiment of the invention, said transfer is activated by means of cascade logic control (in English "pipelined logic").

 Advantageously, in this case, the value of said indicator is a function of a reaction time of said control means.

 According to a preferred aspect of the invention, the value of said indicator is also modified when said storage means is almost full (in English "almost full"), in a manner known per se.

 In particular, the value of said indicator is modified when the filling rate of said storage means is greater than N-x, where: N represents the size of said storage means; x represents the depth of the pipeline, said transfer being based on a cascade logic.

 According to an advantageous embodiment of the invention, the method comprises the following steps: monitoring the filling rate of said storage means; modification of the value of said indicator if said data

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 supplying the storage means meet at least one predetermined condition; taking into account of said modification of said value, resulting in a transfer of at least part of the data contained in said storage means.

 Advantageously, when the invention is implemented in a device comprising at least two storage means as presented above, such as, for example, a switching node, the method comprises a step of transferring data between two means storage in a mode combining burst and pipeline transfer techniques depending on the value of said indicator.

The invention also relates to devices for optimizing the use of a storage means implementing the method described above, as well as switching devices comprising one (or more) such an optimization device.

 The invention also relates to a signal implemented by this method, this signal being representative of an indicator for filling a storage means capable of conveying at least two distinct values, at least one first value associated with a substantially empty state of said storage means, and at least a second value associated with a substantially full state of said storage means, and also taking said second value when the data contained in said storage means meet at least one predetermined condition.

 The invention also relates to the switching nodes comprising at least two storage means and a transfer means between at least two of said storage means, and means for generating at least one filling indicator, and means for modifying the value of said indicator when the storage space available in at least one of said storage means exceeds at least a predetermined threshold, and further comprising means for modifying the value of said indicator when the data contained in said storage means fill in the minus one condition

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 predetermined.

 Advantageously, such a node comprises a control means activating the transfer of data between two of said storage means according to a mode combining the techniques of burst and pipeline transfer according to the value of said indicator.

 Furthermore, of course, such a node advantageously comprises at least one device for optimizing the use of a storage means as described above.

la transmission de données numériques ; la réception de données numériques ; les applications audio ; la transmission d'images en temps réel. Finally, the invention relates to the various applications of the method, the devices, the signal and the switching node presented above, and in particular the applications to at least one of the fields belonging to the group comprising: high-speed switching;

transmission of digital data; reception of digital data; audio applications; real-time image transmission.

Other characteristics and advantages of the invention will appear more clearly on reading the following description of a preferred embodiment, given by way of simple illustrative and nonlimiting example, and of the appended drawings, among which: - the figure 1 presents a block diagram of the various steps implemented according to the invention during the reception, by a storage means, of data fulfilling at least one predetermined condition; - Figure 2 illustrates an exemplary embodiment of a device for generating a filling indicator implemented according to the method of Figure
1; - Figures 3 to 9 describe an example of implementation of the invention in the context of a high speed switching system for domestic applications. More specifically, Figure 3 illustrates

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 the general architecture of such a broadband switching system. Figure 4 shows the different devices connected to the switch of such a system. Figure 5 illustrates the internal architecture of the switch. Figures 6 and 7 describe in more detail the architecture of a so-called 0-FIFO block of such a switch. Finally, Figures 8 and 9 illustrate specific elements of the 0-FIFO block.

 The general principle of the invention is based on the generation of an indicator for filling a storage means which is significant, simultaneously, with information relating to the "container" and to the "content" of this storage means.

 The steps implemented according to the invention are presented in relation to FIG. 1 during the reception, in a storage means, of data fulfilling a predetermined condition.

 Consider a FIFO type storage means (in English "First In First Out"), which is initially in a substantially empty state. The value of a filling indicator for this FIFO is then positioned (311) at "false". As data is received supplying the storage means, the filling rate of the FIFO is monitored (312).

 Upon reception of data by the FIFO, it is further checked (313) whether these data meet at least one predetermined condition. Such a condition, according to a preferred embodiment of the invention, is verified if the data received constitute the end of a set of data. For example, during a transmission in burst mode, the data checks such a condition if it constitutes an end of packet.

 If the data received by the FIFO satisfy the predetermined condition or conditions, the FIFO filling indicator then takes (314) the value "true". Otherwise, the FIFO filling rate is continued to be monitored (312), and, according to a conventional process not illustrated in FIG. 1, the FIFO filling indicator takes the value "true" when the rate FIFO filling level is greater than a predetermined threshold.

 When the value of the FIFO filling indicator is set

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 to "true", one then proceeds to the transfer (315) of at least part of the data contained in the FIFO to a recipient element. Such a recipient element can for example be a DPRAM (in English "Dual Port Random Access Memory").

 We now present, in relation to FIG. 2, an exemplary embodiment of a device for generating an indicator for filling a storage means implemented according to the method of FIG. 1.

 Such a device comprises a first module 221 for detecting the end of a packet in the FIFO. Such a module 221 makes it possible to detect the presence of the end of a set of data (of packet or message type for example) in the FIFO.

Such a module 221 is supplied by control and data signals 220, and generates an indicator 224 Eop ~ in ~ fifo, which takes a first "true" value when the end of a packet is present in the FIFO, and which takes a second "false" value otherwise.

 The device of FIG. 2 also includes a second FIFO control module 222, supplied with control and data signals 220, and which generates an indicator 223 of FIFO filling, called Almostfull. Such an indicator 223 takes at least two distinct values indicative of the filling rate of the FIFO.

 For example, according to a preferred embodiment of the invention implementing a cascaded logic (in English "pipelined logic"), the indicator 223 is a binary indicator taking the value "true" when the filling rate of the FIFO is greater than a predetermined threshold (that is to say when the FIFO is substantially full) and the value "false" when this rate is less than the predetermined threshold (that is to say when the FIFO is not not substantially full). This predetermined threshold is worth N-x, where the value x then represents the number of clock cycles necessary for the cascade logic to react to a given event, and where N is the size of the FIFO, for example N = 16.

 The device of FIG. 2 also includes a module 225, powered by the indicators Eopinfifo 224 and Almostfull 223, and generating a third

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 Almostfull indicator 226. Such a module 225 therefore performs a logical OR of the incoming indicators 223 and 224 to deliver the final indicator for filling the FIFO 226. Such an indicator 226 thus makes it possible to trigger the transfer of data contained in the FIFO to a recipient element, on the one hand when the FIFO is full (value of the Almostfull 223 indicator "true"), and on the other hand when it contains an end of packet (value of the Eopinfifo indicator 224 "true") .

 Thus, according to the invention, even if the FIFO memory is not "almost full" and contains only the information representative of an end of packet, this can nevertheless, and in a simple manner, be transferred to a RAM memory for example.

 The method of FIG. 1 and the device of FIG. 2 find applications in numerous fields, and apply in particular in the context of: high-speed switching; transmission and / or reception of digital data; audio applications; real-time image transmission.

 A preferred field of application of the invention is that of domestic applications for broadband transfers, but it is understood that the invention can be implemented in any system requiring the transfer of information, and in particular the transfer packets in a pipeline mode. We will describe below an example of a system implementing the invention, used to interconnect a plurality of audio and video devices, or to transfer information of the type of information transferred between a computer and a printer, scanner or camera. digital.

 The invention is of course also applicable to any other type of system in which it is advantageous to optimize the filling of a storage means, and the corresponding data transfer from this storage means to a recipient element.

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 We have already developed the IEEE 1394 and IEEE 1355 standards suitable for serial communications and point-to-point communications respectively.

The system presented in the rest of the document is a backbone network with switched packets making it possible to achieve high transmission capacities (typically of the order of Gbit), and responding to the significant need for interfacing of the two types of standard above. .

 FIG. 3 shows a block diagram of a switching node 90 connected to two serial communication buses conforming to the IEEE 1394 and IEEE1355 standards.

 The node shown in Figure 3 is also connected to one or more other switching nodes of the switched network to which it belongs.

 In the embodiment shown in FIG. 3, it has been chosen to represent a data processing apparatus 92, also called a peripheral, which is associated with the switching device 90.

 A switching node includes: a switching device 90; and a data processing apparatus 92 associated with said device.

 As a variant, the data processing device can itself constitute or include the switching device 90.

 The device 90 comprises: a central processing unit CPU 93; - A permanent storage means 94 of ROM type; and - a temporary storage means 95 of RAM type, associated with the central unit 93, and in which a software architecture is loaded upon initialization.

 The storage means 95 is able to store data packets of different types, in particular: - asynchronous packets of the type conforming to the IEEE 1394 standard; packets constituting messages in unconnected mode (asynchronous), of the type conforming to the IEEE 1355 standard;

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- control packets of the type conforming to the IEEE 1355 standard; - stream (isochronous) packets of the type conforming to the standard
IEEE 1355.

 The packets of the type conforming to the IEEE 1355 standard actually exist at the level of component 104 which will be mentioned later but they are not stored in this form in the RAM storage means 95. It will be noted that the storage means 95 contains the information needed to generate IEEE 1355 packets.

 The routing of such packets to the storage means 95, coming either from the bus 1394 or from the switched network consisting of IEEE 1355 links will be detailed later.

 The routing of such packets, from the storage means 95 to their transmission by the switching node, either in the direction of the IEEE1394 bus, or in the direction of the switched network consisting of IEEE 1355 links will be detailed later.

 These three elements 93, 94 and 95 communicate by means of respective address and data buses denoted 96, 97 and 98, with a block denoted 99 and known to those skilled in the art under the name of bus controller.

 This block 99 makes it possible in particular to exchange data by means of a main bus 100 with at least one bus interface component 101. In the case where the bus 100 is a standard PCI bus (PCI meaning in English terminology "Peripheral Component Interconnect"), component 101 can be a component called AMCC 5933QC sold by the company APPLIED MICRO CIRCUITS CORPORATION (Registered trademark).

 The bus 100 can also connect other elements, not shown in FIG. 1, to each other, themselves provided with a bus interface and capable of implementing, for example, data processing functions.

 For example, in a case where the bus 100 is a standard PCI bus, the block 99 is in fact a set of PCI components such as the set Intel 440LX AGP ("Intel 440LX AGPset" in English terminology) marketed by the

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 INTEL company (registered trademark).

 Thus, the block 99 comprises, for example, a component 82443LX which provides the interface with the memory 95 via the memory bus 98 and with the central processing unit CPU 93 via the local bus 96. The component 82443LX is itself connected to a component 82371AB which provides an interface with the ISA bus 97 connected to the memory 94. An IOAPIC interrupt controller Intel 82093AA connected to the central processing unit CPU 93 manages the interrupts that may occur in the system.

 As shown in FIG. 1, the device 90 also includes a bus interface 102 which can be similar to the bus interface 101 thus allowing the data processing apparatus or peripheral 92 to access the communication device.

 Such an interface is for example produced in the form of a SEDNET PCI card sold by the company SEDERTA (registered trademark) under the reference SD-PCI-200 and allows any existing data processing device to be connected to it, designed to operate in accordance with standard 1394.

 It is of course possible to use an adapter 102 specific to the data processing device that one wishes to connect to it. The adapter 102 essentially comprises an interface component similar to the bus interface component 101.

 Depending on the type of data processing device, the main bus 100, as well as the bus interface components 101 and bus controller 99 can be adapted according to the architecture of the type of the device. The same is true for all of the elements CPU 93, RAM 95 and ROM 94.

 As shown in FIG. 3, the node according to the invention also comprises two interfacing means 103 and 104.

 The means 103 is intended to provide the interface between the node 90 and the serial communication bus intended to operate according to the IEEE 1394 standard to which the said node is attached.

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 The interfacing means 103 is a set of PHY / LINK 1394 components which for example consists of a PHY component TSB21LV03A and a LINK component TSB12LV01A sold by the company TEXAS INSTRUMENT (Registered trademark) and of connectors 1394, for example marketed by the company MOLEX (registered trademark), for example under the reference 53462.

 The interfacing means 103 comprises at least one external port intended to be connected to a data processing device or peripheral which is attached to the serial communication bus 1394.

 The means 103 includes means for counting the number of pulses as a function of a clock signal generated by a control module 107, which will be defined later. This clock signal is synchronized with the "Cycle master" of the serial communication bus with which it is in contact, via the start of cycle packets, called "Cycle Start packet" in English terminology. The frequency of the clock signal generated by the control module 107 is equal to 24.576 MHz +/- 100 ppm. This signal is represented as being one of the signals denoted ctrl3 in FIG. 3.

 On each serial communication bus of the network, one of the nodes is called "Cycle Master" ("Cycle Master" in English terminology) and the "Cycle Master" node of the "root" bus is called "Master of network cycle "(" Net Cycle Master "in English terminology).

 In addition, all the "Cycle Masters" nodes of the network have their own characteristic, since it depends on the frequency of their internal clock, from which the duration of a "reference period" is defined or "cycle".

 The duration of the cycle noted T is equal to an integer number of clock pulses, common or not to all the buses, and which is multiplied by the inverse of the frequency of the internal clock specific to the "Master of cycle".

 The duration of the cycle T is thus, for example, equal to 125 microseconds.

 When two serial communication buses are connected by a bridge, the

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 "Cycle master" of one of the buses must synchronize its cycles with the cycles generated by the "Cycle master" of the adjacent bus.

 In general, communication networks made up of serial communication buses allow synchronized packet transmission from the bus cycles considered. Buses are for example used to transmit data packets in real time of the audio / video type.

 The counting means such as those of the interfacing means 103 mentioned above are for example in the form of a register.

 The interface means 104 mentioned above is an IEEE 1355 interface component which has three ports. It notably includes a Cl 13 component sold by the company 4LINKS as well as three LUC1141MK interface components sold by the company LUCENT (Registered trademark), themselves connected to IEEE 1355 connectors, for example marketed by the company HARTING (Registered trademark ). The CI 13 component is itself produced on the basis of a programmable component of FPGA type ("Field Programmable Gate Array" in English terminology) Spartan XCS30XL, marketed by the company XILINX (registered trademark).

 The initials FPGA correspond approximately in French to "Matrix of Programmable Doors".

 The three external ports of the interfacing means 104 are intended to be connected to ports of the same type on another switching node of the switched network, thus allowing the device 90 to communicate with another node of this network.

 The device 90 also includes a data flow control means 105 which allows the transfer of data between the different interface components 101, 103 and 104. This means 105 is produced in programmable logic, executed by a component of FPGA type, for example of reference VIRTEX, marketed by the company XILINX.

 This means 105 implements in particular a dual port storage unit 106 which makes it possible to store data intended for, or coming from

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 from the switched network 1355.

 The dual-port storage unit has a storage capacity of less than 2 Mbits and is, for example, produced in the form of a DPRAM type memory with 32-bit access.

 The initials DPRAM mean in Anglo-Saxon terminology "Dual Port Random Access Memory" which can be roughly translated into French by "volatile memory with double port".

 The storage unit 106 includes a plurality of memory areas which are managed as individual FIFO type memories, initials of the English terms "First-in First-out" meaning in French "First in First out".

 Such a memory zone corresponds to a memory in which the data are read in the order in which they have been previously written.

 These memory areas each have an associated read pointer and write pointer.

 Each memory area being managed as a FIFO type memory, its filling and emptying can be carried out at the same time, and independently. This makes it possible to desynchronize the operations for reading and writing the data, carried out by a switching unit 108 which will be defined later, for the operations for reading and writing the data, carried out by the control module 107.

 In fact, the occupancy rate of the memory area considered is managed in a circular manner and it is known at all times whether the data contained in a memory area has been read or not. When these data have been read, it is then possible to come and write new data in place of these.

 The dual port storage unit somehow forms a queue for packets, and the storage function is performed independently, depending on the port through which the packets arrive at the storage unit.

 Generally, all isochronous or asynchronous data

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 from the switched network are stored in the storage unit 106.

 This storage is temporary for the asynchronous data packets (packets constituting a message transmitted in unconnected mode) and for the control packets, which are caused to be then transferred to the RAM 95 storage means for storage of a longer duration. important.

 On the other hand, the isochronous data packets (“stream” type packets, that is to say transmitted in connected mode), are stored only in this storage unit 106 before their transmission on the communication bus to which the switching node 90 or on the switched network.

 This is explained by the fact that this type of data must be transferred as quickly as possible from the switched network to the bus and therefore must be stored in an easily and quickly accessible storage medium.

 Similarly, the isochronous data packets, originating from the communication bus to which the switching node 90 is connected, and which are intended for the switched network, are stored only in the storage unit 106, and not in the storage means 95 , for the same reasons as those mentioned above.

 As shown in FIG. 3, the data flow control means 105 comprises several other elements including a control module 107 (already mentioned above), which provides a control function for the storage unit 106, a unit switch 108 (already mentioned above) in communication with the interfacing means 104, with the storage unit 106 and with the control module 107, as well as a data packet scheduling unit 109, which is relationship with the control module 107.

 It will also be noted that the control module 107 communicates with the interfacing means 103 and 104 as well as with the bus interface component noted 101.

 The control module 107 has the function of multiplexing the read or write accesses to registers of other modules from the main bus denoted 100.

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The module 107 also has control of the bus interface component 101 for the read and write operations on the main bus 100, including in particular the transfer in "burst mode" (known in English terminology under the term "burst" fashion").

 The control module 107 is also responsible for triggering interruptions on the main bus 100, as a function of specific communication events.

 This module exchanges data with component 101, on an additional bus 110 (known in English terminology under the term "add-on bus"), according to the control signals denoted ctrll.

 As announced above, the module 107 is responsible for controlling the storage unit 106, as regards the read and write operations in FIFO mode, in the particular case where the bus interface component 101 is an AMCC, via a data bus 111 and carl2 control signals.

("Asynchronous Transfer FIFO"en terminologie anglo-saxonne) et ITF ("Isochronous Transfer FIFO"en terminologie anglo-saxonne) et une mémoire FIFO de réception dite GRF ("General Receive FIFO"en terminologie anglosaxonne). Ces mémoires FIFO sont plus largement décrites dans la documentation associée au composant LINK TSB12LV01A. The interfacing means 103 contains memories of the FIFO type, which are used during the transfer of data packets of type conforming to the IEEE 1394 standard. It comprises two FIFO memories of transmission known as ATF

("Asynchronous Transfer FIFO" in Anglo-Saxon terminology) and ITF ("Isochronous Transfer FIFO" in Anglo-Saxon terminology) and a reception FIFO memory known as GRF ("General Receive FIFO" in Anglo-Saxon terminology). These FIFO memories are more widely described in the documentation associated with the LINK component TSB12LV01A.

de données sur un bus 112 suivant des signaux de contrôle carl3. The control module 107 and the interfacing means 103 manage the transfer

data on a bus 112 according to control signals carl3.

 Furthermore, the control module 107 controls the switching unit 108, by means of control signals ctrl 4, in order to transfer data from the switching unit to the storage unit 106 via a data bus 113, and vice versa.

 The switching unit 108 is connected to the interface means 104 by

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l'intermédiaire d'un bus de données 114 et de signaux de contrôle curls.

via a data bus 114 and curls control signals.

The data packet scheduling unit 109, also noted SAR (known in English terminology under the term "Segmentation And Reassembling"), informs the control module 107 of the next data packet (s) to be transmitted, by carl6 control signals.

 In addition, the scheduling unit 109 checks the reception of the data packets, and manages the allocation and the release of memory areas (known in English terminology under the term of "buffers") of the storage unit. 106.

 The control signals ctrl7 exchanged between the interface means 104 and the control module 107 include in particular the clock signals regenerated from the reception of the packets 1355 on each of the three ports of the interface means 104.

 A quartz at 49.152 MHz (not shown) is connected both to the means 104 for transmitting the 1355 packets and to the control module 107 which generates a clock signal at 24.576 MHz +/- 100 ppm, on the one hand , for the data packet scheduling unit 109, in order to schedule the transmission of the 1355 packets and, on the other hand for the interfacing means 103, in order to schedule the transmission of the 1394 packets.

 FIG. 4 presents a detailed block diagram of the data flow control means 105, of the interface 104 illustrated with reference to FIG. 3, as well as their interconnections.

 Some details on the serial interface 104 make it possible to understand how packets are multiplexed on the data bus 114.

The serial interface 104 notably comprises: a FIFO control means 120 described above with reference to FIG. 3; three input FIFOs 121 (InPortO ~ FIFO), 122 (InPortl ~ FIFO) and
123 (InPort2 ~ FIFO); a multiplexer 127; and

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des FIFO de sorties 124 (OutPortOFIFO), 125 (OutPortlFIFO) et 126 (OutPort2FIFO).

output FIFOs 124 (OutPortOFIFO), 125 (OutPortlFIFO) and 126 (OutPort2FIFO).

 FIFOs 121, 122 and 123 are used for storing incoming packets, while FIFOs 124 to 126 are used for storing outgoing packets.

 A pair of FIFOs is connected to each port of the 104 IEEE 1355 interface.

Thus, for example: FIFOs 121 and 124 are used for port 0; FIFOs 122 and 125 for port 1; and FIFOs 123 and 126 for port 2.

 The data bus 114, illustrated with reference to FIG. 3, is broken down into two buses in FIG. 4: a bus 44 RxDI [17: 0] for receiving data intended for the switching unit 108 and transmitted by the interface 104; and a bus 41 TxDO [17: 0] for transmitting data from the switching unit 108, to the interface 104.

 After being written to one of the input FIFOs 121, 122 and 123, the incoming packets are multiplexed through the multiplexer 127 before being sent back to the switching unit 108 through the bus 44.

 The outgoing data from the switching unit 108 is sent through the data bus 41 to be stored in one of the output FIFOs 124, 125 or 126.

l'unité de mémorisation à double port ou DPRAM 106. It will be recalled that the data flow control means 105 comprises in particular: the control module 107; the switching unit 108; and

the dual port memory unit or DPRAM 106.

The Curls control signal, illustrated with reference to FIG. 3, breaks down into three signals in FIG. 4: a control signal 51;

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un signal de contrôle 43 TxFIFOfull [O : 2J ; et un signal de contrôle 42 WnTYF7FO//2./.

a control signal 43 TxFIFOfull [O: 2J; and a control signal 42 WnTYF7FO // 2. /.

The control signals 51, TxFIFOfull [O: 2J 42 and WriteTXFIFO [O: 2J 43 allow the FIFO control means 120 to manage the transfer of data packets between the switching unit 108 and the link interface 104 serial, through data buses 44 and 41.

 The processing of the control signals in the switching unit 108 will be described later with reference to FIG. 5.

- un signal de contrôle IntRxTxEOP .: /45a ; - un signal de données 7Y/7.-07 45b. The signal Ctrl4, illustrated with reference to FIG. 3, between the switching unit 108 and the control module 107, breaks down into at least four signals in FIG. 4: - two control signals 53 and 54;

- an IntRxTxEOP. control signal: / 45a; - a data signal 7Y / 7.-07 45b.

The signal 45b is a data bus connecting the elements 106, 107 and 108.

The control module reads the packet headers from this bus 45b.

The control signals 53, 54 and 45a allow the management of data transfer 7RxTY / \? 7.'û / 45b between the dual port memory 106 and the switching unit 108.

 In some cases, notably during packet header processing, the packet data is sent to the control module 107 rather than to the storage unit 106 for later analysis.

 The data bus 45b is represented in FIG. 3 by the data bus 113.

 FIG. 5 represents an electronic diagram of the switching module 108 of FIG. 2.

 The switching module 108 comprises in particular: an arbitration means 60; cycle generation means 20; means responsible for receiving and transmitting data in

<Desc / Clms Page number 22>

coming from or going to the interface 104 (either the data coming from or going to an IEEE1355 switched network); and means responsible for receiving the data coming from the DPRAM memory 106 (ie the data coming from an IEEE1394 bus); and means responsible for transmitting data to the DPRAM memory
106 (ie the data destined for an IEEE1394 bus);

 The means responsible for receiving and transmitting data from or to the interface 104 include in particular: means 18 for modifying the header; a means 19 for header analysis on reception; two volatile reception memories 15 and 16 arranged in FIFO; and a means 17 for controlling the reception FIFOs 15 and 16.

 The means responsible for receiving data from the DPRAM memory 106 include in particular: four input FIFOs 9, 10, 11 and 12; means 130 for controlling the input FIFOs; a multiplexer 50; and a means 13 for analyzing the transmission header.

 The means responsible for transmitting the data to the DPRAM memory 106 include in particular: three assembly memories 22, 23 or 24; three output FIFOs 25, 26 and 27; a control means 84 of the output FIFOs; and a multiplexer 28.

 These elements forming part of the switching module 108 are connected by connection elements described below. It should nevertheless be noted that most of the exchanges are around the arbitration means 60 with the use of two main data buses, TxBus 70 and RxBux 80, the accesses of which are managed by the arbitration means 60.

<Desc / Clms Page number 23>

 The use of the two internal buses, the TxBus 70 transmission bus and the RxBus 80 reception bus, which make it possible to process data transfers between the ports, will now be detailed.

 Outgoing packets to bus 41 are transmitted through the TxBus transmission bus 70.

 The outgoing packets towards bus 45 are transmitted through the internal reception bus RxBus 80.

OpenTxTT[O :33Lon Rx 40 pour les données issues des FIFO d'entrée 9, 10, 11 et 12 ; et de registres à trois états 14 grâce à des signaux de contrôle OpenRxTS~onTx 33 pour les données issues de la mémoire 16. The arbitration means 60 is in charge of managing the write accesses on the TxBus bus 70 controlling the opening: of three-state registers 1,2, 3 and 4 thanks to signals

OpenTxTT [O: 33Lon Rx 40 for data from input FIFOs 9, 10, 11 and 12; and three-state registers 14 using OpenRxTS ~ onTx 33 control signals for the data from memory 16.

The read operations from the TxBus bus 70 to an output port of the interface 104 are managed by the arbitration means 60 according to the control signal to the FIFOs associated with each port T. xF7F <9 / MO.'2 43 and WriteTxFIFO [0: 2] 42.

The arbitration means 60 also manages the write accesses to the RxBus bus 80 by controlling the opening: of three-state registers 5, 6, 7 and 8 through signals
OpenTxTs: 3LonRx 39 for data from input FIFOs 9,10,
11 and 12; and a three-state register 21 through control signals
OpenRxTs ~ onRx 34 for data from memory 15.

 The arbitration means 60 also performs the operations of reading data on the RxBus bus 80 for writing to one of the assembly memories 22, 23 or 24 (in English "assembly buffers"). The "assembly buffer" serves as a buffer for the conversion of data between bus 80, on which the data is expressed in 18 bits (16 data bits and 2 control bits), and the

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a~FIPas 25, 26 et 27, dans lesquelles les données sont exprimées sur 34 bits) (32 bits de données et 2 bits de contrôle).

a ~ FIPas 25, 26 and 27, in which the data is expressed in 34 bits) (32 data bits and 2 control bits).

These bus sizes are linked to physical constraints. The module 84 transmits to the arbitration means 60 a control signal Rx FIFOfull [0 '2] 83, indicating the degree of filling of the FIFOs 25, 26 and 27. The arbitration means 60 generates a control signal WriteOFIFF [2 : 0] 35 to a module 84 for controlling the output FIFOs, depending on the degree of filling of the FIFOS 25, 26 and 27.

 The arbitration means 60 for the multiplexing of the data on the buses 70 of transmission TxBus and 80 of reception RxBus uses signals 46 of cycle EN ~ cycle [0: 2]. It is the cycle generation means 20, for example a Johnson counter, which generates these signals 46.

 The processing of incoming data will now be detailed according to the origin of this data: bus 44; bus 45.

 Incoming data from bus 44 RxDI [17: 01 or bus 45 will be routed to the switch to go: to bus 41 TxD0 [17: 0] either in the direction of interface 104; or to bus 45 either towards DPRAM 106.

 The processing of incoming data from bus 44 will now be explained.

 The data exchanges on the bus 44 are managed through the header modification means 18 and the FIFO control means 120 of the serial interface, thanks to the control signals 51. The control signals 51 comprise a write signal to the header modification means 18 and module 18 flow control signals, each corresponding to input ports of the interfacing means 104.

 The pieces of packets entering from the bus 44 first arrive at a header modification means 18 for processing relating to the

<Desc / Clms Page number 25>

 packet headers.

The pieces of packets are then stored: in the memory 15 when they are addressed to the reception bus 80
RxBus; and in memory 6 when addressed to the transmission bus
70 TxBus.

 When they are addressed to the two buses, the packet pieces are addressed to the two buses simultaneously to be stored in two storage means simultaneously.

 Likewise, the reception FIFO control means 17 controls the storage operations in the two memories 15 and 16.

 The memories 15 and 16 are dual-port memories, divided into three independent zones, each being managed like a FIFO.

 The synchronous signals are managed at a certain rate corresponding to a succession of phases consisting of four clock cycles.

In a four-cycle phase, during each of the first three clock cycles of the phase, both a write operation and a read operation are carried out at two addresses of each of the RAMs (volatile memories) 15 or 16. These addresses point respectively: to the last element (tail) of one of the FIFOs in each of the
RAM 15 and 16; and to the first element (head) of one of the FIFOs in each of the
RAM 15 and 16.

 No read or write operation to the RAMs 15 and 16 is carried out during the fourth clock cycle in a four-cycle phase.

 Each effective FIFO read operation (defined when the Rx output signal 32 [iLread is activated during a cycle and is followed by an AllData used input signal [it activated during a cycle, i corresponding to a FIFO number d 'entry) changes the address pointing to the FIFO header.

 Effective FIFO write operations (based on the same

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 mechanism that the read operations, here using the signal 52 illustrated with reference to FIG. 3) modify the address pointing to the tail of the FIFO.

 Thus, during three cycles, each part of FIFO corresponding to each of the input ports is processed: data writing operations by the header modification means 18 are sequentially addressed to the corresponding parts 15 and 16, each of the pieces of packets entering from each of the input ports 121, 122 and 123 of the interface 104.

 In a similar manner, the data read from memories 15 and 16 are processed respectively by the RxBus 80 and TxBus 70 buses.

 The reception FIFO control means 17 is in charge of reading and actually writing the FIFOs contained in the memories 15 and 16.

 The control signal 52 informs the header modification means 18 that a FIFO is full in one of the memories 15 or 16 and that there is also a write request for a FIFO in one memories 15 or 16.

 The reception FIFO control means informs the arbitration module 60 that a new datum has been read from one of the memories 15 or 16 thanks to the signal Rx {O: 2} read 32.

 The same data is read in each phase of four cycles when they are not effectively read by simply placing them, either on the RxBus bus, or on the TxBus bus, or on both, depending on the packet routing.

 Thus, the same data is presented every four cycles, until it has actually been read by the destination (s).

aux signaux de contrôle OpenRxTs~onTx 33, pour placer les données en lecture de la mémoire 16 sur le bus de transmission TxBus 70. The arbitration means 60 manages the opening of the three-state register 14 thanks to

to the OpenRxTs ~ onTx 33 control signals, to place the data in read mode from memory 16 on the TxBus 70 transmission bus.

The means 60 also manages the opening of the three-state register 21, thanks to the control signals OpenRxTs ~ onRx 34 for putting the data read from the memory 15 to the reception bus RxBus 80.

allRxData~used < K/û.'27 pour indiquer au moyen 17 de contrôle des FIFO de The arbitration means 60 also manages the control of the signals

allRxData ~ used <K / û.'27 to indicate by means 17 of FIFO control of

<Desc / Clms Page number 27>

reception that the next data will be read by a corresponding part in one of memories 15 or 16.
The means 19 for analyzing the header of received packets controls the shape of the signal 47 to the arbitration means 60.

122 ou 123 est traité dans le moyen 18 de modification d'en-tête, le signal 47 70.'27Wû'0.'. 3/ permet la requête d'une connexion : vers l'un des ports de sortie de l'interface 104 à travers le bus multiplex 41 ; ou vers l'une des FIFO internes 25,26 ou 27 à travers le bus multiplexé 45.
Lorsque la fin du paquet est traitée dans le moyen 18 de modification d'entête, le signal 47 RxEOP[0:2] informe le moyen d'arbitrage 60 de la fin d'une connexion. When a new packet from one of the input ports 121,

122 or 123 is processed in the means 18 for modifying the header, the signal 47 70.'27Wû'0. '. 3 / allows the request for a connection: to one of the output ports of the interface 104 through the multiplex bus 41; or to one of the internal FIFOs 25, 26 or 27 through the multiplexed bus 45.
When the end of the packet is processed in the header modification means 18, the signal 47 RxEOP [0: 2] informs the arbitration means 60 of the end of a connection.

 Note that the header modification means 18 emits a signal representative of routing information intended for the header analysis means 19 on reception.

IEEE 1355, le moyen 60 d'arbitrage gère les signaux 81 RO [0 :c < ?onnected émis vers le moyen 17 de contrôle de FIFO de réception pour indiquer le statut de la connexion associée à chaque port. Regarding connection and disconnection to the serial interface

IEEE 1355, the arbitration means 60 manages the 81 RO [0: c <? Onnected signals transmitted to the reception FIFO control means 17 to indicate the status of the connection associated with each port.

Similarly, the arbitration means 60 manages the signals 70.'2 / c6'necJ 82 to the means 130 for controlling the input FIFOs 9, 10, 11 and 12 for the data coming from the DPRAM 106.

 The data exchanged on the bus 45 are managed: by the means 84 for controlling the output FIFOs 0 ~ FIFO and the control module 107 by means of the signal 53; and by the means 13 for controlling the I-FIFO input FIFOs and the control module 107 by means of the signal 54.

 Multiplexer 28 authorizes the selection of a FIFO output FIFO from the three FIFOs 25, 26 or 27 for FIFO read operations of

<Desc / Clms Page number 28>

 data intended for the dual-port storage memory 106. This selection operation is managed by the means 84 for controlling FIFO of output 0FIFO by means of a signal 85.

 Furthermore, the means 130 for controlling the FIFO of inputs f7FO control operations for writing the storage memory 106 to one of the four FIFOs 7F7FIFO for input 9, 10, 11 or 12 by means of the signals 90.

 This is only the case for the bus 42 where the control signals 43 and 42 attached to the storage means of the output ports are directly connected to the arbitration means 60.

 In other words, the bus 41 is the only bus whose control signals (42 and 43) are directly connected to the arbiter 60.

 The processing of incoming data from bus 45 will now be detailed.

 The packet pieces from bus 45 are demultiplexed to each input FIFO 9, 10, 11 and 12. Thus, four packets (one per input FIFO) can be processed simultaneously.

 Each input FIFO is connected to two internal buses 70 and 80 through the three-state registers 1 to 8.

The arbitration means 60 is responsible for managing: the write accesses on the TxBus bus 70 alternately controlling the opening of the three state registers, 1 to 4 thanks to the OpenTx7 signals [0: 33LonTx 40, each of the registers 1 to 4 being assigned to a
Input FIFO 9 to 12; and write accesses on the RxBus 80 bus alternately controlling the opening of the three-state registers 5 to 8 thanks to the signals
OpenTxTs [0: 3] ~ onRx 39, each of registers 5 to 8 being assigned to a
Input FIFO 9 to 12.

 The write operations on the RxBus 70 bus are independent of the write operations on the TxBus 80 bus.

 The arbitration means 60 also generates control signals aTxData

<Desc / Clms Page number 29>

M0 ; / 37, qui autorisent la lecture sur l'une des FIFO d'entrées 9 à 12, grâce aux moyens de contrôle des FIFO d'entrée 130.

M0; / 37, which authorize the reading on one of the input FIFOs 9 to 12, by means of the control of the input FIFOs 130.

 The means 130 for controlling the input FIFOs informs the arbitration means 60 of the success of a read operation, carried out by one of the input FIFOs, by means of the control signal 38 Tx [O: 3LRead.

 The packet header data is multiplexed by a multiplexer 50 from one of the output FIFOs 9 to 12 to be sent to the header analysis means 13.

7jc/.'JVï : 3 à destination du moyen d'arbitrage 60. The transmitted packet header analysis means 13 analyzes the data from the input FIFOs 9, 10, 11 and 12 to generate the signal 36

7d /. 'JVï: 3 for the arbitration means 60.

When a new packet is processed in one of the input FIFOs 9 to 12, the signal 36 70.'WMO.'37 allows the request for a connection: to one of the output ports of the means of interfacing 104 by a bus
41 multiplexed; or to one of the output FIFOs 25, 26 or 27 by a multiplexed bus 45.

 When the end of the packet is processed in one of the input FIFOs 9 to 12, the signal 36 TxEOP (3P.'3 makes it possible to inform the arbitration means 60 of an end of connection.

 FIG. 6 illustrates the architecture of the O-FIFO block presented in FIG. 5. The O-FIFO block implements three output FIFOs 25, 26 and 27, each associated with an internal port. An O-FIFO output FIFO will be described in more detail in relation to FIG. 7.

 Control signals 203 coming from the reception bus 80 Rx-bus are processed by the logic means RXBUS20F 204. These logic means have the task of addressing one of the three FIFOs 25 to 27, as a function of the control signals 203 The RXBUS20F 204 logic is also in charge of converting data from 16 to 32 bits. Such a conversion is carried out by implementing the we-low and we-high commands of the FIFOs. Finally, a

<Desc / Clms Page number 30>

additional function of this logic is to decode the eop / eom indicators (end of packet / end of message for, in French, end of packet / end of message) coming from the reception bus 80 Rx ~ bus, and generate the command we ~ eop 228 of FIFOs.

The multiplexer 28 feeds the intrx ~ tx ~ data 45 bus using data from one of the FIFOs, according to the intrx-datarequest signal [2: 01 214. The multiplexer 28 also detects the reading of an end packet or end of message (eop / eom) from the FIFOs, so as to generate the signal eop-alout-pins 205.

FIG. 7 illustrates the architecture of an output FIFO O ~ FIFO 25, 26 or 27.

An O ~ FIFO is performed using two counters 206 and 207, a volatile dual-port memory 210 to 212, an indicator generator 208 which will be described in more detail in relation to FIG. 9, and a detector of end of packet or end of message 209 which will be described in more detail in relation to FIG. 8.

 The write counter 206 is used to generate write addresses in the volatile dual-port memories 210 to 212, when data arrives via the reception bus 80 Rx ~ bus. This counter 206 is controlled by the loading signal 213 push generated by the logic RXBUS20F 204, as illustrated in FIG. 6. This loading signal 213 is generated each time two words of 16 bits and a control word of 2 bits are written in the dual-port volatile memories 210 to 212, that is to say each time a 34-bit word is written.

données est émise à travers le signal intrx~datarequest 214. The read counter 207 is used to generate read addresses in the dual-port volatile memories 210 to 212, when a request for

data is sent through the intrx ~ datarequest 214 signal.

The almostfull signal 226 is obtained by performing a logical OR between the signal û / MO / M 223 generated by the flag-gen indicator generator 208 and the eop-in signal io 224 generated by the end of packet detection module ~ ff top-detect 209, as illustrated previously in relation to FIG. 2.

<Desc / Clms Page number 31>

Figures 8 and 9 illustrate in more detail the possible embodiments of the end of packet detector eop ~ detect 209 and the indicator generator? Aggen 208.

The eop ~ detect 209 module is a counter 227 which counts the number of occurrences of an end of packet or of an end of message (eop / eom) in the FIFO. This counter 227 is incremented when the signal we ~ eop 228 is validated, that is to say during a writing in the volatile dual-port memory 212 of bits 32 and 33.

 This counter 227 is decremented when the signal eop ~ at ~ out ~ pins 205 is validated. Such a signal 205 is generated by the multiplexer 28 when an end of packet or message (eop / eom) is read from the FIFO.

 Obviously, when these two conditions are satisfied (eop ~ at ~ outpins 205 and we ~ eop 228 validated simultaneously), the counter remains unchanged.

 As illustrated in FIG. 9, the indicator generator 208 is also a counter, which counts the set number of 34 bits in the 0FIFO.

Claims (37)

 CLAIMS 1. Method for optimizing the use of a storage means, using at least one filling indicator, the value of said indicator being modified when the storage space available in said storage means exceeds at least one predetermined threshold, characterized in that the value of said indicator is also modified when the data contained in said storage means meet at least one predetermined condition. 2. Method according to claim 1, characterized in that one of said predetermined conditions is the reception, in said storage means, of information on the end of transmission of a set of data. 3. Method according to claim 2, characterized in that said data sets belong to the group comprising: packets; protocol units; frames; messages. 4. Method according to any one of claims 1 to 3, characterized in that said storage means comprises at least one FIFO type memory. 5. Method according to claim 4, characterized in that the said FIFO memory or memories are associated with input ports of switching means. 6. Method according to any one of claims 1 to 5, characterized in that the modification of said value results in the transfer of at least part of said data contained in said storage means. 7. Method according to claim 6, characterized in that said transfer is activated by means of cascade logic control (in English "pipelined logic"). 8. Method according to claim 7, characterized in that the value of said indicator is a function of a reaction time of said control means. 9. Method according to any one of claims 1 to 7, characterized in that <Desc / Clms Page number 33>  that the value of said indicator is modified when said storage means is almost full (in English "almost full"). 10. Method according to claim 8, characterized in that the value of said indicator is modified when the filling rate of said storage means is greater than N-x, where: N represents the size of said storage means; x represents the depth of the pipeline, said transfer being based on a cascade logic. 11. Method according to any one of claims 1 to 10, characterized in that it comprises the following steps: monitoring the filling rate of said storage means; modification of the value of said indicator if said data supplying the storage means meet at least one predetermined condition; taking into account of said modification of said value, resulting in a transfer of at least part of the data contained in said storage means. 12. Method according to any one of claims 1 to 11, characterized in that it comprises a step of transferring data between two storage means according to a mode combining the techniques of burst and pipeline transfer depending on the value of said indicator . 13. Device for optimizing the use of a storage means, comprising means for generating at least one filling indicator, and means for modifying the value of said indicator when the storage space available in said storage means exceeds at least a predetermined threshold, characterized in that it further comprises means for modifying the value of said indicator when the data contained in said storage means meet at least one predetermined condition. 14. Device according to claim 13, characterized in that one of said <Desc / Clms Page number 34>  predetermined conditions is the reception, in said storage means, of information on the end of transmission of a set of data. 15. Device according to any one of claims 13 and 14, characterized in that said storage means comprises at least one FIFO type memory. 16. Device according to claim 15, characterized in that the said FIFO memory or memories are associated with input ports of switching means. 17. Device according to any one of claims 13 to 16, characterized in that it comprises cascade logic control means (in English "pipelined logic") ensuring the transfer of at least part of said data contained in said storage means, when said value is modified. 18. Device according to claim 17, characterized in that the value of said indicator is a function of a reaction time of said control means. 19. Device according to any one of claims 13 to 18, characterized in that the value of said indicator is modified when said storage means is almost full (in English "almost full"). 20. Switching device, characterized in that it comprises means for optimizing the use of an internal storage means, said optimization means comprising means for generating at least one filling indicator, and means for modifying the value of said indicator when the storage space available in said storage means exceeds at least a predetermined threshold, and / or when the data contained in said storage means meet at least one predetermined condition. 21. Switching device according to claim 20, characterized in that it comprises a device for optimizing the use of a storage means according to any one of claims 13 to 20. 22. Switching device according to any one of claims 20 and 21, characterized in that one of the said predetermined conditions is the reception, in the said storage means, of information on the end of transmission of a set of data. <Desc / Clms Page number 35>  23. Switching device according to any one of claims 20 to 22, characterized in that said storage means comprises at least one memory of the FIFO type. 24. Switching device according to any one of claims 20 to 23, characterized in that it comprises cascade logic control means (in English "pipelined logic") ensuring the transfer of at least part of said data contained in said storage means, when said value is modified. 25. Switching device according to claim 24, characterized in that the value of said indicator is a function of a reaction time of said control means. 26. Switching device according to any one of claims 20 to 25, characterized in that the value of said indicator is modified when said storage means is almost full (in English "almost full"). 27. Signal representative of an indicator for filling a storage means that can convey at least two distinct values, at least a first value associated with a substantially empty state of said storage means, and at least a second value associated with a state substantially full of said storage means, characterized in that said signal also takes said second value when the data contained in said storage means meet at least one predetermined condition. 28. Signal according to claim 27, characterized in that one of said predetermined conditions is the reception, in said storage means, of information on the end of transmission of a set of data. 29. Signal according to any one of claims 27 and 28, characterized in that said storage means comprises at least one memory of FIFO type. 30. Signal according to any one of claims 27 to 28, characterized in that the modification of said value results in the transfer of at least part of said data contained in said storage means. 31. Signal according to any one of claims 27 to 30, characterized in that <Desc / Clms Page number 36>  that the value of said indicator is a function of a reaction time of said control means. 32. Signal according to any one of claims 27 to 31, characterized in that the value of said indicator is modified when said storage means is almost full (in English "almost full"). 33. Signal according to claim 32, characterized in that the value of said indicator is modified when the filling rate of said storage means is greater than N-x, where: N represents the size of said storage means; x represents the depth of the pipeline, said transfer being based on a cascade logic. 34. Switching node comprising at least two storage means and a transfer means between at least two of said storage means, and means for generating at least one filling indicator, and means for modifying the value of said indicator when the storage space available in at least one of said storage means exceeds at least a predetermined threshold, characterized in that it further comprises means for modifying the value of said indicator when the data contained in said storage means fill at least one predetermined condition. 35. Switching node according to claim 34, characterized in that it comprises a control means activating the transfer of data between two of said storage means according to a mode combining the techniques of transfer in burst and in pipeline according to the value of said indicator . 36. Switching node according to any one of claims 34 and 35, characterized in that it comprises at least one device for optimizing the use of a storage means according to any one of claims 13 to 20. 37. Application of the method according to any one of claims 1 to 12 to at least one of the fields belonging to the group comprising: <Desc / Clms Page number 37>  high speed switching; transmission of digital data; reception of digital data; audio applications; real-time image transmission.