GB2370416A

GB2370416A - Hydrogenation of dangling bonds at a gate oxide/semiconductor interface

Info

Publication number: GB2370416A
Application number: GB0118019A
Authority: GB
Inventors: Yi Ma
Original assignee: Agere Systems Guardian Corp
Current assignee: Agere Systems LLC
Priority date: 2000-07-25
Filing date: 2001-07-24
Publication date: 2002-06-26
Also published as: GB0118019D0; KR20020009515A; JP2002134747A

Abstract

A hydrogen or deuterium containing silicon nitride or oxide layer (. é. 1-5% atomic H) is formed over a gate and/or a field oxide region. The hydrogen containing layer is used as a hydrogen source for passivating dangling bonds present at an interface between the gate oxide and the underlying silicon substrate. The activation energy for diffusing the hydrogen from the hydrogen containing layer to the interface may be provided by passing a current through the semiconductor layer 14. The hydrogen containing layer may be patterned to form a gate sidewall 38 or a field oxide sidewall 56. The passivation of the dangling bonds at the gate oxide / Si interface reduces interface trap densities to less than 10<SP>10</SP> cm<SP>-2</SP> eV and mitigates the effects of hot carrier ageing.

Description

23704 1 6

LOW TEMPERATURE PROCESS FOR

MITIGATION OF HOT CARRIER AGING

Field of the Invention

The present invention is directed to low temperature methods of forming 5 insulator material in semiconductor devices and mitigating hot carrier agin;,.

Background of the Invention

Metal oxide field effect transistors (MOSFET's) are widely used in

semiconductor products. Reliable and stable performance of these devices is dependent in part upon passivation of a high quality gate dielectric over the 10 conducting channel region. In the past great attention has been directed to formation of a high quality thermally grown silicon dioxide gate layer over the active semiconductor device layer with fully passivated silicon bonds at the interface. That is, all of the available silicon bonds along the interface should be tied up with oxygen and hydrogen. Otherwise, so-called dangling bonds form 15 interface trap defects which slow down device speed, increase threshold voltage and shorten device lifetime. The process by which these dangling bonds are tied up is known as passivation. It is commonly effected with a forming gas anneal, e.g., 10 percent hydrogen in a nitrogen environment at 425 C for two hours. While isotopes of hydrogen are believed to be more stable constituents at the interface of the gate 20 dielectric and channel region it has been even more difficult to diffuse such species to the interface because of the larger mass. For example, passivation with deuterium-based forming gas may require a ten hour anneal at 450 C. Recently it has been determined that such an anneal may be performed under pressure to more effectively diffuse hydrogen or deuterium to the oxide-channel 25 interface. See U.S. Patent Application Ser. No. 09/521, 268 filed 3/8/00 assigned to the assignee of this application. The resulting diffusion provides a relatively fast means of passivating, e.g., minutes. While proper passivation at the gate dielectric channel interface eliminates immediate problems associated with dangling bonds, it does not preclude degradation of a passivated oxide layer as hot carriers (electrons 30 or holes) move from the transistor source region through the channel region. That is, during operation highly kinetic hot carrier collisions along the gate dielectric

channel interface result in severance of Si-H bonds and creation of the aforementioned interracial trap defects. Such hydrogen Resorption gradually results in degradation of transistor performance Generally hot carrier injection continues to limit the useful life of semiconductor devices.

5 Summary of the Invention

According to the invention a semiconductor device includes a layer of insulative material having more than one percent diffusable hydrogen formed therein. There is also disclosed a semiconductor device having a first layer of 10 monocrystalline semiconductor material having a first surface and comprising silicon. A second layer formed along the first surface predominantly comprises silicon oxide. The interface between the first and second layers is characterized by a sustainable interracial trap density less than 10' cm eV. The device may include a third layer comprising silicon nitride and at least S atomic percent hydrogen.

15 In a prefelled embodiment a semiconductor device includes a first layer of semiconductor material having a field effect transistor conduction channel region

and a conducting layer is positioned over the channel region to operate as a field

effect transistor gate. A dielectric layer is positioned to electrically isolate the channel region from at least a portion of the conducting layer; and an insulative 20 region formed over the first layer comprises more than one atomic percent hydrogen. The hydrogen may include deuterium and the insulative region may comprise silicon and nitrogen.

To address problems associated with high temperature processing and hot carrier injection a method is provided for operating a semiconductor device having 25 one or more field effect transistors of the type formed with semiconductor material

and insulative material. In one embodiment of the invention an insulative material is formed on a semiconductor device by reacting silane with ammonia to deposit a layer predominantly comprising silicon, nitrogen and at least one percent hydrogen.

One method of mitigating hot carrier aging in a semiconductor device 30 includes providing on the device a layer of material comprising more than one percent hydrogen and providing activation energy to diffuse some of the hydrogen

) 3 out of the layer. The activation energy may result from conducting current through a semiconductor layer in the device.

Brief Description of the Drawings

The invention is best understood from the following detailed description

5 when read in conjunction with the accompanying figures, wherein: Figures 1-5 illustrate a first embodiment of the invention; and Figure 6 illustrates an alternate embodiment of invention.

Like numbers denote like elements throughout the figures and text. The features described in the figures are not drawn to scale.

10 Detailed Description

To facilitate description of the invention several associated concepts and

related terms are now discussed.

Semiconductor device means a body comprising any type of semiconductor material suitable for formation of a bipolar or field effect transistor which body

15 provides an electrical function performed in whole or part by one or more transistors. Semiconductor devices include integrated circuits of all kinds as well as individual, or discrete, transistors.

Silicon nitride layer as used herein means a layer of material containing silicon and nitrogen in a matrix predominantly in the form Si3N4. However, such a 20 layer may include defect regions which could provide weak bond sites for retaining hydrogen. Active device region means an active portion of a semiconductor device.

For a field effect transistor (FET) this may be a source, drain or channel region, or

any combination of the foregoing.

25 Hydrogen means the element hydrogen in any or all of its molecular and atomic forms including all isotopes having an atomic number of one. The symbol H means the isotope of hydrogen having an atomic weight of approximately one atomic mass unit. The symbol D means the isotope deuterium having an atomic weight of approximately two atomic mass units.

30 Diffusable hydrogen means hydrogen releasable from a solid layer by provision of activation energy. Such activation energy may be electromagnetic,

chemical or thermal, e.g., a temperature elevation in and about the solid layer. The mechanism of activation may be dissociation of the diffusing species from a weak bond or merely provision of sufficient energy to increase the rate of thermal diffusion. With sufficient activation energy such diffusion of hydrogen from the 5 solid layer to the interface of a gate dielectric and a channel region will be sufficient to initially passivate the interface or, during device operation, remove traps resulting from hot carrier aging. Generally, during manufacture of a device having E;ETs, the invention provides for a net loss of traps at the interface of the channel region and the gate dielectric.

10 In the past the amount of hydrogen which could be accumulated at or near the interface of the gate dielectric and channel region has been essentially limited to the number of atoms which actually passivate the dangling bonds. Provision of hydrogen in still higher concentrations at or near this interface will provide a reservoir for continued passivation to offset the creation during device operation of iS interface trap defects (by hot carrier collisions) and thereby impart greater longevity to semiconductor devices. Prior efforts to diffuse hydrogen atoms to the interface after high temperature processing, e.g., by high pressure hydrogen anneal, while effective for purposes of initial passivation, nonetheless result in provision of only a minimal volume percent (perhaps substantially less than one percent) hydrogen in 20 the various layers formed about the interface.

With reference to Figure 1 there is shown in partial cross-sectional view a semiconductor structure 10 fabricated according to one embodiment of the invention. A JET 12 is formed along a monocrystalline silicon layer 14 between a pair of isolation regions 16. The FET comprises a pair of source/drain regions IS, a 25 channel region 20, a gate dielectric 22, a gate conductor 24, e.g., comprising polycrystalline silicon, and a metal silicide layer 26, e.g., tungsten silicide, formed in situ over the layer 24. Conventionally, the gate dielectric 22 comprises a thermally grown silicon dioxide. Alternately, the dielectric 22 may comprise any of the following: SiOxNy, SiO2/Si3N2 or SiO2/SiOxNy Other oxide variants may be 30 suitable and the dielectric material may be doped with species that alter the physical or electrical properties of the layer.

The layers 22, 24, and 26 comprise a gate structure generally referred to in the figure by reference number 30. The gate structure 30 further includes a pair of conventionally formed sidewall spacer elements 34 each comprising an oxide layer 36 and a nitride layer 38; A dielectric layer 40 is deposited over the transistor 12 5 and an exemplary contact 42 to one of the source/drain regions 18 is illustrated.

Such contacts are conventionally formed of metal systems comprising W. but other metals, e.g., CoSi are appropriate.

Formation of metallization layers follows, e.g., by subtractive metal etch or Damascene formation with electroplating and passivation. A dual Damascene 10 structure is shown in Figure 1 with a plurality of metal levels 44, e.g., electroplated copper, connected to one another through via portions 46 and with levels 48 of dielectric material providing isolation between the metal levels 44. The dielectric levels 48 may each comprise multiple sublayers of deposited dielectric material and some or all of these dielectric materials may be of the type having relatively low 15 dielectric constants compared to conventional high density silicon oxides. For details regarding conventional formation of Damascene metallization structures see J.L. Yeh, et al, "Reverse Pillar Process: I. New Approaches to Interconnections in VLSI," AT &T Technical Memorandum 52168-871204-30TM, 1987; C.W. Kaanta, et al, "Dual Damascene: A ULSI Wiring Technology,"1991 EKE VLSI Multilevel 20 Interconnect Conference, pp. 144; and E. Barth, et al, "Integration of Copper and Fluorinated Silicate Glass for 0.1 Sum Interconnections," 9000 International Interconnect Technology Conference, pp. 219. For those features of fabrication not described specifically herein, any set of a variety of well-known process fabrication steps may be selected to create the structure 10. Specific choices for a 25 process design will depend on, among other considerations, device geometries, packing density and performance requirements.

The following description of fabrication details are exemplary for the

structure 10. In Figure 2 a layer 50 of silicon oxide has been deposited by low pressure chemical vapor deposition (LPCVD) over the gate structure 30 and 30 portions of the silicon layer 14. The layer 50 is then anisotropically etched, resulting in formation of the first spacer element 36. See Figure 3. This may be

done with a conventional plasma etch comprising CF /CHE3/Ar. Note, a portion 52 of the layer 50 remains about the isolation regions 16. A silicon nitride layer 56 is then deposited at low temperature. See Figure 4. Preferably this is deposited with silane or deuterated silane (Side) as follows: 5 TABLE 1

Signor SiD4 100 seem NH3 3500 sccm Temp. 650 C Pressure 900 Torr 10 Time 1 minute Deposition Rate 50 nm/minute More generally, the reaction may proceed according to any of the following ranges while still other variants are anticipated: TABLE 2

15 Signor SiD4 5 scorn -500 seem NH3 1000 seem - 5000 seem Temp. 500 C 900 C Pressure Torr - 500 Torr Time 5 Sec - 30 minute 20 Deposition Rate 50 nm/minute - 200 nm/minute To achieve a high concentration of hydrogen in the silicon nitride layer 56, the NH3 concentration should be high relative to silane and the reaction temperature should be less than 750 C. With this approach hydrogen concentration in the resulting nitride layer can be expected to exceed five atomic percent by atomic 25 weight. The hydrogen may comprise a variable amount of deuterium depending on the specific chemistry. Maximum deuterium concentration in the nitride layer may be achieved by using fully deuterated silane, although SiHxDy or a mixture of SiH4 and SiHxDy may be reacted.

Generally the reaction is 30 SiHXDy + NH3 Si3N4 + (x+3)H + Dy

The relative proportion of SiH<Dy to ammonia in the reaction process affects the net volume concentration of the diffusing species in the resulting silicon nitride layer. By varying the relative flows of reactants the concentration of the diffusing species in the deposited layer may be substantially elevated. It is possible to 5 achieve a hydrogen concentration in a Si3N4 layer of 10 to 15 atomic percent or even higher. See Table 3.

Table 3

SiH4 1000 scorn NH3 3500 seem 10 Temp 650 C Pressure 275 Torr Time 1 minute Deposition Rate 100 nm/minute Alternately, the reaction may comprise multiple species of silane: 15 SiH4+SiD4 +NH3 Si3N4+H+D For example, when 6% of the silane is fully deuterated the net hydrogen concentration in the silicon nitride may range from 3 to 5 atomic percent while the net deuterium concentration in the silicon nitride may range from 2 to 5 atomic percent. When 76 percent of the silane is fully deuterated there may be equal 20 concentrations, e.g., 5 atomic percent of hydrogen and deuterium, in the deposited silicon nitride layer.

The reaction can also incorporate one or more species of deuterated ammonia. For example: SiHXD x + NHyD3 y Si3N4 + H2 +D2 25 The hydrogen in the resulting silicon nitride layer is weakly bonded to Si and N atoms. The silicon nitride layer 56 is anisotropically etched, e.g., with C2F6/02 followed by Ar/CHI;3 to provide the second side wall element 38 with a portion 58 of the layer 56 remaining over the isolation regions 14 and the portion 52. See 30 Figure 5.

With respect to the embodiment of Figures 1-5, an advantage of the invention is formation of the nitride layer 56 and resulting element 38 with the above chemistry in a temperature ranging from 550 to 700 C. The reaction is at a substantially lower temperature and for a shorter duration than conventional 5 LPCVD furnace processes, e.g., dichlorosilane and ammonia at 750 - 800 C, 400 mtorr for approximately two hours. The low reaction temperature avoids undesirable diffusion of source/drain dopants. During subsequent lower temperature processing, e.g. , formation of dielectric layers in multi-level metallization processes (400C - 500C), there is sufficient activation energy to result 10 in substantial diffusion of free hydrogen from the deposited layer 56 to the gate dielectric 22 and the active field effect transistor region of layer 14. As a result the

gate dielectric 22 becomes passivated without requiring a separate anneal. More generally, the interface between the gate dielectric and the channel region is passivated by provision of an activation energy to release diffusable hydrogen from 15 a layer in the semiconductor device.

While not limited to any particular theory, it is believed, for embodiments of the invention having diffusable hydrogen in a silicon nitride layer, that atomic hydrogen is held at relatively weak bond sites associated with defects in the layer.

At temperatures exceeding 50 C in the silicon nitride layer and the active device 20 region, there is sufficient thermal energy to assure minimal thermal movement, e.g., less than 20 nm, of the diffusable hydrogen to the interface of the channel region and the gate dielectric.

According to the embodiment of Figures 1-5 a silicon nitride side wall spacer element is formed with this low temperature reaction, but other silicon nitride 25 layers may be formed with the same or a similar chemistry to effect substantial diffusion of hydrogen to the gate dielectric 22. For example, in high density SRAM circuits, commonly formed as integrated components of circuit devices including microprocessors, spacings between transistor structures are often reduced by formation of a so-called nitride liner having etch properties which assure formation 30 of the contact 42 without incurring a short to the gate structure. This is sometimes referred to as a self-aligned contact. See figure 6 which illustrates the transistor 12

of Figure 1 incorporated into such a device structure 60 wherein like reference numerals are used to identify components or features similar to those already described with respect to the other figures. In addition, a silicon oxide layer 60 has been formed over the semiconductor layer 14 after spacer formation; and a silicon 5 nitride layer 62 has been formed over the silicon oxide layer 60.

With the layers 60 and 62 in place a window for the contact 42 is etched through the nitride layer 62 and the oxide layer 60 down to the source/drain region 18. The invention may be applied to the structure 60 of Figure 6 by depositing the nitride layer 62 according the reaction of Table 1.

10 Summarily, a sequence for fabricating the structure 60 of Figure 6 may follow the sequence leading to the structure of Figure 5 with the subsequent deposition of the layers 60 and 62. The layer 60 may be deposited by a low pressure chemical vapor pressure deposition (LPCVD) of TEOS (Tetraethyl Orthosilicate), approximately 100 angstroms. The TEOS may be deposited at 650 C and 400 mtorr.

15 Next, the nitride layer 62 is deposited according to the specifications of Table 1.

Between the deposition of layers 60 and 62 it is conventional to perform a rapid thermal anneal for purposes of diffusing dopants in source/drain regions 18. Next, the layer 40, comprising boron and phosphorous-doped silicate glass (BPSG) is deposited at 480C. The BPSG is a TEOS - deposited film which may be formed 20 with 10 to 14 percent ozone in oxygen at a reactor pressure of 200 torn The layer 40 may be densified with a furnace treatment (775 C for 30 minutes in nitrogen) followed by chemical-mechanical polishing.

An etch sequence to create the opening for contact 42 begins with conventional photoresist deposition and patterning, and removal of any anti 25 reflection coating, e.g. with C2F6. The vertical contact is opened through layer 40 with a C4F /CO/Ar etch chemistry. This is a timed etch terminating about 1500 rim above the nitride layer 62. The remainder of the oxide is penetrated with a C /CH2F2/Ar chemistry (selectivity > 30:1). The opening is extended through silicon nitride layer 62 with a CH2F2/O2/Ar chemistry.

30 In the past, formation of the silicon nitride layer from silane and ammonia in a conventional furnace has been known to result in the deposit of gaseous reaction

products, e.g., clusters of silicon nitride formed in the gaseous state. One feature of the invention is the formation of the silicon nitride layers without inclusion of such deposited clusters. The reactions as described in the tables are most preferably performed through a chamber volume less than five percent that of a conventional 5 furnace. With the recommended reactant flow rates such clusters or defects will not deposit with a single wafer processing tool such as available from Applied Materials, Inc. of Santa Clara, California.

More generally, to avoid formation of clusters in the silicon nitride layer, the ratio of reactant flow rate to chamber volume should be sufficient to assure that such 10 reaction products are evacuated from the chamber and only products formed at or near the deposition surface comprise the silicon nitride layer. In this manner a high quality insulator film can be formed with silane and ammonia. The preferred chamber volume for the reaction of Table 1 is 2500 cm3. This results in a ratio of silane flow rate to chamber volume of 0.04 sccm/cm3. More generally, the ratio of i5 siiane flow rate to chamber volume will range between 0.002 sccm/cm3 and 0.2 sccm/cm3; and the ratio of ammonia flow rate to chamber volume will range between 0.4 sccm/cm3 and 2 sccm/cm3.

Method and structure have been illustrated for passivating dangling bonds associated with an active device region by diffusing hydrogen from a solid layer to 20 the active region. The solid layer may be formed of a silicon oxide (e.g., by plasma enhanced chemical vapor deposition) rather than silicon nitride: SiD4 + 2N2O SiO2 +2N2 +4D, or, more generally, SiHXDy + 2N2O SiO, + 2N2 +xH + yD, 25 reacted at 200 - 400C. The HDP oxide layer 40 of Figure 1 or Figure 6 may be formed accordingly and the resulting oxide may comprise as much as 15 volume percent deuterium. Alternately, an oxide side wall spacer, e.g., layer 36 of Figure 1, may be formed according to the above reaction to provide a deuterium-rich oxide spacer element. With sufficient activation energy deuterium may diffuse from either 30 oxide layer to the channel region 20.

While not limited to any particular theory, it is believed for the disclosed embodiments that diffusable hydrogen is releasable from a solid layer by thermal provision of activation energy, but other means are contemplated, especially when subsequent low temperature processing is insufficient to cause passivation by 5 thermal diffusion. The activation energy may initially be in electromagnetic, chemical, thermal or other form. Thermal diffusion will result with a temperature elevation in the insulative region and active region in the range of 50 C to 100C, but preferably reaching 150 C to or higher.

An important feature of providing a solid layer with diffusable hydrogen is 10 that an activation energy which releases the hydrogen can be achieved during normal device operation. Thus there is a counter mechanism to hot carrier degradation of a passivated interface between the channel region and the gate dielectric layer. The hot carrier interface can be expected to sustain an interracial trap density less than 10' cm 2eV.

15 The invention has been described with only a few illustrative embodiments while the principles disclosed herein provide a basis for practicing the invention in a variety of ways on a variety of semiconductor structures. Other constructions, although not expressly described herein, do not depart from the scope of the invention which is only to be limited by the claims which follow:

Claims

Claims:

1. A method for passivating an interface between two materials in a semiconductor device having multiple layers of material comprising the step of releasing hydrogen from a portion of one layer of material, said one layer comprising at least one atomic percent hydrogen.

5 2. The method of claim 1 further including the step of forming said one layer of material by reacting silane with ammonia to deposit an insulative layer comprising two or more atomic percent hydrogen.

3. The method of claim 2 wherein the step of reacting silane with ammonia is effected by reacting SiHxDy with NH3 with x and y each in the range from zero to four 10 andx+y=4.

4. The method of claim 2 wherein the reaction is controlled to provide at least five atomic percent hydrogen in the layer of insulative material.

5. The method of claim 2 further including the step of: forming the insulative layer in accord with the conditions of Table 2 such that a 15 portion of the insulative material retains more than five atomic percent hydrogen.

6. The method of claim 1 performed on a device after fabrication of a field effect

transistor gate dielectric layer on semiconductor material therein, wherein the step of releasing hydrogen includes allowing the hydrogen to thermally diffuse from a layer of insulative material to passivate dangling bonds at the interface between the dielectric O layer and the semiconductor material.

7. The method of claim 1 wherein the step of releasing hydrogen includes provision of thermal activation energy to the one layer to diffuse the hydrogen to a different layer in the device.

8. A method of forming an insulator in a semiconductor device comprising the 5 steps of: reacting silane with ammonia to deposit a layer predominantly comprising silicon, nitrogen and at least one percent hydrogen.

9. The method of claim 8 wherein the reaction is performed in a chamber of predetermined volume and the ratio of silane flow rate to chamber volume is in the range O between 0.002 sccm/cm3 and 0.2 sccm/cm3.

10. The method of claim wherein the ratio of ammonia flow rate to chamber volume is in the range between 0.4 sccm/cm3 and 2 sccmlcm3.

11. The method of claim 8 wherein the step of forming the insulator is performed with a single wafer process tool at a temperature between 600 C and 750 C. 5 12. A method for forming a layer in a semiconductor device comprising the steps of reacting SiHxDy with NH3 at.a temperature below 800 C to form a layer containing at least one atomic percent hydrogen.

13. The method of claim 12 wherein multiple species of SiHxDy are reacted.

14. A method for mitigating hot carrier aging in a semiconductor device 10 comprising: providing a semiconductor layer suitable for formation of an active transistor region; providing on the device a layer of second material comprising more than one percent hydrogen; and providing activation energy to diffuse some of the hydrogen out of 15 the second material.

15. The method of claim 14 wherein the device includes an active transistor region and the step of providing activation energy includes conducting sufficient current through the semiconductor layer to elevate the temperature in the semiconductor layer and the second material layer to a level which thermally activates and diffuses the 20 hydrogen to the active transistor region.

16. The method of claim 14 wherein the step of forming the second material layer comprises deposition of an insulative material.

17. The method of claim 14 wherein the step of forming the second material comprises formation of a nonsemiconductor material.

25 18. A method of mitigating hot carrier aging in a semiconductor device having an active field effect transistor region, a gate dielectric layer formed over the transistor

region and a layer comprising diffusable hydrogen, comprising the step of diffusing the hydrogen to the active region during device operation.

19. The method of claim 18 wherein the diffused hydrogen passivates dangling 30 bonds in or about the active region.

20. A method for fabricating a semiconductor device including field effect

transistors of the type having a gate dielectric layer positioned between the gate and channel regions, comprising: forming a plurality of doped semiconductor regions about the surface of a S semiconductor layer; and reacting silane to deposit over the semiconductor layer an insulator region comprising elemental or molecular hydrogen in combination with one or more complexes from the group consisting of silicon oxide and silicon nitride.

21. The method of claim 20 wherein the net hydrogen concentration in the 10 deposited insulator region exceeds that achievable by diffusing hydrogen into the semiconductor device under a high pressure anneal.

22. A semiconductor device comprising a layer of insulative material having more than one percent diffusable hydrogen formed therein 23. The device of claim 22 wherein the insulative material comprises silicon IS nitride.

24. The device of claim 22 wherein the insulative material comprises silicon oxide. 25. The device of claim 22 wherein the insulative material comprises diffusable deuterium. 20 26. A semiconductor device comprising: a first layer of semiconductor material having a field effect transistor conduction

channel region formed therein; a conducting layer positioned over the channel region to operate as a field effect

transistor gate; 25 a dielectric layer positioned to electrically isolate the channel region from at least a portion of the conducting layer; and an insulative region formed over the first layer comprising more than one atomic percent hydrogen.

27. The device of claim 26 wherein the hydrogen is diffusable to a portion of the 30 first layer.

28. The device of claim 26 wherein the hydrogen comprises deuterium.

29. The device of claim 26 wherein the insulative region comprises silicon, nitrogen and hydrogen.

30. The device of claim 26 wherein the insulative layer comprises at least five atomic percent hydrogen.

5 31. A semiconductor device comprising: a first layer of monocrystalline semiconductor material having a first surface and comprising silicon; a second layer predominantly comprising silicon oxide formed along the first surface, the interface between the first and second layers characterized by a sustainable 10 interracial trap density less than let0/cm2eV.

32. The device of Claim 31 further including a third layer comprising silicon nitride said third layer further including at least S atomic percent hydrogen.

33. The device of claim 31 wherein the hydrogen in the third layer comprises deuterium. 15 34. The device of claim 31 wherein the hydrogen in the third layer comprises at least 5 atomic percent deuterium.