GB2365235A

GB2365235A - A circuit for simulating an impedance

Info

Publication number: GB2365235A
Application number: GB0017889A
Authority: GB
Inventors: Ranulph Henry Murton Poole
Original assignee: British Broadcasting Corp
Current assignee: British Broadcasting Corp
Priority date: 2000-07-20
Filing date: 2000-07-20
Publication date: 2002-02-13
Anticipated expiration: 2020-07-20
Also published as: GB2365235B; GB0017889D0

Abstract

A simulated inductance circuit (gyrator) 30 has first and second operational amplifiers A1 and A2 and first and second circuit terminals 11 and 12. The first circuit terminal 11 is connected to the non-inverting input terminal 13 of the first amplifier A1 and to one end of a first resistor R1. Four equal resistors R2a, R2b, R3a, and R3b, connected as two branches in parallel, couple the other end of the first resistor R1 to one terminal of a first capacitor C1. The other terminal of the capacitor C1 is connected to the non-inverting input terminal 16 of the second amplifier A2 and is coupled to ground by a sixth resistor R4. The first and sixth resistors R1 and R4 are equal. Each of the other four resistors R2a, R2b, R3a, and R3b is twice the resistance of R1. The values of the first and sixth resistors R1 and R4 and the value of the first capacitor C1 are chosen to provide a desired value of inductance between the circuit terminal 11 and 12. The second circuit terminal 12 is connected to the common ground rail of the supply to the two amplifiers A1 and A2. A compensating capacitor C2 is connected in parallel with the resistor R3b and together they provide feedback between the active output terminal 15 and inverting input terminal 14 of the first amplifier A1. The junction of the resistors R2a and R3a is connected to the inverting input terminal 18 of the second amplifier A2 and the resistor R2a is connected to provide feedback between the active output terminal 17 and the inverting input terminal 18 of the second amplifier A2. The value of the compensating capacitor C2 is chosen to prevent high frequency oscillation of the circuit 30.

Description

<Desc/Clms Page number 1> A Circuit for S mulatinq an Impedance

This invention relates to a c-lrcui'r for sJmulating an impedance. In order to produce integrated C 4 rcuits wh 4Lch can serve as or include filters, it is necessary to provide in integrated circuit form circuitry that presents inductance without using coils. Various desIgns for circuits iDrovid-ing inductance using only operational amplifiers, resistors, and capacitors are well known. Examples are described at pages 266 and 267 of "The Art of Electronics", second edition, 1989, by P. Horowitz and W. Hill (ISBN 0-521-37095-7) , pages 27 and 28 of "Microelectronic Circuits", third edition, 1991, by A. S. Sedra and K. C. Smith (ISBN 0-03-053237-X) , and pages 132 to 134 of "Analogue and Digital Electronics for Engineers An Introduction", 1984, by H. Ahmed and P. j. Spreadbury (ISBN 0 S21 31910 2) . The last of these examples inherently includes resistance at operating frequencies. A more general approach to the simulat-Lon of impedance is presented at pages 3.40 to 3.42 of "Electronic Filter Design Handbook", 1995, by A. B. Williams and F. J. Taylor (ISBN 0 07 070441 4). Fig. 1 shows a conventional gyrator or simulated inductor 10 which has a pair of circuit terminals 11 and 12. in operation, as seen from the circuit terminal 11, the gyrator 10 behaves as though it were an inductance of value L where:

R1 and R2 are the respective resistances of two resistors connected in series across the input terminals 113 and 14 of a first operational amplifier Al, R3 is the resistance of a

resistor providing a negative feedback path connectinq the active outiDut terminal 15 of the first operatLonal amplifie-- Al zo its inver'#ing input terminal 14, C1 is the capacitance of a capacitor coupling the active output ter=nal 15 of the _'_rst operational amplifier Al to the non-inverting inpu-# term-'nal 16 of a second operational amplifier A2 whose active outout terminal 17 is connected to the junction of the resistors R1 and R2, and whose --'nve--t--na input terminall 18 is connected to the junction of the res, stors R2 and R, and hence to the inverting input terminal 14 of the fi--st operational amplifier Al, and R4 is the resistance of a resistor connecting the non-inverting terminal 16 of the second operational amplifier A3 to the terminal 12. Each of the operational amplifiers Al and A2 provides at its respective output terminal 15 or 17 an output voltage with respect to ground which is established by a supply (not shown) which is connected to a common ground rail (not shown) in the circuit. It is necessary to connect the circuit input terminal 12 to the common ground rail. The terminal 11 is the input terminal to which driving voltage is applied. It will be appreciated that the supply provides positive and negative supply voltages V+ and V- to each of the amplifiers Al and A2. It will be seen that Rl, R2, R3, Cl and R4 are connected in series in that order between the circuit terminals 11 and 12, and that R2 is connected as a negative feedback resistance path connecting the output terminal 17 of the second operational. amplifier A2 to its inverting input terminal 18. According to the present invention there is provided a circuit for simulating an impedance, as defined hereinafter by claim 1, to which reference should now be made. Preferred embodiments of the present invention are defined hereinafter by claims 2 to 6.

7he 4nven#Jon will now be descr-lbed bv wav of examnle w-Ith reference to the accompanying drawings, in which Fig . 1 is a circui t diagram cl' a known simulated inductor; Fig. 2 is a diacram of a circuit equivale-z to the ind'-'Ctor Of _74Lg. 1; Figs. 3, 4 and 5 are circuit diagrams of portions separared out of the circuit of Fia. 2; Fig. 6 is a circuit diagram of an embodiment of the present invention; Fig. 7 is a more detailed circuit diagram of the embodiment of Fig. 6; Fig. 8 is a circuit diagram of a known general impedance simulating circuit; and Fig. 9 is a circuit diagram of a general impedance simulating circuit embodying the present invention. It has been found that the conventional gyrator circuit of Fig. 1 tends to oscillate at a high frequency. For example, if the components of the circuit of Fig. 1 are chosen to provide an inductance L of 10-2 henrys, wizn Rl = R4 03 ohms, R2 = R3 = 10' ohms, and Cl = '0 farads, then, with the operational amplifiers Al and A2 implemented using MAX412 dual op-amps, and the gyrator 10 connected in parallel with a further capacitor of 10' farads to form a ;Dara-',Iei resonant circuit, resonant at about- 15.6 kilohertz, in a filter circuit, it is found that the gyrator 10 oscillates at about 1 megahertz. It will be noted that, as , s usual in this type of circuit, the values of the resistors R1 to R4 are chosen to be equal.

it has now been reall'sed that the circuit of the gyrator can be sepa_ra#ted into two part's: an all-pass phase slifter a unitv-aaln invel--:#_-a amz)lifi-er. The '7' first step is to divide each of the see-saw feedback 2 -F #ors R2 and R3 nto two, as shown in F#c. 7 -esis- - a and R2b are each made twice the value of the original R2, likewise R3a and R3b, the operation of the circuit is u n ch a n g ed . 7' t is now possible to remove the d.-.-ec-connection between the inverting inputs 16 and 1.8 of the operational amplifiers Al and A2, again without affecting the oneration in anv wav. The two separated parts of the circuit can be thought of as forming a loop. If the loop is broken at a convenient point, the performance of each part - or the two parts in tandem - can he measured without difficulty. Fig. 3 shows the all-pass phase shifter separately, consisting of the second operational amplifier A2, resistors R2a, R3a, and R4, and the capacitor Cl, with all-pass phase shifter input terminals 19 and 20 and all-pass phase shifter output terminals 21 and 22. Input terminal 20 and output terminal 22 are shown grounded. The second output terminal (not shown) of the operational amplifier A2 is also grounded. In the gyrator circuit of Fig. 2, the active output terminal 15 of the first operational amplifier A! constitutes the input terminal 19 of Fig. 3. Fig. 4 shows the unitty-gain amplifier separately, consisting of the first operational amplifier A!, and the resistors R3b, R2b, and R1, with unity-gain inverting amplifier input terM4 nals 23 and 24, and un4ty-gain inverting amplifier output terminals 25 and 26. in The gyrator circuit of Fig. 2, the active output terminal 17 of the second operational amplifier A2 constitutes the 4 nput --erminai 23 of Fig. 4. The terminals 12, 24, and 26, and

--',-e second output #_e_-minal ',not shown) of --he operaz-Lonal a.-,,-- #_ 'ifier - # Al are grounded. 7he gyrator circuit input terminals 11 and 12 are, at high -_ #-eaue- - ncy, efec7:-vely shor-# C`rCUjted when, as s -s'-Ily the case, the gyrator cl-rcuit is connected e]'.ther in parallel with a capacitor to form a parallel rescnant circuit in a filter circuit, or in series with a capacitor to form a series resonant circuit in filter circuit driven by a low output impedance source. Hence, for the purposes of incorporation in a filter circuit, the circuit of Fig. 4 will therefore be treated as though terminals 11, 1# and 24 were one terminal, so that the non-inverting input terminal 13 of the operational amplifier Al is grounded. Furthermore, since in the gyrator circuit of Fig. 2 the active output terminal 17 o f the second operational amplifier A2 is connected to the input terminal 23 of Fig.4, and the all-pass phase shifter circuit of Fig. 2 has a very low output impedance, the resistor Rl is effectively replaced by the low output impedance at the terminal 17 and can be ignored. Accordingly, the circuit of Fig. 4 can be treated as the circuit shown in Fig. 5. TI the operational amplifiers, Al and A2 were "ideal" op- _L 4 ft, amps of infinite gain and no phase sh-L the all-pass phase shifter would provide a gain of +1 at high frequencies, and the unity-gain inverting amplifier would provide a gain of -1 at high frequencies. The complete loop would then have a aa-in of -1 and therefore be stable. However, a real ooamp has a gain which falls with frequency, and this falling response is associated with a phase shift. When feedback is applied to a real op-amp, the result may be a high frequency --ain peak as well as a phase sh-'- f t - ShouId the phase shift w-#-#_hin the complete loon equal 120' and --he ca-in be areazer than unity, the loo-Q will oscillate.

For the oart-icular exa.7,ple of the gyrator circuit of Fig, 2 giving an inductance I_ of !0- , henrys, the resistors R2a, R2b, R3a and R3b of Figs. il and S are, of course, 2 x 10 ohims each . was Iv measurement that w-* t- t-, e s e na rt cul ar va'; ues, and w,* th C! 10 -#' Farads and a,r,;Di--'fie--s _`I-nnlemented-# bv MI.TX'#1,2 duai op-amps, #:he all-pass phase shifter circuit of Fig. 3 and the unity-gain inverting amplif ier of Fig. nad respective gain/frequency characteristics each with a Deak at about 10 megahertz. These peaks can be removed by placing a small compensating capacitor in parallel with the negative feedback resistor -'in the res-cective circuit. To avoid a detrimental effect as regards Dhase/frecruencv resnonse in the all-pass phase shifter circuit of Fig. 3, it is preferable to apply the compensating capacitor to the unity-gain inverting amplifier circuit of Fig. 5 only. F-ig. 6 shows a gyrator circuit 30 embodying the present invention in which the feedback path of the first operational amplifier Al -'is represented by an impedance value Z. Circuit component values and voltages and currents are indicated in Fig. 6. The associated equations are shown below: i,, (V#.,. - V#) /R .......... (1) V, V ", .......... (2) jo CR V3 V_- I + jo CR .......... (3) V4 V__- .......... (4) V# V# = V; - V, .......... (5)

V5 - VI VI - V" (6) 2R z where j is the square root of minus one and co Is angular frequency of the voltages and currents. Combining (1) and (5), i- V, - 2V4) /R; (V-n + and including (4), (vi, + v, - 2v,) /R. Combining this with (3), ii,, R = vi,, + V2 2V2 1 + j(j)CICR so CR) iin R = vin + V2 + j: #R ....... (7) Eliminating v, from (1) using (2) and (6), i, (V. - V2) ,n P, = Vin #v,, + 2R z so v- = v, + i,,,. Z/2 ........ (8) Substituti-ng (8) into (7),

jo) CR) (V. 0+ jo) CR) therefore (1-jo)CR) (I - i o) CR) /2) (I+ jo) CR)' (I + CR) and '7" # (1+ -#W CR) + (1-jW CR) k11+jCO CR) - (Z/2) --P') therefore v,,/i,, = (1/2) {R(I+jco CR) - (Z/2) (1-jco CR) (9) Note that, if Z=2R, V4,,/L,# = jw CR 2 so the circuit offers an --impedance v,,..ii, equivalent to -LhaT-- of an inductor CR 2 . Now suppose that the complex impedance Z is comprised of a resistor 2R in parallel with a small capacitor c. Then Z = (2R/jco c) / #2R + (1/jw c) I = 2R/(jcoc 2R +1). If 1/c 2R = L),, Z = 2R/I(jw/w-) +11. ...... (10) Inserting (10) into (9) and calling 1/CR = w,, (R/2) 'l+jw/cj, (R /2) (1 -j(,)/w,) / (1- j a) A), IR/2) - f (I + JO) / W(') (I + jW 0), (1 - JO) O)C,), + JO) / 0), + j (d / (VO -#. J (d '/ o (W 0), ) ((d (J" 0' 0) (R/2)(

#2(jo) loo)+Jo) 1co, -(w loo)(w lwl)#- (1+JO) /C91) Multiplying numerator and denominator by (1-jw/w#) (R/2) #2(jw /(00)+Jo) /0), -(W /00)(0) 10)1)J(1-Jo, lwl) (1+J(O /Col)(1-JO, /0)1) (R/2) - #2jo) Iwo +Jo) /W' _W2 WOO)i + 2w 2 / woo)l + 0) 2 /0) 1 2 +jo) 1 /000)1 2 ]+(0) /0) + (W 0) 1 )2 2 /( 21 (R12)(jw 1wO)f2+wO1w1 +(R12)#w' 1wo(t),+C0 1) 1 ,+(a) /(, ,)1)2 If vi,,/ii,. - R (jw/wo) - an inductor of value R/w,,,or R 2C as expected. Normally, (L)/Wl ) 2 < < So v,,/i,, = (R/2) (jcj/w#)f2+(,),/G)J4-(R/2) The effect of the compensation is therefore to increase the inductance of the gyrator by a fraction (1/2) (wo/w,) . Generally this is a very small amount. If, as a typical example, w, is taken as 2ri x 16 kHz, and w, as 2ri x 3 MHz, the fractional increase is 1 part in 375. Such an error is easily absorbed by the adjustment that must be provided to accommodate normal component tolerances. The comoensation a! SC 4 ntroduces a resis#'Jve term (R12# (,)I) Al-hough thJs appears negligible at: -F-'--st sight, -J# -an represent an appreciable loss of Q. If #:he gyra7-or is used

a s r. a r t o f a -# u n e d c I r c -,-: I', t o f _- e _- c - a n a gu I a r _` r e -,.I e n c v h e ,iponent becomes T h e Q c e tu n e d res' Stive con C -, r cu 1 :1 s i v e n b v [inductive impedence] 0 / (o 0) Q series resistance (R 2)((o 0 / w, or Q = 2w# /w,. In this example, the maximum possible Q of the tuned circuit is 375. In practice, the Q is likely to be less than this, because of otlier phase shifts within the gyrator and the power factor of the resonating capacitor. To check the performance in a practical app '. 4 cation, the comDensated circuit was used as the inductive element in a parallel tuned circuit. With the inductance of the compensated circuit equal to 10 mH, if the resonating capacitor is made equal to C, the resonant frequency is given by fo =(1/2ri) x V#11(R'C x C)) = (1/2n) x 1/(RC) = (1/2n) x 10' or about 16 kHz, where R = 103 ohms and C = 10' farads. Fig. 7 shows a practical embodiment, of the invention in the form of a gyrator circuit 30 --or--espcnding to the circuit of Fig. 6 O'-t In wnich -the general -imnedance Z providing feedback between the output terminal -1-5 of the first operational amplifier Al and _L#_s inverting input te--m-Lnal 1-4 is shown explicitly as a resistor R3b with a compensating capacitor C2 in paraLle-1. With the --Following component values, the circuit of Fig. 7 provides an inductance of !0 millihenrys:

Rl = R4 = 103 ohms R2a R2b = R3a = R3b = 2 x 103 ohms C1 # 10 nanofarads c2 = 27 picofarads Amplifiers Al and A2 are MAX412 op-amps. The circuit is designed to provide parallel resonance with a capacitor of 10 nanofarads at about 16 kilohertz. Fig. 8 shows a generalized impedance converter circuit corresponding to the circuit described with reference to Fig. 3 - 31 on page 3.40 of "Electronic Filter Design Handbook" by A. B. Williams and F. J. Taylor, published by McGraw-Hill in 1995, ISBN 0-07-070441-4. The impedance presented between the terminals 11 and 12 in the circuit of Fig. 8 is given by Z1.Z3.Z5 Z2'Z4 if Z1 = R1 Z2 = R2 Z3 = R3 Z4 =(l/wCl) and Z5 R4, then Z 1. Z3. Z5 R 1. R3. R4 Z2.Z4 R2. (1 / wC 1)

and if R3 = R2, the impedance is a)C1.Rj_.R4 i.e. an inductive 4 mpedance wL wC!.Rl.R4.

According to the present invention, the conventional circuit of Fig. 8 is modified to the circuit of Fig. 9, in which the negative feedback impedances of the two operational amplifiers Al and A2 are in effect split and separated by being replaced by imiDedances Z2a, Z2b, Z3a, and Z3b, and the direct connect-'on between the inverting input terminals 14 and 18 of the operational amplifiers Al and A2 being removed.

in the circuit of Fig. 9 it is possible to use values for the impedances Z2a, Z2b, Z3a, and Z3b which are individually selected to provide the optimum characteristics for the circuit in its context in use. Four nodes, 19, 21, 23, and 25 are indicated in Fig. 9 which correspond to the terminals 19 and 21 of Fig. 3 and 23 and 25 of Fig. 4.

The general impedance converter circuit of Fig.9 can be separated into two parts for analysis similarly when it is shunted by a low impedance, and hence this analysis is relevant when the circuit is driven by a source which has a low impedance at high frequencies. In particular, the feedback impedance Z2a should have a value chosen to ensure that the gain v. frequency characteristic of the par-, of the circuit between the terminals 19 and 21 and including the second operational amplifier A2 does not include a peak, i.e. the impedance Z2a should be chosen to eliminate any peak in the gain v. frequency characteristic which might occur if Z2a = 0, in other words if the second operational amplifier A2 were provided with 100% negative feedback. Sirr-ilarly, the feedback impedance Z3b should have a value chosen to ensure that the gain v. frequency characteristic of the part of the circuit between the terminals 23 and 25 and including the first operational amplifier Al does not include a peak, i.e. the impedance Z3b should be chosen to eliminate any peak in the gain v. frequency characteristic which might occur if Z3b = 0, in

other words if the first operational amplifier Al were provided with 100% negative feedback.

Claims

CLAIMS A circuit for slimulaz_`ng an. -imcedance, tte rcu4 C OMP' Sln#-: Llrsz and secc-c operaztlona_ a=__'Z#ers, eacn. opera-:icnal amplifrier havJ no a ncn-i-ver- -ncr inpur -ermi na' , an inver:iing input terminal, and an active output terminal; a f 4 IrS.:# circu4t term#nai connected tio tihe nor-4nvertina input terminal of the firs#n operat-onal amplifier; a second cir CU4 t -ermi-a- connected to a corrmon gro'-ind terminal of the c-i-rcuit; first and second imuedance means connected in series and coupling the first circuit term-'#.nal to the inverting J.nput terminal of the f i rst operational amplifier; third impedance means connected in series with the first impedance means and thereby coupling the first circuit terminal to the inverting input terminal of the second operational amplifier, the active output terminal of the second operational amplifier being connected to the junction of the first and third impedance means whereby the third impedance means provides feedback between the active output terminal of the second operational amplifier and the inverting input terminal of the second operational amplifier; fourth impedance means connected to provide feedback between the active output terminal of the first operational amplifier and the inverting input terminal of the first operational amplifier; fifth impedance means connected in series with the third impedance means between the active output terminal of the first operational amplifier and the inverting input terminal of the second operational amplifier whereby the series combination of the 'third and fifth 4 mpedance means is connected in ")aralle# with the series combination of :'he second and fourth _'mpedance means; and sixth and seventh inipedance means connected in series with one another and coupling the active cu#_pput I-erminal of the first operational amplifier to the second c-Lrcui# terminal, with the

<Desc/Clms Page number 15>

Junction of the six#_'-. and seven--h impedance means connected !:C. the ncy,-Inver--Ina 1-;Du-_ #:ermlna_' of the second Ooera:#_-onal a=)iifier. circui accord. -nc 1-o cla-",m 1, charac-.e-sed #n f: s t, second, third, f ifth ard sever,!#h impedance means are substantially purely resistive, the sixth impedance means is substantially purely capacitive, and the fourth impedance means comprises resistance and capacitance. 3. A circuit according to claim 2, characterised in that the first and seventh imDedance means have equal values of resistance, that the second, third, fourth, and fifth impedance means have equal values of resistance, that the resistance values of each of the second, third, fourth, and fifth impedance means is twice the resistance value of each of the first and seventh impedance means, and that the capacitance value of the sixth impedance means is greater than the capacitance value of the fourth impedance means. 4. A circuit according to claim 1, characterised in that -the third and fourth impedance means are selected to stabilize operation of the circuit. 5. A circuit according to claim 4, characterised in that a-least one of the third and fourth impedance means is selected to prevent inflection of an open-loop gain versus frequency characteristic of the part of the circuit includIng the operational amplifier for which the said one impedance means Drovides feedback. 6. A s1mulated inductance cl'rcuit comiDrisina: a first circuit terminal connected to one end of _L the first resistor and to the non-inverting input terminal of a first operational amplifier, the other end of the first _resis:_-or beina onnec'#ed to resiDecLive ends a second resistor and a third

<Desc/Clms Page number 16>

resistor and to the active output terminall of a second op,erational amplifier; #o'_rtn- and f4l-'- res-.szr--rs with one en,4 ±he resistor connected to the other end of the second resistor, and cne end -c f the -L' i fth re s i stor ccnn e c--e,--' to the ot.-e r end o third resistor, the respective other ends of the fourth and f-fth resistors being connected together and to the ac'#ive output terminal of the first operational amplifier and to one terminal of a capacitor having its other terminal coupled to a common around -termina-, of the circuit by a s-Lx::h resistor, the respective resistance values of the first and sixth resistors being equal, and the respective resistance values of the second, third, fourth and fifth resistors being equal and being twice the resistance value of the first resistor; and a compensating capacitor connected in parallel with the fourth resistor, the junction of the second and fourth resistors and the compensating capacitor being connected to the inverting input terminal of the first operational amplifier whereby the parallel combination of the fourth resistor and the compensating capacitor provide a feedback path between the active output and inverting input terminals of the first operational amplifier, and the junction between the third and fifth resistors being connected to the inverting input terminal of the second operational amplifier whereby the third resistor provides a feedback path between the active output terminal and the inverting input terminal of the second operational ;_--m.plifier, and the value of the capacitance of the compensating capacitor being chosen to prevent oscillation of the circuit at a -freauencv which is high relative to the intended frequency or band of frequencies of use of the circuit. A circuit for simulating an impedance, substantially as described hereinbefore with reference to Fig. 9 of the accomnanying drawings .

<Desc/Clms Page number 17>

8 . A circuit for SiMU!at4ng an inductance, substantially as described hereinbefore with reference to FJg. 6 or of the accompanying drawings.