GB2364188A - Multi-path sigma delta modulator - Google Patents

Abstract

A multi-path sigma-delta modulator (40) has a sample and hold (S/H) section (41) that converts a received analog signal (25) into quadrature and in-phase signals (45,46) and first and second sigma-delta A/D converter stages (52,53) coupled to the S/H section (41) to convert the respective quadrature and in-phase signals into digital output signals, wherein the S/H section (41) and the sigma-delta A/D converters (52, 53) are controlled by non-overlapping clocks wherein the duration of the S/H clock (P1) is shorter than the duration of the sigma-delta A/D converter stage clocks (P2A,P2B).

Description

2364188 MULTI-PATH SIGMA DELTA MODULATOR

FIELD OF THE INVENTION

The present invention relates generally to sigma- delta modulators in analog to digital (A/D) converters, and more specifically to multi-path bandpass sigma delta modulators.

BACKGROUND OF THE INVENTION

In digital wireless communication applications, such as radio and cellular systems, basic sigma-delta modulators typically form part of switched capacitor network forming a bandpass and low pass A/D converter.

Such sigma-delta modulators are easy to implement in conventional integrated circuit processes, and achieve high performance and resolution with precise timing integrated clock speeds and highly oversampled analog input signals.

However, in some applications where a basic sigma- delta modulator is implemented, either a gain error or a phase error in the FM modulated signal causes harmonic distortion of the demodulated output The harmonic distortion at the demodulated output degrades the overall performance of the receiver, which can be rated by the signal to noise and distortion ratio (SNDR) It is expected that for some applications, for example state of the art digital FM receivers, a performance level of 66 d B SNDR will be required For such an application the maximum acceptable gain error is 0 2 % for a zero phase i error, or the maximum acceptable phase error is 0 0002 rad for a zero gain error For a zero gain error, the specified phase error defines the maximum skew in time between the two sampling edges which is further dependant on the IF frequency For example, with an upper IF frequency of 25 M Hz, the skew must be less then 13 ps which has been unachievable in the prior art.

U 5544353 describes a sixth order muli-bit single-path implementation of the bandpass sigma-delta two step A/D converter A signal flow diagram of a single band pass sigma-delta modulator used in such a two step A/D converter is shown in FIG 1 The single path structure of U 5544353, discussed further below, provides adequate performance, however the structure has high power dissipation.

In attempt to overcome high power dissipation associated with single-path bandpass sigma-delta modulators, bandpass sigma-delta A/D converters with a two-path architecture have been implemented For example, in the IEEE Journal of Solid-State Circuits, Vol 32, No.

12, December 1997, an article entitled "A Two-Path Bandpass SA Modulator for Digital IF Extraction at 20 M Hz " by Ong et al at pp 1920-1934 describes a two-path architecture for a fourth-order, bandpass modulator.

While the two-path structure provides lower power dissipation, there are weaknesses such as phase and gain error limitations as discussed in the article The prior art structure, as shown in FIG 2 and discussed below, is formed of two low-pass sigma-delta modulators that are clocked by non-overlapping clocks, as shown in timing diagram in FIG 3 In such a configuration, the sample and hold (S/H) circuits of the in-phase (I) and quadrature (Q) components are clocked with different clocks The two clock signals are derived from a higher clock frequency by a combinational network Due to inherent unavoidable matching errors of the propagation delay time within the clock generator, there is a phase error between the two sampling clocks Also, gain errors between the I and Q components are caused by any differences in gain between the two bandpass sigma-delta modulators of the I and Q component Gain and phase mismatch between the signal transfer functions in the two paths presents a serious performance problem.

Thus, there is a need for a multi-path bandpass sigma delta modulator that overcomes the disadvantages of the above discussed circuit arrangements in order to meet both performance and power dissipation requirements of applications such as state-of-the-art digital wireless communication applications.

BRIEF DESCRIPTION OF THE DRAWINGS

Preferred embodiments of the present invention will now be described with reference to the accompanying drawings in which:

FIG 1 is a signal flow diagram of bandpass sigma- delta modulator used for example in a single path implementation of the prior art;

FIG 2 is a circuit block diagram of a two-path sigma-delta architecture of the prior art;

FIG 3 is a timing diagram for the prior art structure of FIG 2; FIG 4 is a circuit block diagram of a two-path sigma-delta architecture of an embodiment of the present invention; FIG 5 is a timing diagram of the two-path sigma delta architecture of FIG 4; FIG 6 is an embodiment of a more detailed circuit diagram of the S/H and mixer stages shown in FIG 4; FIG 7 is an embodiment of a more detailed circuit diagram of the S/H and mixer stages shown in FIG 4; FIG 8 is a timing diagram of the S/H and mixer stage of FI Gs 6 and 7; FIG 9 is a circuit diagram of a resonator, as referred to in signal flow diagram of FIG 1 of the prior art, in a sigma delta modulator applied in an embodiment of the invention; FIG 10 is a timing diagram of the resonator of FIG.

9; and FIG 11 is a block diagram of two-step four-bit charge-redistribution of a two step A/D converter of a sigma-delta modulator applied in an embodiment of the invention.

DETAILED DESCRIPTION

To better understand embodiments of the invention, configurations of the prior art discussed above will first be described with reference to FI Gs 1-3 Referring to FIG 1, a signal flow diagram of a bandpass sigma-delta modulator of the prior art is shown The bandpass sigma- delta modulator represented by the signal flow diagram of FIG 1 is described in U 5544353 The architecture of U 5544353 is commonly classified as a sixth order multi-bit single-path implementation of the bandpass sigma-delta two step A/D converter The sigma-delta bandpass modulator represented by the signal flow diagram of FIG 1 may be a two-step A/D converter 1 that receives an analog input signal 4 at a first band pass sigma-delta modulator 2 which converts the received analog signal 4 into an intermediate analog signal 5 and a first digital signal 6.

A second bandpass sigma-delta modulator 3 is coupled to the first bandpass sigma-delta modulator 2 to convert the intermediate analog signal 5 into a second digital signal 7 A digital filter (not shown) is coupled to the first bandpass sigma-delta modulator 2 and the second sigma- delta modulator 3, and converts the first digital signal and the second digital signal to the digital output signal.

F 6 In the first bandpass sigma-delta modulator 2, an analog signal 4 is received, and the first predetermined fraction of the analog input signal is summed by first summing device 15 with the first predetermined fraction through unit delays z, and Z 2 of a first feedback signal 8 to provide a first error signal 9 The first error signal 9 is bandpass-filtered through second summing device 16, a first D/A converter (DAC) 10 for example a one bit D/A converter, and unit delays z 3 5 to produce a first intermediate analog signal 5 The first intermediate analog signal is quantized through quantizer 12 for example a one bit quantizer and unit delay Z 6 to provide a first digital signal 6 The first digital signal is D/A converted to provide another feedback signal to the first summing device 15.

In the second bandpass sigma-delta modulator 3, a second predetermined fraction of the first intermediate analog signal 18 is summed at a third summing device 17 with the second predetermined fraction of a second feedback signal 14 to provide the second error signal.

The second error signal is bandpass-filtered through unit delays z 7 9 to provide a second intermediate analog signal 19 The second intermediate analog signal 19 is quantized through quantizer 13 for example a four bit quantizer to provide a second digital signal 7 The second feedback D/A converter (DAC) 11 for example a four bit D/A converter provides the feedback signal after converting the digital output signal to analog form The first and second digital signals 6 and 7 are filtered (not shown) to provide first and second filtered signals, respectively, and the two signals are summed to provide a digital output signal.

The bandpass sigma-delta structure of U 5544353, shown in FIG 1, provides adequate performance, however the structure has high power dissipation.

As mentioned above, FIG 2 is an example of a circuit block diagram of a two-path fourth order sigma- delta band pass modulator implemented in receiver architecture 20 of the prior art FIG 2 shows a simplified block diagram 23 for digitising a narrow band IF signal 25 with an oversampled bandpass sigma-delta modulator In such an application, a radio frequency of 87.5 108 M Hz Frequency Modulated (FM) signal 24 is received through a superheterodyne receiver 21, and passed through to tuner 22 to transform the received FM signal 24 into an Intermediate Frequency (IF) signal 25 of, for example, 10 7 M Hz The tuner includes, for example, band pass filter as band select filter (BSF) 27, low noise amplifier (LNA) 28, mixer 29, local oscillator (LO) 32, automatic gain control (AGC) 30 and band pass filter (BPF) such as station/select filter 31.

The IF signal 25 is passed through the A/D converter 23 and the bandpass signal is converted into the digital domain at the IF location where the low-pass in-phase (I) and quadrature (Q) components are separated A drawback X 6 of this configuration is that the sample and hold circuits (not shown) of the I and the Q components are clocked with different clocks P 3 and P 4 These two clock signals are derived from a higher clock frequency by a combinational network (not shown) Since there is unavoidable matching errors of the propagation delay time within the clock generator there is an inherent phase error between the two sampling clocks P 3 and P 4 This is shown in FIG 3, which is a timing diagram for the prior art structure of FIG 2.

The I-sampling edge 33 is shown for clocks P 3 and the Q- sampling edge 34 is shown for clocks P 4 over time, P 3 (t) and P 4 (t), respectively in FIG 3.

Another disadvantage associated with the A/D converter 23 shown in FIG 2 is that there are gain errors between the I and Q components which are caused by any differences in gain between the two band-pass sigma-delta modulators of the I and Q components.

FIG 4 is a circuit block diagram of a two-path sigma-delta architecture 40 in accordance with an embodiment of the invention The architecture of the bandpass sigma-delta configuration has a shared sample- and-hold (S/H) section 41 The S/H section receives the IF signal 25, which may be provided for example by a receiver and tuner configuration as discussed above and shown in FIG 2 The two-path sigma-delta architecture 40 of FIG 4 comprises a common S/H section 41 comprising a S/H stage or circuitry 42 with clock Pl and mixer-1 circuitry 44 The S/H section passes the signals representative of the I and Q signals 45 and 46 to the separate paths 47 and 48 of two path bandpass sigma delta architecture 43, respectively While FIG 4 shows a two- path topology, it will be appreciated that the principle of the shared S/H stage may be applied to a multi-path or N-path bandpass sigma-delta topology.

In the two path bandpass sigma-delta stage 43, each I and Q path 47 and 48 may have a bandpass or for example a lowpass sigma-delta A/D converter stage 49, digital quadrature mixer stage 50, and decimating digital filter stage 51 that are configured separately in parallel paths 47 and 48 Thus, along each I and Q path 47 and 48 there may be separate devices along each path, i e band-pass sigma-delta modulators (BP-SD ADC) 52 and 53, mixers (mixer-2) 54 and 55, and decimators 56 and 57 In this embodiment, for example, bandpass sigma-delta modulators 52 and 53 may be identical and may be of the two step A/D converter configuration as shown in FIG 1 and described above.

The S/H section 41 provides from mixer 44 a signal to the two path sigma-delta stage 49 which provides digital signal to corresponding digital quadrature mixer stage 50 and decimating digital filter stage 51 As shown, the digital quadrature mixer stage comprises mixer-2 54 along the first I path 47, and mixer-2 44 along the second Q path 48 Similarly, decimating digital filter stage 50 comprises decimator 56 along the first I path 47 and decimator 57 along the second Q path 48 The decimating digital may be electrically coupled to a digital signal processor (DSP) 39 that processes the decimated quadrature digital signal and the decimated in-phase digital signal to produce a baseband digital audio signal 59.

The two paths are clocked by clocks Pi, P 2 A and P 2 B to form a two phase non-overlapping clocking system, respectively, for controlling the switched capacitive networks of the bandpass sigma-delta modulators 52 and 53.

Clocks P 1, P 2 (A-B) are generated from a clock generator or module (not shown) as discussed above with reference to FIG 2 Such clock generators are known in the art In FIG 4, the clock generator receives a higher frequency clock frequency, e g 28 5 M Hz, which may be conveniently chosen as twice the clock frequency of Pl in the combinational network (not shown) in combination with delay elements, which are known in the art However, the configuration of FIG 4 avoids any phase errors between the I and Q sampling by construction and overcomes the most stringent performance limitation of the prior art.

The two-path sigma-delta modulator of FIG 4 is not sensitive to the skew between different clock edges This improves the performance by both increasing the linearity and decreasing the quantisation noise.

A timing diagram of the two-path sigma delta architecture of FIG 4 is shown in FIG 5 The I-sampling edge 59 and the Q-sampling edge 60 is shown for clocks P 1, P 2 A, and P 2 B over time Pl(t), P 2 A(t), and P 2 B(t), respectively in FIG 5.

It will be appreciated that the bandpass sigma-delta modulators shown in FIG 4 may be implemented as switched capacitor (SC) networks Active SC networks in general are based on amplifiers used to transfer charges between capacitors, and therefore the settling of the active network is an essential criteria of the SC network which must occur with the allocated time In the sigma-delta modulators shown, amplifier settling of the two bandpass converters of the I and Q signal paths 47 and 48 are taking place while either clocks P 2 A or P 2 B are high In order to maximise the available settling time for the purpose of minimising the overall power dissipation of the IF data converter, rather narrow Pl clocks can be chosen.

Thus, the duration of the clock Pl is of narrower or shorter duration than the duration of the sigma-delta A/D converter stage clocks P 2 A and P 2 B Considering non- overlapping clock constraints, this increases the available settling time, for example 1 6 times, which would result in 38 % savings in power dissipation considering a first-order settling model of the amplifier.

The power savings is also higher in cases where the settling model is expanded to further include non-dominant poles of the amplifier as well as finite switch resistors in the switched capacitor network Additionally, the two- path implementation of the bandpass sigma-delta modulator furthermore leads to network simplifications and power savings over the prior art since it enables the \ 5 implementation of the multi-bit quantizer in a two-step, charge re-distribution A/D converter architecture.

A more detailed circuit diagram of the S/H and mixer stage 41 shown in FIG 4 is shown in FIG 6 The preferred embodiment of the shared S/H circuitry 42 with subsequent mixer stage 44, is formed of switches 51-55, capacitors 66 and 67, and the transmission gate 68 The IF input signal is applied differentially to the input terminals IP and IN of the S/H network The S/H network is insensitive to stray capacitance and samples the differential IF signal on inputs IP and IN with the falling edge of clock signal Pl and stores the time- discrete charge packages temporarily on the sampling capacitors 66 and 67 The switches 51-55 may be implemented by means of NMOS devices Transmission gates 68 may be formed of a PMOS and NMOS devices connected in parallel, which are controlled by complementary control signals applied to their gates Switches 58-511 form the mixer stage 44 Transmission gates 61-64, switches 56 and 57, and capacitors 72 and 73 form the one bit D/A converter, which is part of the feedback network of the sigma-delta modulators A one bit quantizer (not shown in FIG 6) controls the D/A converter, which provides the two control inputs RP and RN The input voltage range of the sigma-delta modulator is set by the reference voltage VR=Vrefp Vref N and the capacitor ratio, i e capacitors 72 and 73 with respect to capacitors 66 and 67.

Another embodiment of the S/H stage is shown in FIG.

7 and may include other means of minimising power by means of trading the amplifier settling time against the Pl clock duration For example, while the S/H network and mixer stage is the same as in FIG 6, the D/A converter may be arranged in a different manner For example, the one bit D/A converter may be configured by means such that the current taken from the reference network, i e S/H stage, can be decoupled from the bandpass sigma-delta modulator and hence signal injection from the sigma-delta modulator to the reference is reduced The coupling of the reference may be arranged by means of an inverting SC delay module formed of the devices 512-518, capacitors 80 and 81, and transmission gate 82 Any signal on the reference is undesired and may degrade the performance of the data converter since it will modulate its output.

FIG 8 is a timing diagram of the S/H and mixer stage of FI Gs 6 and 7 As shown in FIG 5, the I sampling edges 59 and the Q sampling edges 60 are indicated in FIG.

8 The particular clocking structure allocates sequential time slots of different duration for the passive S/H stage enabled with the Pl clock and for the amplifier settling of the D/A converter (not shown) controlled by P 2 lA,Bl.

By means of extending the duration of the P 2 lA,Bl clocks at the cost of truncating Pi, the requirements of the amplifier with respect to settling time and bandwidth are relaxed This allows dimensioning the amplifier for a lower slew-rate and bandwidth, which in turn saves power as discussed above The Pl clock may be truncated since t the Pl clock merely controls the passive S/H stage having excessive bandwidth In the process of minimising the duration of the Pl clock, one must however, consider the ringing of the interconnect, such as bond wire, being triggered with the rising edge of Pl must settle to the sampling instance which takes place with the falling edge of Pi.

FIG 9 is a circuit diagram of a resonator, as referred to in signal flow diagram of FIG 1 of the prior art, in a sigma delta modulator applied in an embodiment of the invention The structure of this SC-network is representative for all three resonators shown in FIG 1.

In order to optimise the Signal to Noise Ratio (SNR) and to minimise the injection of switching noise a differential SC-network implementation has been chosen.

The well known "bottom-plate sampling" SC design concept has been systematically applied.

The circuit diagram the resonator of FIG 9 relates to the two delay modules and the 3-input summing node of FIG 1 The two delay stages are in a ring arrangement with a feedback gain of -1 such that this structure is resonating at f J/4 and hence forms the bandpass filter.

Furthermore the 1-bit DAC, part of the feedback network from the quantizer to the summing node, is contained in the network.

The 3 inputs to the summing node are inputs IlP,Nl,.

feedback of the second delay stage to the summing node, and inputs RlP,Nl The input pair IlP,Nl is controlled from the previous stage Feedback of the second delay stage to the summing node This feedback is implemented by means of capacitors C 2 lP,Nl and the associated switches.

The gain coefficient of -1 has been realised by means of cross-coupling the differential feedback signals Inputs RlP,Nl are the quantizer control inputs that are provided by combinatorial logic (not shown) which combine the 1-bit quantizer output QTZ with clock P 2 BD to RP=QTZP 2 BD, RN=QTZ_bP 2 BD respectively Inputs RlP,Nl control the 1- bit DAC, which is an integral part of the resonator.

The two delay stages forming the resonator are implemented by means of amplifier 93, capacitors CllP,Nl and C 2 lP,Nl and the associated switches.

FIG 10 is a timing diagram of the resonator of FIG.

9 With clocks P 2 B and P 2 BD being high the capacitors CSlP,Nl, CRlP,Nl and C 2 lP,Nl will be charged For example, capacitors CSlP,Nl will be charged to the differential input voltage VIP-VIN This signal is provided from the preceding resonator (or Mixer-1 stage) and settles to its final value during P 2 B The charge transfer to capacitors CSlP,Nl occurs while P 2 B is high and will terminate with the P 2 B high to low clock transition by means of opening the bottom-plate switch of CSlP,Nl.

Furthermore, as already mentioned the control inputs RlP,Nl are generated by gates which combine the 1-bit quantizer output QTZ and clock P 2 BD as RP=QTZP 2 BD; RN=QTZ_bP 2 BD respectively These inputs control the 1-bit DAC Depending on the state of the 1-bit quantizer the capacitors CRlP,Nl will be charged positive or negative to the differential reference voltage V Refp-V Ref N The SC-network causes the differential output voltage to increase or decrease by VQP-VQN = +/-(V Refp-V Ref N)CR/C 1; hence the incremental voltage change depends merely of the reference voltage and the ratio of the reference capacitor CR and capacitor Cl Additionally, the capacitors C 2 lP,Nl will get charged to the output voltage V Qp-VQN.

In transition from one clock period P, to the next clock period PN+ 1 the clocks P 2 B and P 2 BD return sequentially to the low state After clock P 2 BD has returned to the low state the clocks P 2 A and P 2 AD turn high The latter clock transition causes the charge established in the previous clock cycle on CSlP,Nl, CRlP,Nl, and C 2 lP,Nl to be transferred by means of the transconductance amplifier 93 to capacitors CllP,Nl For this purpose amplifier 93 and capacitors C 1 lP,Nl are configured as integrator during P 2 A With reference to the timing diagram shown in FIG 10 the corresponding amplifier output burst is Qn This summing operation introduces a delay of % clock period by means of storing the three inputs intermediately on capacitors CSlP,Nl, CRlP,Nl and C 2 lP,Nl.

In transition from the first half clock period (P 2 A and P 2 AD being high) to the second half period (P 2 B and P 2 BD being high) the charge of C 1 lP,Nl will be transferred to C 2 lP,Hl using again amplifier 93 but with capacitors C 2 lP,Nl connected as integrating capacitors Since C 1 lP,Nl = C 2 lP,Nl, the output voltage VQP-VQN settles to the same value as already established during the first half clock period; hence the SC-network delays the signal by M clock period, or by z 1 With reference to the timing diagram shown in FIG 10 the delayed amplifier output burst is Qn+l/2 The amplifier is active during both clock phases and performs the summation of the three input charges of CSlP,Nl, CRlP,Nl, and C 2 lP,Nl to C 1 lP,Nl during the first clock phase of the clock period; performs the charge transfer from C 1 lP,Nl to C 2 lP,Nl respectively Because of the time multiplexing of the amplifier the outputs of the first and second delay stage appear as time multiplexed signals at the amplifier outputs QlP,Nl.

An example for the particular architecture of the two-step multi-bit quantizer is that the output of the resonator is present twice during a clock period, as shown in FIG 10 This lends to a two-step A/D converter architecture shown in FIG 11 which performs the A/D conversion in two steps whereas the two most significant bits (MSB) are extracted from the first output burst, the least significant bits (LSB) from the second burst respectively The two-step A/D converter is formed of three arrays of capacitors and switches and of three comparators extracting the two MS Bs and of three arrays of capacitors and switches and of three comparators extracting the two LS Bs.

^ 5 FIG 11 is a block diagram of two-step four-bit charge-redistribution of a two step A/D converter of a sigma-delta modulator applied in an embodiment of the invention The MSB arrays of capacitors and switches (Marray) add offset to the input signal by means of charge redistribution in such manner that the three MSB comparators take their decision as follows:

If V Ip-i N-V Refp-Ref N /2 > O then MH=high; else MH=low If VIP_IN> O then MN=high; else MN=low If V Ip-IN+V Refp-Ref N /2 > O then ML=high; else ML=low With reference to the timing diagram of the resonator given in FIG 10 the offset is added by the M-array while P 2 B is high, the MSB comparators take their decisions at the falling edge of P 2 B. The LSB arrays of capacitors and switches (L-array) add also offset to the input signal by means of charge redistribution but in addition consider the state of the MSB comparators in such manner that the three LSB comparators take their decision as follows:

if MH=high & MN=high & ML=high:

If VIP-IN-V Ref P-Ref N 7/8 > Othen LH=high; else LH=low If VIP-IN-V Refp-Ref N 6/8 > Othen LN=high; else LN=low If VIP-_N-V Ref P Ref N 5/8 > Othen LL=high; else LL=low else if MH=low & MN=high & ML=high:

If VIP-IN-V Refp-Ref N 3/8 > Othen LH=high; else LH=low If VIP-i N-V Refp-Ref N 2/8 > Othen LN=high; else LN=low If VI Pi N-V Ref P Ref N 1/8 > O then LL=high; else LL=low else if MH=low & MN=low & ML=high:

If VIP-IN+V Ref P-Ref N 1/8 > O then LH=high; else LH=low If V Ip IN+V Refp-Ref N 2/8 > O then LN=high; else LN=low If VIP-IN+V Refp-Ref N 3/8 > O then LL=high; else LL=low else:

If VIP-IN+V Ref P Ref N 5/8 > O then LH=high; else LH=low If V Ip-I+V Refp-Ref N 6/8 > O then LN=high; else LN=low If V Ip-IN+V Refp-Ref N 7/8 > O then LL=high; else LL=low With reference to the timing diagram of the resonator given in FIG 10 the offset is added by the LSB array while P 2 A is high; the LSB comparators take their decisions at the falling edge of P 2 A.

It will be appreciated that in view of more complex charge-redistribution flash-type A/D converter used in the prior art, in this configuration the network complexity and the input capacitance of the A/D converter is reduced.

This reduction of complexity and input capacitance also leads to reduce the capacitive loading of resonators.

Furthermore, it is conceivable to extend the A/D converter resolution further at still reasonable complexity which would be much more costly with the flash architecture.

While the invention has been described in the context of the preferred embodiment, it will be apparent to those skilled in the art that the embodiments of the invention may be modified in numerous ways and may assume many embodiments other than that specifically set out and described above For example, the multi-path configuration may be applied to many other applications other than FM digital radio, A/D converters such as used 6 in parallel pipeline A/D converters, parallel succession approximation A/D converters, and parallel low pass sigma- delta A/D converters Also, as stated above, the two-path topology may be more than two-path, i e multi or N-path.

Accordingly, it is intended by the appended claims to cover all modifications of the invention which is defined by the claims.

Claims (14)

CLAIMS:

1 A multi-path sigma-delta modulator ( 39) comprising:

a sample and hold (S/H) section ( 41) that converts a received analog signal ( 25) into quadrature and in-phase signals ( 45,46) representative of quadrature and in-phase components of the received analog signal; a first path ( 47) for receiving said quadrature signal from the S/H section; and a second path ( 48) for receiving said in-phase signal from the S/H section, the first and second paths each comprise a sigma-delta A/D converter stage ( 49,52,53) operably coupled to the S/H section to convert the respective quadrature and in-phase signals into a digital output signal, wherein the S/H section and each sigma- delta A/D converter is controlled by non-overlapping clocks wherein the duration of the S/H clock (P 1) is of a shorter duration than the duration of sigma-delta A/D converter stage clocks (P

2 A,P 2 B) to 2 A multi-path sigma-delta modulator ( 39) according to claim 1 wherein the S/H section ( 41) further comprises a S/H stage ( 42) for receiving the analog signal ( 25), and a mixer ( 44) for mixing the analog signal into the quadrature and in-phase signals ( 45,46).

3 A multi-path sigma-delta modulator ( 39) according to any preceding claim wherein each path ( 47,48) further comprises a digital quadrature mixer stage ( 50,54,55) that mixes digital output signal with digital quadrature signals to produce a quadrature digital signal at baseband and an in-phase digital signal at baseband; and a decimating digital filter stage ( 51,56,57) that decimates the quadrature and in-phase digital signals to produce a decimated quadrature digital signal and a decimated in- phase digital signal.

4 A multi-path sigma-delta modulator ( 39) according to any preceding claim wherein each path ( 47,48) further comprises a digital signal processor ( 39) that processes the decimated quadrature digital signal and the decimated in-phase digital signal to produce a digital audio output.

A multi-path sigma-delta modulator ( 39) according to any preceding claim wherein each sigma-delta converter forms a bandpass A/D converter.

6 A multi-path sigma-delta modulator ( 39) according to any of claims 1-4 wherein each sigma-delta converter forms a lowpass A/D converter.

7 A multi-path sigma-delta modulator ( 39) according to any preceding claim wherein each sigma-delta A/D converter is a two step A/D converter.

8 A receiver comprising a multi-path sigma-delta modulator according to any preceding claim, the receiver further comprising a receiver means 21 and tuner means 22.

9 A digital radio including the arrangements as claimed in any of the previous claims.

A digital car radio including the arrangements as claimed in any one of the claims 1-8.

11 A GSM mobile handset including the arrangements as claimed in any one of the claims 1-8.

12 A multi-path sigma-delta modulator ( 39) as claimed in any one of claims 1-7 manufactured as an integrated circuit.

13 A method of converting an analog signal to a digital signal in a multi-path sigma-delta modulator comprising the steps of:

providing an analog signal ( 24,25); transforming the analog signal ( 25) in a sample and hold (S/H) section ( 41) into quadrature and in-phase signals ( 45,46) representative of quadrature and in-phase components of the received analog signal; converting the quadrature signal from the S/H section along a first path ( 47) and the in-phase signal from the S/H section along a second path ( 48) wherein the first and second paths each comprise a sigma-delta A/D converter stage ( 49,52,53) operably coupled to the S/H section to convert the respective quadrature and in-phase signals ^ 5 into a digital output signal; and controlling the S/H section and each sigma-delta A/D converter with non-overlapping clocks wherein the duration of the a S/H clock (P 1) controlling the S/H section is of a shorter duration than the duration of sigma-delta A/D converter stage clocks (P 2 A,P 2 B) controlling the sigma- delta A/D converter.

14 A multi-path sigma-delta modulator ( 39) substantial as hereinbefore described with reference to and as shown in FI Gs 4-11.