GB2360601A - Enhanced resolution attenuator - Google Patents

Abstract

The invention provides an enhanced resolution attenuator (10) for receiving input radiation (P<SB>i</SB>) and attenuating the input radiation (P<SB>i</SB>) to generate corresponding output radiation (P<SB>o</SB>), the attenuator (10) including: <SL> <LI>(a) an attenuator module (20) for receiving the input radiation (P<SB>i</SB>) and attenuating the input radiation (P<SB>i</SB>) propagating therethrough to provide the output radiation (P<SB>o</SB>); and <LI>(b) a field programmable gate array (FPGA) (60) for receiving a signal (P<SB>R</SB>) indicative of attenuation required, and for generating a corresponding drive signal for controlling attenuation provided by the attenuator module (20). The attenuator (10) differs from known attenuators in that: <LI>(c) the attenuator module (20) is operable to provide an attenuation dependent upon its temperature; <LI>(d) the attenuator module (20) includes a thermoelectric element (30) for heating or cooling the attenuator module (20) in response to the drive signal; and <LI>(e) the drive signal is derived from a PWM signal generated in the FPGA (60), the PWM signal being cyclical in nature and having a duty ratio, each PWM signal cycle corresponding to a frame, a plurality of such successive frames forming a multiframe, and the FPGA (60) being operable to modify the duty ratio of one or more frames within each multiframe for providing enhanced resolution heating or cooling of the thermoelectric element (30) and thereby enhanced resolution attenuation provided by the attenuator (10). </SL>

Description

2360601 ENHANCED RESOLUTION ATTENUATOR The present invention relates to an

enhanced resolution attenuator, in particular, but not exclusively, to an enhanced resolution variable optical attenuator for use in an optical communication system.

It is conventional practice to employ optical attenuators in optical communication systems for regulating and controlling the power of optical radiation propagating within the systems. Such attenuation is necessary in order to avoid saturating sensitive optical components such as detectors and optical amplifiers, as well as ensuring that optical radiation is of sufficient power not to be swamped by noise. Saturation can lead to loss of information and hence errors in communication traffic conveyed by the systems.

Conventional optical attenuators employ a number of different optical component configurations, for example they can comprise one or more of Mach- Zelinder interferometers, modulated liquid crystal shutters and dispersion effect modulators. In communication systems, it is particularly convenient to employ thermally variable optical attenuators providing an optical attenuation therethrough which is determined by attenuator temperature. Thus, attenuation can be selected in these thermally variable attenuators by adjusting their temperature.

Temperature adjustment is conveniently achieved by including thermoelectric elements into the variable attenuators. Such elements function by the Seebeck effect and can selectively cool or heat attenuation determining optical components incorporated within the attenuators. However, the elements often consume significant power in operation, for example 2.5 Watts corresponding to an electrical drive signal of 5 volts potential at 0.5 amps current.

Conventional optical communication systems are typically configured as a plurality of nodes interconnected by optical fibre waveguides through which communication traffic bearing optical radiation propagates from one node to another. The nodes often comprise a considerable array of optical and electrical signal processing equipment usually arranged into equipment racks, for example conventional 19-inch racks. The equipment typically incorporates numerous examples of the aforementioned thermally variable attenuator. On account of inclusion of such examples, thermal power dissipation from the attenuators can represent a considerable thermal load in the equipment racks requiring cooling facilities, for example fans for providing cooling airflow through the racks.

The inventors have appreciated that, whereas it is not feasible to reduce thermal dissipation within the attenuators because such dissipation is dictated by fundamental characteristics of their associated thermoelectric elements, it is beneficial to reduce power dissipation within electrical driver circuits which provide power to the attenuators. It is known practice when driving thermoelectric elements to regulate current flowing therethrough by using a conventional circuit comprising linear non-switching components such as series regulating bipolar power transistors driven by conventional analogue operational amplifiers. Such a circuit suffers a drawback that power dissipation within the power transistors can approach power dissipation occurring within their associated thermoelectric element. In order to address this drawback, the inventors have devised a circuit for driving a thermoelectric element of a thermally variable optical attenuator wherein the circuit employs pulse width modulation (PWM) techniques for generating a drive is signal for driving the thermoelectric element, the circuit exhibiting reduced power dissipation compared to the aforementioned conventional circuit. However, the inventors have found that such PWM techniques provide insufficient resolution of attenuator temperature control when the drive signal is synthesized digitally. Such insufficient resolution gives rise to corresponding lack of resolution of optical attenuation which creates problems in associated communication systems.

The inventors have therefore devised an improved attenuator and associated control circuit which provide power efficiency attributable to PWM operation but a variable attenuation of sufficient resolution for use in optical communication systems.

According to a first aspect of the present invention, there is provided an enhanced resolution attenuator for receiving input radiation and attenuating the input radiation to provide corresponding output radiation, the attenuator including:

(a) attenuating means for receiving the input radiation and attenuating the input radiation propagating therethrough to provide the output radiation; (b) controlling means for receiving a signal indicative of attenuation required, and for generating a corresponding drive signal for controlling attenuation provided by the attenuating means, characterised in that (c) the attenuating means is operable to provide an attenuation dependent upon its temperature; (d) the attenuating means includes temperature modifying means for heating or cooling the attenuating means in response to the drive signal; and (e) the drive signal is derived from a PWM signal generated in the controlling means, the PWM signal being cyclical in nature and having a duty ratio, each PWM signal cycle corresponding to a frame, a plurality of such successive frames forming a multiframe, and the controlling means being operable to modify the duty ratio of one or more frames within each multifrarne for providing enhanced resolution heating or cooling of the temperature modifying means and thereby enhanced resolution attenuation provided by the attenuator.

The invention provides the advantage that the attenuator is capable of providing an enhanced degree of attenuation resolution together with power efficiency benefits associated with using PWM drive signals.

Conveniently, the controlling means includes an output filter for filtering the PWM signal to generate the drive signal. Such filtration provides a benefit that PWM cycle fluctuations are not directly experienced by the attenuating means and therefore less likely to be transmitted onto the output radiation.

The PWM signal is preferably of substantially constant cycle period, and the filter is operable to attenuate PWM signal components at a frequency corresponding to the cycle period. Such filtration is effective at removing principal fluctuating harmonic signal components present in the PWM signal. Conveniently, the filter is a passive filter comprising inductors and capacitors; such inductors and capacitors have low energy losses associated therewith and hence provide energy efficient conversion of the PWM signal to generate the drive signal.

Advantageously, modifications to the duty ratio of frames within each multifrarne are substantially uniformly distributed within the multiframe. Such uniform distribution assists to reduce the magnitude of relatively low frequency perturbations in the drive signal. The duty ratio of each frame is preferably incrementable in discrete steps, the modifications to the duty ratio of the frames corresponding to one such step difference.

Conveniently, each multiframe comprises in a range of 2 to 1000 frames. This range provides a compromise between enhanced resolution and lower frequency signal fluctuations present in the drive signal. Preferably, each multiframe comprises 64 frames as a optimal compromise.

Advantageously, the attenuator is capable of providing radiation power stabilisation of the output radiation by using a negative feedback loop. In order to provide such stabilisation, the attenuator further comprises:

(a) detecting means for receiving a portion of the output radiation and generating a corresponding detection signal; (b) amplifying means within the controlling means for comparing the detection signal with a reference signal and for adjusting via the temperature modifying means the temperature of the attenuating means so that the output radiation has associated therewith a radiation power determined by the reference signal.

When implementing the attenuator in practice, it is desirable the controlling means is implemented as a field programmable gate array (FPGA). Use of the FPGA provides benefits of reconfigurability whilst employing relatively few electronic components. Preferably, the FPGA is clocked at a rate of at least 30 MHz.

The temperature modifying means requires appreciable current to operate when providing a relatively high degree of heating or cooling of the attenuating means. Thus, conveniently, the FPGA is operable to generate a PWM signal which is buffered by power MOSFETs for output to drive the attenuating means.

Embodiment of the invention will now be described, by way of example only, with reference to the following diagrams in which:

Figure 1 is a schematic illustration of an enhanced resolution attenuator according to the invention; Figure 2 is a diagram of a PWM output stage of an FPGA and low pass filter of the attenuator illustrated in Figure 1; and Figure 3 is a diagram illustrating a multiframe structure of a PWM signal generated in the FPGA shown in Figures 1 and 2.

Referring now to Figure 1, there is shown an enhanced resolution attenuator according to the invention indicated generally by 10. The attenuator 10 includes an attenuator module 20 thermally coupled to an associated therino-electric element 30, an optical splitter 40, an optical detector 50, a field progranunable gate array (FPGA) 60 connected to an associated timing clock 70, and an output low-pass filter 80. The attenuator 10 further comprises a first waveguide 100 connected to an optical input port of the attenuator module 20 for conveying input optical radiation Pi thereto, a second waveguide 110 connected from an optical output port of the attenuator module 20 to an optical input port of the splitter 40, a third waveguide 120 connected to a first optical output port of the splitter 40, and fourth waveguide 130 connected from a second optical output port of the splitter 40 to an optical input port of the detector 50. The waveguides 100, 110, 120, 130 are each monomode optical fibre waveguides; they can alternatively be multimode waveguides. An electrical output TI of the detector 50 is connected to a first electrical input I, of the FPGA 60. The FPGA 60 also includes a second electrical input 12 for receiving a reference input PR which determines an attenuation factor provided through the attenuator module 20. The FPGA 60 further includes an electrical output V. at which a PWM signal is output in operation; the output V. is connected to an electrical input JI of the filter 80. An electrical Output J2 of the filter 80 is connected to an electrical input 13 of the thermoelectric element 30. Finally, the clock 70 includes electrical outputs which are connected to clock (CLK) inputs of the FPGA 60.

The attenuator module 20 incorporates optical components which give rise to attenuation of the input radiation Pi propagating through the module 20 from its input port to its output port. The optical components are operable to provide a degree of attenuation which is a function of their temperature. The thermoelectric element 30 is thermally coupled to these components and operable to influence their temperature by heating or cooling them relative to ambient temperature. The thermoelectric element 30 exploits the Seebeck effect to achieve such heating or cooling.

The splitter 40 is an optical fibre coupler which is operable to couple substantially in a ratio 90% and 10% of optical radiation P,, received at its optical input port to its first and second optical output ports respectively; in practice, the ratio can be in a range 98%: 2% to 85%: 15%. The detector 50 includes a photodiode and is operable to receive optical radiation O.I.P. at its optical input port and generate a corresponding electrical signal at the -output T - 5 The low pass filter 80 is a passive filter network comprising inductors and associated capacitors. The filter 80 is operable to attenuate signal components in the PWM signal output from the output V,, above 10 kHz and especially around 40 kHz. Thus, the filter 80 is capable of converting the PWM signal into a corresponding low-frequency direct current signal for driving the thermoelectric element 30.

The FPGA 60 is a semiconductor logic device incorporating an array of logic gates which are user configurable to customize the device to particular applications. In the attenuator 10, the FPGA 60 is configured to be clocked by the clock 70 at a rate of 40 MHz. The FPGA 60 also provides an amplification function and also a PWM signal generating function.

The amplification function is used in the attenuator 10 to provide a negative feedback loop for adjusting attenuation provided by the attenuator module 20 so that the signal T1 generated by the detector 50 is similar in value to the reference signal PR. The amplification function is configured within the FPGA 60 to drive the PWM function which in turn generates the PWM signal for controlling power applied to the thermoelectric element 30.

The PWM signal function is operable to generate the PWM signal for output at the V, output, the signal being in the form of a binary signal periodically switching between a high state and a low state in a cyclical fashion. The signal has a period of 25 Lsec which corresponds to 40 kHz or, in other words, 1000 clock cycles of the clock 70. A frequency of 40 kHz for the PWM signal is chosen as a compromise between:

(a) choosing a frequency which enables practical values of inductors and capacitors to be used in the filter 80; (b) choosing a frequency which is sufficiently high so that electrical ripple in the filtered output from the filter 80 does not become amplitude modulated onto optical radiation propagating through the attenuator module 20; and (c) choosing a frequency which is sufficiently low for adequate adjustment resolution to be achieved when the PWM signal is generated digitally and derived from a master high frequency clock.

The operating frequency of the 40 MHz clock 70 is governed by the rate at which logic gates within the FPGA 60 can switch. Power applied to the thermoelectric element 30 is deterniined by the mark-space ratio of the PWM signal, in other words a ratio of the time for each cycle the PWM signal is in its first state relative to its second state. A mark- space ratio of 1: 1 in the attenuator 10 corresponds to zero power being supplied to the thermoelectric element 30.

Deviations from the ratio of 1: 1 result in heating or cooling of the attenuator module 20.

As a consequence of there being 1000 clock cycles within each PWM cycle, the attenuator can provide cooling to a resolution of 500 steps and also heating to a resolution of 500 steps; this corresponds to 9-bit resolution for heating or cooling.

Operation of the attenuator 10 will now be described with reference to Figure 1. The input radiation Pi propagates along the first waveguide 100 to the attenuator module 20. The radiation Pi propagates through the attenuator module 20 wherein it is attenuated to provide attenuated radiation P, The attenuated radiation P,, propagates to the splitter 40 where substantially a 10% portion of the attenuated radiation P. couples through the waveguide 130 to the detector 50. The detector 50 receives the portion and generates the electrical signal TI which passes to the I, input of the FPGA 60. The FPGA 60 converts the TI signal using an analogue-to- digital converter (ADC) into corresponding TI data; it also converts the reference signal PR into corresponding PR data. The amplification function then calculates a difference between the T1 data and the PR data to generate corresponding difference data. The difference data is passed from the amplification function to the PWM function which generates the PWM signal with a mark- space ratio (duty ratio) governed by the difference data. The PWM signal is then output from the FPGA 60 through MOSFET buffer power transistors (not shown in Figure 1) and therefrom through the filter 80 to the thermoelectric element 20. The FPGA 60 is effective in operation to regulate the radiation power of the attenuated radiation P, to a level related to the reference signal PR. If the reference signal PR is maintained substantially constant, the attenuator 10 will attempt to regulate the attenuated radiation P. to a substantially constant power level within an attenuation adjustment range and resolution provided by the attenuator module 20.

The aforementioned MOSFET transistors and filter 80 will now be described in more detail with reference to Figure 2. The FPGA 60 includes two output logic gates 200, 210 whose mutually antiphase outputs (K) switch between a positive supply rail (+ve) and a negative supply rail ( ve). An output from the gate 200 is connected to a gate electrode of a first power MOSFET 7- (FETI). Likewise, an output from the gate 210 is connected to a gate electrode of a second power MOSFET (FET2). A drain electrode of the first MOSFET is connected to the positive rail. Moreover, a source electrode of the second MOSFET is connected to the negative rail.

Source and drain electrodes of the first and second MOSFETs respectively are connected together and to the input JI of the filter 80.

The filter 80 includes an inductor L, connected in parallel with an associated capacitor Cl.

Moreover, the filter 80 also includes an inductor L2 connected in series with an associated capacitor C2. The input J1 is connected to a first node of a parallel resonant circuit comprising the inductor L, and the capacitor Cl. A second node of the parallel circuit is connected to a first terminal of the inductor L2. A second terminal of the inducted L2 is connected through the capacitor C2 to a ground potential (Ov). The rails (+ve, -ve) are symmetrically disposed in potential relative to the ground potential (Ov). Additionally, the parallel and series resonant circuits are designed to resonate at 40 kHz so that components in the PWM signal at 40 kHz applied to the J1 input are substantially not transmitted through the filter 80 so that the electrical signal applied to the input 13 of the thermoelectric element is substantially low frequency "direct currenC, namely substantially devoid of alternating components.

In operation, when the mark-space ratio of the PWM signal is 1: 1, the signal applied to the JI input is connected through the first MOSFET (FET1) to the positive rail (+ ve) for a period equal to a period when the JI input is connected through the second MOSFET (FET2) to the negative rail (-ve). Such a 1: 1 mark-space ratio results in an average potential around Ov being supplied to the thermoelectric element 30, namely substantially zero current through the element 30. As the mark-space ratio (duty ratio) is varied away from 1: 1, current flow will occur through the element 30 in both positive and negative directions giving rise to corresponding heating or cooling of the attenuator module 20 respectively. For example, if the output K is mostly at a potential of the positive rail, the first MOSFET (FET1) will be conducting most of the time; thereby providing a positive current flowing through the filter 80 and into the input 13 of the element 30 to Ov and thus causing heating of the module 20. Conversely, if the output K is mostly at a potential of the negative rail, the second MOSFET (FET2) will be conducting most of the time, thereby providing a negative current flowing through the filter 80 and into the input 13 of the element 30 to Ov and thus causing cooling of the module 20.

8 As described above, a problem arises with the attenuator 20 regarding resolution. The PWM frequency of 40 kHz is selected as a compron-fise and provides 500 steps of resolution for positive currents through the element 30 and also 500 steps of resolution for negative currents through the element 30. It is found in practice that such 500 steps of resolution corresponding to 9-bits resolution is often too coarse when using the attenuator 20 to regulate the attenuated radiation to a precision required in communication systems; such coarseness is a problem. Ideally, 16-bits resolution is desired but would require the FPGA 60 to clock at a frequency of 2.5 GHz which is unrealistic. One solution to the problem would be to select a lower PWM frequency; to obtain 16-bit resolution, the PWM signal frequency would have to be reduced to 620 Hz which is impractical with regard to component values for the filter 80. Another solution would be to dispense with PWM operation and employ linear regulation; such linear regulation is, however, not practical on aforementioned grounds of power dissipation.

The inventors have addressed the problem by devising a multiframe approach to generate the 15 PWM signal within the FGPA 60 of the attenuator 10. The multiframe approach will now be described with reference to Figure 3.

In Figure 3, there is shown a multiframe structure of the PWM signal indicated generally by 200.

Each cycle of the PWM signal generated by the FPGA 60 has a duration of to = 25 Lsec and is referred to as a frame. Sixty four such frames form a multiframe having a duration of 64 to.

Each frame is in a high state (+ve) for a period tI, and in a low state (ve) for a period t2. The periods t, and t2 SUM to the period to. The FPGA 60 clocks at a rate of 40 MHz enabling the periods t, and t2 to be generated with a resolution of 25 nsec: time steps t, Thus, the period t, can be expressed by Equation 1 (Eq. l):

t, = n,t, Eq 1 where nj = number of time steps t, in the period ti.

Moreover, the period t2 can be expressed by Equation 2 (Eq. 2):

t2 = LO - n, t.' Eq. 2 The number of time steps nj are modifiable by the FPGA 60 to be in a range of 1 to 1000; as described above, 1000 steps are inadequate resolution in the context of optical attenuation in a communication system. The inventors have appreciated that, although it is not possible to increase the resolution within each frame, it is feasible to enhance resolution by modifying the duration of one or more frames within each multiframe. By keeping the modification to one time step t,, the modification represents a small perturbation which is not apparent in attenuated radiation P,, output from the attenuator module 20.

For example, a slight increase in thermoelectric element drive current is desired from a situation where nj=500 for all the 64 frames of the multiframe. Using the multiframe approach, n, for frames 1 to 63 can be set to a value 500, and nj for frame 64 to a value 501. The approach thereby provides an average ni for each frame of the multiframe of 500. 015625. Thus, use of the 64 frame multiframe increases resolution by 6 bits which, combined with 10 bits resolution (1000 counts) provided within each frame, provides an overall effective resolution of 16 bits which is adequate in the context of the attenuator 10 operating in a communication system.

An issue arises when a plurality of frames within the multiframe are to be incremented each by one count, the issue concerning which frames of the multiframe to increment. When two frames are each to be incremented by 1 count, it is preferable that frames 32 and 64 are incremented, thereby distributing associated perturbations as uniformly as possible within the multiframe; this assists to prevent transient thermal fluctuations within the thermoelectric element 30 being detectable as modulation in the attenuated radiation P, Such fluctuations could arise if the frames chosen for incrementation were grouped together in one region of the multiframe.

Likewise, when three frames are each to be incremented by one count, it is preferable that frames 21, 43, 64 are incremented, and so on. Table 1 provides a list of frames to be incremented when control to a resolution greater than the step t. is required.

It can be seen from Table 1 that frames within the multiframe requiring incrementation to obtain resolution of fractions of the time step t, are distributed as uniformly as possible within the multiframe.

The multiframe approach provides a superior result compared to using a lower frame frequency to obtain for resolution because only small perturbations of one count occur within the multiframe; this represents only a relatively small temporal power deviation compared to a PWM signal not using the multiframe approach and of a frequency lower in proportional by the number of frames in the multiframe. Thus, the attenuator 10 devised by the inventors provides not only enhanced resolution but also power efficiency associated with PWM control and the 5 FPGA 60 operating at a convenient frequency of 40 MHz.

It will be appreciated that modifications can be made to the attenuator 10 without departing from the scope of the invention. Although Figure 1 illustrates the FPGA 60 providing a local feedback loop to stabilise radiation power of the attenuated radiation P,, it is possible for the FPGA 60 to receive control signals from other circuits, for example detector circuits further downstream from the attenuator 10 in the communication system, but control the thermoelectric element using the aforementioned multiframe technique applied in the PWM drive signal. Moreover, although a multiframe comprising 64 frames is described above, the multiframe can be modified to include a different number of frames, for example in the range of 2 to 1000 frames depending upon resolution requirements. Furthermore, although the FPGA 60 is described as being clocked at 40 MHz, it can be clocked at rates of at least 30 M1-1z provided that the filter 80 is suitably tuned in accordance.

Table 1

Number of frames Specific frames within the multiframe to be incremented each to have its nj value incremented by 1 count 1 64 2 32,64 3 21,43,64 4 16,32,48, 64 13,26,38,51,64 6 11,21,32,43,53,64 7 9, 18,27, 37,48, 55, 64 8 8, 16, 24, 32, 40, 48, 56, 64 9 7, 14, 21, 28, 36, 43, 50, 59, 64 6, 13, 19, 26, 32, 38, 45, 51, 58, 64 11 5, 12, 17, 23, 29, 35, 41, 47, 52, 58, 64 12 5, 11, 16, 21, 27, 32, 37, 43, 48, 53, 59, 64 13 5, 10, 15, 20, 25, 30, 34, 39, 44, 49, 54, 59, 64 14 5, 9, 14, 18, 23, 27, 32, 37, 41, 46, 50, 55, 59, 64 4, 9, 13, 17, 21, 26, 30, 34, 38, 43, 50, 51, 55, 60, 64 16 4, 8, 12, 16, 20, 24, 28, 32, 36, 40, 44, 48, 52, 56, 60, 64 17 4, 8, 11, 15, 19, 23, 26, 30, 34, 38, 41, 45, 49, 53, 56, 60, 64 18 4, 7, 11, 14, 18, 21, 25, 28, 32, 36, 39, 43, 46, 50, 53, 57, 60, 64 19 3, 7, 10, 13, 17, 20, 24, 27, 30, 37, 37, 40, 44, 47, 51, 54, 57, 61, 64 3, 6,10,13,16,19, 22,26,29, 32, 35, 38,42,45,48, 51, 54, 58, 61, 64 21 3,6,9,12,15,18,21,24,27,30,34,37,40,43, 46, 49, 52,55, 58, 61, 64 22 3, 6, 9, 12,15,17, 20, 23, 26, 29, 32, 35, 38,41, 44, 47, 49, 52, 55, 58, 61, 64 23 3, 6, 8, 11, 14, 17, 19, 22, 25, 28, 31, 33, 36, 39, 42, 45, 47, 50, 53, 56, 58, 61, 64 24 3, 5, 8, 11, 13, 16, 19, 21, 24, 27, 29, 32, 35, 37, 40, 43, 45, 48, 51, 53, 56, 59, 61, 64 3, 5, 8, 10, 13, 15, 18, 20, 23, 26, 28, 31, 33, 36, 3 8, 41, 44, 46, 49, 51, 54, 56, 59, 61, 64 26 2, 5, 7, 10, 12, 15, 17, 20, 22, 25, 27, 30, 32, 34, 37, 39, 42, 44, 47, 49, 52, 54, 57, 59, 62, 64 and so on equally distributed to 58 1, 2, 3, 4, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 28, 29, 30, 31, 32, 33, 34, 35, 36, 38, 39, 40, 41, 42, 43, 44, 45, 46, 47, 49, 50, 51, 52, 54, 55, 56, 57, 58, 59, 60, 61, 62, 63, 64 59 1, 2, 3, 4, 5, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31, 33, 34, 35, 36, 37, 38, 39, 40, 41, 42, 43, 44, 46, 47, 48, 49, 50, 51, 52, 53, 54, 55, 56, 57,59, 60,61, 62, 63, 64 1, 2, 3, 4, 5, 6, 7, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23, 25, 26, 27, 28, 29, 30, 31, 32, 33, 34, 35, 36, 37, 38, 39, 41, 42, 43, 44, 45, 46, 47, 48, 49, 50, 51, 52, 53, 54, 55, 57, 5 8, 59, 60, 61, 62, 63, 64 61 1, 2, 3, 4, 5, 6, 7, 8, 9, 10,11, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31, 33, 34, 35, 36, 37, 3 8, 39, 40, 41, 42, 43, 44, 45, 46, 47, 48, 49, 50, 51, 52, 54, 55, 56, 57, 58, 59, 60, 61, 62, 63, 64 62 1, 2, 3, 4, 5, 6,7, 8, 9, 10, 11, 12, 13,14, 16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31, 32, 33, 34, 35,36, 37, 38, 39, 40, 41, 42, 43, 44, 45, 46, 47, 49, 50, 51, 52, 53, 54, 55, 56, 57, 58, 59, 60, 61, 62, 63, 64 63 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31, 33, 34, 35, 36, 37, 38, 39, 40, 41, 42, 43, 44, 45, 46, 47, 48, 49, 50, 51, 52, 53, 54, 55, 56, 57, 58, 59, 60, 61, 62, 63, 64 64 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31, 32, 33, 34, 35, 36, 37, 38, 39, 40, 41, 42, 43, 44, 45, 46, 47, 48, 49, 50, 51, 52, 53, 54, 55, 56, 57, 58, 59, 60, 61, 62, 63, 64

Claims (1)

1. An enhanced resolution attenuator (10) for receiving input radiation (Pi) and attenuating the input radiation (Pi) to provide corresponding output radiation (P,,), the attenuator (10) including:

(a) attenuating means (20) for receiving the input radiation (Pi) and attenuating the input radiation (P1) propagating therethrough to provide the output radiation (P.); (b) controlling means (60) for receiving a signal (PR) indicative of attenuation required, and for generating a corresponding drive signal for controlling attenuation provided by the attenuating means (20), characterised in that (c) the attenuating means (20) is operable to provide an attenuation dependent upon its temperature; (d) the attenuating means (20) includes temperature modifying means (30) for heating or cooling the attenuating means (20) in response to the drive signal; and (e) the drive signal is derived from a PWM signal generated in the controlling means (60), the PWM signal being cyclical in nature and having a duty ratio, each PWM signal cycle corresponding to a frame, a plurality of such successive frames forming a multiframe, and the controlling means being operable to modify the duty ratio of one or more frames within each multiframe for providing enhanced resolution heating or cooling of the temperature modifying means (30) and thereby enhanced resolution attenuation provided by the attenuator (10).

2. An attenuator according to Claim 1 wherein the controlling means includes an output filter (80) for filtering the PWM signal to generate the drive signal.

3. An attenuator according to Claim 2 wherein the PWM signal is of substantially constant cycle period (to), and the filter (80) is operable to attenuate PWM signal components at a frequency corresponding to the cycle period.

4. An attenuator according to Claim 2 or 3 wherein the filter (80) is a passive filter comprising inductors and capacitors.

13- 5. An attenuator according to Claim 1, 2, 3 or 4 wherein modifications to the duty ratio of frames within each multiframe are substantially uniformly distributed within the multiframe (Table 1).

6. An attenuator according to Claim 5 wherein the duty ratio of each frame is incrementable in discrete steps, the modifications to the duty ratio of the frames corresponding to one such step difference.

7. An attenuator according to any preceding claim wherein each multiframe comprises in a range of 2 to 1000 frames.

8. An attenuator according to Claim 7 wherein each multiframe comprises 64 frames. 9. An attenuator according to any preceding claim wherein the attenuator (10) further comprises:

(a) detecting means (50) for receiving a portion of the output radiation (PJ and generating a corresponding detection signal (T1); (b) amplifying means within the controlling means (60) for comparing the detection signal (T1) with a reference signal (PR) and for adjusting via the temperature modifying means (30) the temperature of the attenuating means (20) so that the output radiation (PJ has associated therewith a radiation power determined by the reference signal (Pp).

10. An attenuator according to any preceding claim wherein the controlling means (60) is implemented as a field programmable gate array (FPGA).

11. An attenuator according to Claim 10 wherein the FPGA (60) is operable to generate a PWM signal which is buffered by power MOSFETs (FETI, FET2) for output to drive the attenuating means (20, 30).

12. An attenuator according to Claim 10 or 11 wherein the FPGA (60) is clocked at a rate of at least 30 M1U.

13. An attenuator (10) substantially as hereinbefore described with reference to one or more of Figures 1 to 3.