GB2360409A

GB2360409A - Frequency detector

Info

Publication number: GB2360409A
Application number: GB0113893A
Authority: GB
Inventors: Bin Wu; Richard C Walker
Original assignee: Agilent Technologies Inc
Current assignee: Agilent Technologies Inc
Priority date: 1997-07-01
Filing date: 1998-06-15
Publication date: 2001-09-19
Anticipated expiration: 2018-06-15
Also published as: GB2360157A; GB2360157B; GB0113893D0; GB0113891D0; GB2360409B

Abstract

A frequency detector with a deadband has a frequency detector 20 generating a beat signal reflecting the difference in frequency between its input signals and an up/down signal that reflects the sign of the difference in frequency between its input signals. A frequency comparator 24 receives the beat signal and a deadband signal and disables the up/down signal when the beat signal is less than the deadband.

Description

2360409 FREQUENCY DETECTOR The invention is directed to a frequency

detector for data communication and telecommunication applications, for example to phased-locked loops used in these applications.

Phase locked loops (PLLs) are used in data communication and telecommunication applications to lock onto the frequency of a signal. The capture range of a PLL is typically narrow. Therefore, a frequency acquisition aid is usually needed in clock and data recovery (CDR) circuits. Walker, et al. in "A 1.5 Gigabit/s link interface chipset for computer data transmission", IEEE J. Selected Areas Communication, disclosed a technique using special training data sequences. The transmit side sends special training sequences (clock-like signals) during receiver frequency/phase acquisition stage. The disadvantage is that the training sequences are not always available for all applications. Another prior art method uses frequency detectors (FDs) that operate on the input data, and the 1 and Q output of the voltage-controlled oscillator (VCO). These FDs mostly can be categorized into two types: quadricorrelator and rotational frequency detector. The quadricorrelator may either be analog or digital while a rotational frequency detector is digital. An analog quadricorrelator requires many special analog components, including rectifier, differentiator, etc., as disclosed by Gardner in "Properties of Frequency Difference Detectors", IEEE Trans. Comm.. It is difficult to implement and when not carefully designed, may not function properly under all conditions. The digital implementations, such as that disclosed by Pottbacker, et al. "A Si Bipolar Phase and Frequency Detector IC for Clock Extraction up to 8 Gigabit/s", WEE Journal of Solid State Circuits or Messerschmitt, et al. in "Frequency Detectors for PLL Acquisition in Timing and Carrier Recovery", WEE Trans. Comm., have at most +1-50% usable frequency range, but are often narrower

2 depending on the implementation and the statistics of the input data. Due to process, temperature and WC variations, many integrated VC0s have an upper frequency range that is more than twice, and a lower end that is less than V2 of their nominal frequency. Therefore these digital implementations are not adequate in this respect. Furthennore, they are also susceptible to erroneous out-of-lock indications due to jitter on the input data or isolated bit errors.

Other prior art solutions use a local reference clock. The W0 is made to frequency lock to this reference. This method is robust because it does not rely on the input data stream. Two variations are common. In the first, an externally supplied lock-to-reference control signal causes the PLI, to lock to the reference clock exclusively. Having achieved frequency lock, the I'LL phase locks to the data when the control is deasserted. The disadvantage is that the users must provide an extra control signal, which is not always convenient. In the second variation, a lock detector provides an automatic lock-to-reference control. The lock detector asserts this control signal when it thinks the I'LL is out of lock. This lock detector operates on the input data and WO output, similar to the frequency detector methods. This lock detector therefore has similar problems, including narrow usable frequency range, susceptibility to erroneous out-of-lock indication due tojitter on the input data or isolated bit-error events.

The present invention seeks to provide an improved frequency detector.

3 According to an aspect of the present invention there is provided a frequency detector with a deadband comprising:

a frequency detector for receiving a first and second input signals and being operable to generate a beat signal reflecting the difference in frequency between the first and second input signals and a sign output signal that reflects the sign of the difference in frequency; a frequency comparator for receiving the beat signal and a deadband signal and being operable to generate an output signal that indicates when the beat signal is within a deadband tolerance; and a disabling means connected to the frequency detector and the frequency comparator for disabling the sign output signal when the beat frequency is less than the deadband.

4 The preferred embodiment can provide a simple yet robust solution to the PLL frequency acquisition problem in clock and data recovery (CDR) circuits, when a local frequency reference signal is available. The frequency detector has a narrow deadband around its nominal frequency. This deadband allows for possible mismatch between the data rate and the local reference frequencies, yet the width of this deadband is still narrower than the capture range of the phase lock loop. A crucial element used to construct such a frequency detector is an oversampling rotational frequency detector. Compared with a standard rotational frequency detector, the oversampling version provides a much wider usable frequency range to cover the wide variations of the typical integrated voltage controlled oscillators.

An embodiment of the present invention is described below, by way of example only, with reference to the accompanying drawings, in which:

Figure 1 illustrates an embodiment of phase-locked loop.

Figure 2 is a block diagram for the frequency detector with deadband shown in Figure 1.

Figures 3A-B illustrate the desired frequency characteristic for the ftequency detector with deadband shown in Figure 2.

Figures 4A-C illustrate a prior art rotational frequency detector.

Figure 5 illustrates a generalized oversampling rotational frequency detector.

Figures 6A-C illustrate a double-rate rotational frequency detector.

Figures 7A-C illustrate a quad-rate rotational frequency detector.

Figure 8 illustrates the debouncer circuit shown in Figure 2.

Figure 9 illustrates the ftequency comparator shown in Figure 2.

6 Figure 1 illustrates a block diagram of a preferred embodiment of phaselocked loop (PLL) 10. An adder 12 receives, as inputs, the outputs from a phase detector 14 and a frequency detector 16. The output of the adder 12 is connected to a loop filter 18. An input of a voltage controlled oscillator (VCO) 19 is connected to the loop filter 18 while the output is connected to the phase detector 14 and a divider 15. The divider 15 is further connected to the frequency detector 16. The phase detector 14 receives data as an input signal. The frequency detector 16 receives two clock signals f F and fd.db d.

RE Figure 2 illustrates a block diagram for the frequency detector with deadband 16 illustrated in Figure 1. A rotational frequency detector 20, generates an up/down output and beat output, is connected to an optional debouncer circuit 22. The beat output of the frequency detector 20 is connected to one input of a frequency comparator 24. The other input of the comparator 24 is connected to fd,,,,db.d. The up/down output of the frequency detector 20 is enabled/disabled by a tristate or similar device 25 under the control of the inband output of the frequency comparator 24.

Figures 3A-B illustrate the desired characteristics of the frequency detector with deadband 16 shown in Figure 2. The output is zero when the flequency difference is less thanfd,,.db.A (e.g..4% of nominal frequency). This deadband is needed because although the local reference clock is very close in frequency to the input data (e.g. within 100 PPM), it is often not frequency locked. This band must be narrower than the pull-in range of the PLL, yet wide enough to allow certain frequency difference between the data rate and local reference clock, and also j itter and wander at the data input.

The output of the frequency detector with deadband saturates rapidly when the frequency difference is larger thanfdedbd. The frequency detector drives the loop with full force when the voltage-controlled oscillator (VCO) is out of band. This ensures that the loop is driven back to within the deadband, even with possible offsets in the loop filter, and possible erroneous output from the phase detector.

7 The rotational frequency detector compares the output of the WO with the reference clock, and generates a beat tone at the difference frequency and a logic signal indicating whether the WO is too fast or too slow. The debouncer takes away the spurious transitions in the beat signal. The frequency comparator compares the beat tone with a known low frequency, which can be produced, for example, by dividing down the reference clock. When the beat tone is slower than this frequency, the output of the frequency comparator is a logic 1, which is used to disable (tristate) the up/down output. After the frequency detector is disabled, the phase detector operates alone to phase lock the WO to the input data.

Rotational frequency detectors are well suited for generating a beat tone and an up/down indication. In a prior art rotational frequency detector (shown in Figure 4A), a clock signalf, and its quadratureA are sampled by another signalfer which is nominally at the same frequency. When the two frequencies are exactly the same, the sampled values are static, that is the sampled vector stays at a particular quadrant A, B, C or D (shown in Figure 4B). When the two frequencies are slightly different, the vector rotates in one direction or another depending on the sign of the frequency difference, which in turn generates the up/down signal and beat tone. However, this device has a maximum usable frequency range of only + /- 50% (shown in Figure 4Q. It is usually not wide enough to cover the frequency variations of an integrated W0.

Figure 5 illustrates a generalized oversampling rotational frequency detector.

A phase sampler 26 samples the phase of the input signals. A phase correction generator 32 produces a correctional phase due to oversampling. A subtractor 28 corrects the ouput of the phase sampler 26. The output of the subtractor connects to a rotation direction/frequency detector block. The output of the block indicates the direction of rotation and the beat frequency.

In operation, the generalized oversampling rotational ftequency detector measures the frequency error of a signal, e.g. fc., by sampling it with a reference signal, i.e. f"F.

f_f +Aj(t) WO Nom 8 fREFkf,VOM (2) Since signal fvco is sampled at a rate of fRff, the phase rotation between consecutive samples is:

AO= 1 x2nx4CO= X2n(fNOM+AMD (3) fREF kfNom 2 ir + 2 nAf(t) (4) k kfNom This rotation consists of two terms: 27cAAt) is the desired term corresponding to the Af(t), kfNom the frequency error; and 27e/k is due to the oversampling condition. To correct the phase samples for oversampling by k, the oversampling phase error term 27r must be eliminated. k If k = 1, then there is no error. If k = 2 (double rate), then each sample n, where n is an integer has an error of nn, or alternating polarity inversion between samples. If k = 4 (quad rate), then the phase error of sample n is 7r n 2 Preferably, when the' phase sampler 26 measures binary-quantized 1, Q samples, k is limited to 1, 2 or 4. With a more general multi-phase sampler, k is arbitrary. In the general case, the phase correction of sample n is 9 27En k correction(n) (5) The I and Q samples are adjusted into corrected samples l' and Q' with the following formula for vector rotation:

I 1(n) =cos(Oc(n))In +sin(Oc(n))Q,, (6) Q '(n) = -sin(O,(n))I n +cos(O,(n))Q,, (7) When k = 2 or 4, the cosine and sine terms simplify to cos(nn) and sin(nn) or e(O, 1, -1), making for a very simple digital implementation.

Figures 6A-C illustrates a schematic diagram of a double-rate rotational frequency detector 20 that implements the functional block diagram shown in Figure 5. A first doubleedge-triggered alternating inverting latch (AIL) and a second AIL receive a reference signal fREF a clock input. The input signal to the first AIL is f, while the input signal to the second AIL is fQ. A D-flip-flop 46 is clocked by the output of the second AIL while it receives the output of the first AIL as an input. The output of the flip-flop 46 reflects the sign of the frequency offset. An XOR gate 48 is connected to the outputs of the first and the second AIL. 71e output of the XOR 48 indicates the beat frequency or the magnitude of frequency offset Af(t). It would be evident to one of ordinary skill in the art following the teachings herein that the generation of the beat signal may be accomplished in a different manner including simply selecting one of the AIL outputs as the beat signal.

Each AIL includes a first D latch 34, 42 and a second D-latch 36, 40. The clock input of the first D-latch 34, 42 is inverted. The inputs of the Dlatches 34, 36, 40, 42 are tied together. The inputs for a 2-input selector 38,44 are the negated output of the first D-latch 34, 42 and the output for the second D-latch 36, 40.

When the sampling frequency is twice the nominal rate, we have shown that the sampled vectors exhibit a spurious 1 SO' on alternate samples. These samples may be phase corrected by alternately inverting the sampled vectors. The sense and frequency of the rotation of this phase corrected vector reflects the direction and the frequency difference of the Af(t). This alternate inversion function is implemented as an integral part of the sampling AIL: this special double-edge-triggered latch sets its output Q to D at the rising edge of clock, s ets Q to D-bar at the falling edge.

The usable range of this double rate detector is doubled to +/- 100%, or from DC to twice the nominal frequency. The beat frequency output vs. frequency offset is plotted in Figure 6C.

If the double-rate sampling still does not provide enough covering range, an alternative embodiment, a quad-rate sampling scheme (shown in Figures 7A-C), can be used. Without phase correction, the sampled vector rotates counter-clockwise 90' per sample, when the frequency is in proximity to its nominal rate. Phase correction rotates the sampled vector clockwise by 0% 90% 180' and 270' successively, and repeats. In the truth table, shown in Figure 7A, the four states that correspond to the four different degrees of rotation are coded as 00, 0 1, 11 and 10. The function can be implemented with two selectors, i.e. two 4: 1 multiplexors, shown in Figure 7B. The phase-corrected vector provides the sense and magnitude of the frequency offset. The usable range is quadrupled to +/- 200%, or from DC to three times the nominal frequency. The beat frequency output vs. the frequency offset is shown in Figure 7C.

The debouncer circuit 22 is illustrated in Figure 8. Signal beatl is the input to a first latch 66 and the clock input to a second latch 68. Signal beatQ is the input to the second latch 68 and the clock input to the first latch 66. The outputs of the first and second latches 66, 68, beat I' and beat Q', are debounced signals. They may be optionally combined with an XOR gate 70.

The debouncer circuit 22 takes care of the situations when the phasecorrected vector is not or barely rotating, which happen when the PLL is, in-lock or very close to it. This vector may by chance lie near the border between two adjacent quadrants. Under this condition, spurious beat signals can be generated from j itter on the clocks, meta-stability of the flipflops, power supply noise and other noise sources. Because only one bit of the vector is chattering while the other bit is decidedly static, cross coupling the two bits of this vector to the D and Q input of two D-latches eliminates chattering.

Figure 9 illustrates the frequency comparator 24 shown in Figure 2. An edge-triggered SR latch 72 receives the deadband signal at the S-input and the beat signal at the R-input. The input of a D-flip-flop 74 is connected to the output of the S-R latch 72 and clocked by the beat signal. The output of the D-flip-flop 74 indicates that the beat signal is "in-band".

The frequency comparator 24 compares the beat frequency with that of a known (usually low) frequency fd.,,db,,,,d. If the beat frequency is lower, then the PLL is operating within the prescribed deadband. The main requirement of this frequency comparator 24 is that when the WO is inband, its output has to be static, free of any glitches whatsoever. This property can be easily verified by inspection: The in-band signal is clocked out by the beat signal. The beat signal also reset the S-R latch 72. If the beat signal is the one with lower frequency, then between two consecutive beat signal edges it is guaranteed to have at least one A,. dbl d edge, which sets the S-R flip-flop 38. Therefore the output is always one. When out-of-band, it is acceptable to produce glitches and this design indeed does. The average output vs. frequency difference curve has been plotted in Figure 3A. This output in conjunction with the up/down signal implements the desired overall frequency detector characteristics shown in Figure 3B.

The preferred embodiment provides an elegant design that uses standard digital cells. The design is robust because the frequency acquisition process is aided by a local reference clock. It is resistant to false lock, isolated bit-error events and jitter on the input data. This is a very important property for data communication applications, which are driven by cost and therefore usually do not have perfect signal qualities. Furthermore, this design has wide usable frequency range to cover the variations of an integrated W0. The frequency of the WO is not allowed to deviate from the deadband, no matter what signal is received at the data input, including no input, spurious input, or data at the wrong bit rate. This preferred design 12 keeps the WO approximately in frequency lock at all times, thereby greatly reducing phase acquisition time.

Parent British patent application no. 9812928.1 covers a k-fold oversampling rotational frequency detector for receiving at least one phase of an input clock signal having a frequency f,,0,,, + Af and a reference clock signal, comprising:

a phase sampler for receiving the input and reference clock signals, and operable to generate a first phase signal indicative of the phase of the input clock signal on at least one edge of the reference clock signal, having a phase sampling rate (kfO.); a phase correction generator for receiving the reference clock signal, and operable to generate a phase error signal, wherein the phase error for the nth sample is (n)=27rn/k, the phase error being due to the oversampling factor k>1; a phase subtractor for receiving the first phase signal and the phase error signal, and operable to produce a phase difference signal indicative of the phase difference between the first phase signal and the phase error signal; and a rotation direction/frequency detector for receiving the phase difference signal, and operable to produce a sign output signal indicative of the sign of the Af term of the input clock signal and a beat signal that toggles at a frequency proportional to Af. It may provide:

a first and a second latch each latch being operable to receive the inphase clock signal on its data input, the first latch being operable to receive an inverted reference signal at its clock input and the second latch being operable to receive the reference signal at its clock input; a third and a fourth latch, each latch being operable to receive the quadrature phase clock signal, the third latch being operable to receive an inverted reference signal at its clock input and the fourth latch being operable to receive the reference signal at its clock input; 13 a first selector including an inverted input operable to receive the output of the first latch and an input operable to receive the output of the second latch, a control input operable to receive the reference signal, an output; wherein when the control input is HIGH the output of the second latch is selected, when the control input is LOW the output of the first latch is selected; a second selector including an inverted input operable to receive the output of the third latch and an input operable to receive the output of the fourth latch, a control input operable to receive the reference signal, an output; wherein when the control input is HIGH the output of the fourth latch is selected, when the control input is LOW the output of the third latch is selected; a flip-flop connected to the outputs of the first and second selectors and operable to produce the sign output signal; and an exclusive-OR gate for receiving the outputs of the first and second selectors and operable to produce the beat signal.

Alternatively, the phase sampler may include:

a first latch including an output and being operable to receive the inphase clock signal and the reference clock signal, and a second latch including an output and being operable to receive the quadrature phase clock signal and the reference clock signal; the phase correction generator includes:

a third latch including an input and output and being operable to receive the reference signal at a clock input.

a fourth latch including an inverted output connected to the input of the third latch and an input connected to the output of the third latch and being operable to receive the reference clock signal at a clock input; 14 the phase subtractor includes two selectors operable to receive the outputs of the first and second latches, including control lines connected to the output of the third latch and the inverted output of the fourth latch, the two selectors in combination being operable to produce the phase difference signal; and the rotation direction detector includes:

a fifth latch for receiving the phase difference signal from the two selectors and being operable to generate the sign output signal, and an exclusive-OR gate for receiving the phase difference signal from the two selectors and being operable to generate the beat signal.

British patent application no. 9812928.1 also covers a frequency detector with a deadband including the rotational frequency detector specified above and a frequency comparator for receiving the beat signal and a signal at a deadband frequency corresponding to the width of the deadband; and disabling means connected to the rotational frequency detector and the frequency comparator for disabling the sign output signal when the beat frequency is less than the deadband.

Co-pending divisional British patent application No. 0 3 3Y /. t'(RJ/N10888) is directed to a debouncer circuit comprising:

a first flip-flop including an output and being operable to receive a first output signal at an input and a second input signal at a clock input; and a second flip-flop including an output and being operable to receive the second input signal at an input and the first input signal at a clock input; wherein the outputs of the first and second flip-flops produce debounced versions of the first and second input signals.

The above-described features may be aspects of the present invention.

The disclosures in United States patent application no. 081885,368, from which this application claims priority, in British patent application no. 9812928.1 of which this is a divisional patent application, and in the abstract accompanying this application are incorporated herein by reference.

Claims

16 CLAIMS

1. A frequency detector with a deadband comprising: a frequency detector for receiving a first and second input signals and being operable to generate a beat signal reflecting the difference in frequency between the first and second input signals and a sign output signal that reflects the sign of the difference in frequency; a frequency comparator for receiving the beat signal and a deadband signal and being operable to generate an output signal that indicates when the beat signal is within a deadband tolerance; and a disabling means connected to the frequency detector and the frequency comparator for disabling the sign output signal when the beat frequency is less than the deadband.

2. A frequency detector with deadband according to claim 1, comprising a debouncer circuit for receiving the beat signal and being operable to generate a stable beat signal.

3. A phase lock loop including the frequency detector according to claim 1 or 2, and a phase detector including a first input and being operable to receive a data signal on a second input; an adder for receiving from the phase and frequency detectors; a loop filter for receiving from the adder; a voltage controlled oscillator for receiving ftom the loop filter, connected to the first input; and a divider for receiving from the voltage controlled oscillator and for providing a signal to the frequency detector.

4. A frequency detector substantially as hereinbefore described with reference to and as illustrated in the accompanying drawings.

17

5. A phase locked loop substantially as hereinbefore described with reference to and as illustrated in the accompanying drawings.