GB2356502A - Diode free cross point array for magnetic random access memory - Google Patents

Abstract

A diode-free array for magnetic random access memories comprises two sets of lines, an array of magnetic memory cells 11,12,21,22 (either vertical stacks or horizontal stripes) at each intersection, and a peripheral circuitry. During a write operation write currents, supplied by a voltage source through load resistors, are used to write the selected cells and do not pass through any cell, otherwise they may damage the cells, because all the lines are brought to actual ground. During a read operation a sense current is directed through the selected cell and measured without causing alternative current paths by clamping all the bit lines to either actual or virtual ground with the aid of an operational amplifier. Such a simplified diode-free array overcomes the diode-area constraint in the prior art. Spin-valve elements or magnetic tunnel junction devices may be used for the magnetic memory cells.

Description

2356502 Diode-Free Cross-Point Array Architecture for Magnetic Random

Access Memories

TECM141CAL FEELD

This invention relates in general to a novel diode-free cross-point array architecture for magnetic random access memories (MRAMs), in particular those using magnetic tunnel junctions (MTJs) or spin-valve (SV) elements as the individual magnetic memory cells, for use as computer main storage and other memory applications.

0 BACKGROUND OF THE HWENTTON

Read-access time and storage density are the twin keys to computer main storage. Although new electronic devices, processor organizations and software systems have contributed to enormous advances in computer technology, they would have been worthless without the faster and denser memories that were developed with them. So-called serruconductor memories refer respectively to bipolar memories and MOS (Metal-OxideSemiconductor)based memories. Bipolar circuitry are of TTL (Transistor-Transistor Logic), ECL (Emitter Coupled Logic) or I2L (Integrated Injection Logic) types and the range of devices which may be produced is more limited than MOS since only Static RAMs (SRAMs) may be fabricated. In storage density, conventional semiconductor memory cells have current flow in the plane of the cell, i.e., "horizontaT', and therefore occupy a total surface area that is the sum of the essential memory cell area plus the area for the electrical contact regions, and therefore do not achieve the theoretical minimum cell area. SRAM cells have four or six transistors, but ROM (ReadOnly Memory) cells consist of only one single transistor. Although having a storage density close to that of the ROMs, the Dynamic RAMs (DRAMs) must be periodically recharged or refreshed, i.e. they are volatile or dependent on backup battery power, and require complex structures to incorporate a capacitor in each cell. Flash type Electrically Erasable Programmable Read Only Memory (EEPROM) cells are nonvolatile, have low sensing power, and can be constructed as a single device, but take microseconds to write and milliseconds to erase, which makes them too slow for many applications, especially for use in computer main memory. Complementary MOS (CMOS) is today's mainstream technology for both logic and memories. In general, bipolar memories are fast but of low capacity whereas MOS-based memories are somewhat slower, but of very large capacity.

Magnetic random access memories (MRAMs), unlike the above memories, that store information as the orientation of magnetization of a ferromagnetic region can hold stored information for long periods of time, and are thus nonvolatile. An MRAM is an array of individual magnetic memory cells. In the prior art cross- point array MI?,Ws, current rectification is desirable, as described in GB Pat. No.148635, May., 1985. In Fig.1, the basic array element is a semiconductor switch 15 (a diode or a transistor) connected in series with a binary data memory cell 13. Word line control circuitry 17 is attached to word lines 4, 5 and bit line control circuitry 19 is attached to bit lines 6, 7. With a onediode-per-cell architecture it is possible to flow current through a single chosen cell by forward-biasing the diode connected in series with that cell, blocking all alternative current paths by reverse-biasing the rest of the diodes. In the absence of such a diode all the cells at each intersection of every word line and bit line in the cross-point array would otherwise be electrically connected to one another and there would be currents spreading over the network.

A certain type of MRAM with magnetic tunnel junction(MTJ)-diode series is described in U.S. Pat. No.5,640,343, June, 1997. The diode in the memory cell functions as a unidirectional current valve. The write currents to change the magnetic state of the selected cell 13, for example, do not pass through the tunnel barrier layer by reverse biasing the diode 15 in the sense path by setting the voltage of the bit line 6 more positive than that of the word line 4. To read or sense the memory cell 13's magnetic state, for example, a sensing current is directed through the cell 13 by selectively establishing a forward bias voltage across the MTJ- diode series (13 and 15) by raising the voltage of the word line 4, and pulling down the voltage of the bit line 6.

However, such a memory-cell-diode series puts a severe constraint on the storage density, although a successful vertical integration of MTJs with hydrogenated amorphous silicon (a-Si:H) diodes was made by Sousa, et al. in "Vertical integration of a spin dependent tunnel junction with an amorphous Si diode for MRAM application", HA-03, INTERMAG'99, Kyongju, Korea, May 1999. This is because the scaling down of the integrated cell will mainly depend on the diode area required for the diode to achieve current flows higher than 10' A at a voltage lower than IV. It isn't currently possible to build a suitable diode with the required low leakage current without making the diode from very thick oxide layers which makes its resistance too high to be useful for high speed applications. One can obviously make very large diodes to reduce the resistance but this then makes the memory cells far too large to be technologically useful. The area of the diode must be at least 103 (gM)2 with 200 nm film in order to operate the integrated junction-diode cell at around 0.5-1 V. Note that 103 (jum)' of the area of the diode is much larger than 0.17 (/.,M)2 of the smallest magnetic tunnel element described by Parkin, et al. in "Exchangebiased magnetic tunnel junctions and application to nonvolatile magnetic random access memory", Journal of Applied Physics, V61.85, No.8, 1999. On the other hand, when the MTJ elements are in series with their respective diodes and organized into an array, there would be sensing power inefficiency due to the resistance of the diode in series with the MTJ element. This reduction would be by a ratio of the diode resistance D to the sum of MR and D, where MR is the MTJ resistance. When one memory cell is being sensed, the current flows through both the MTJ and the diode. This reduces the efficiency of the sensing process in two ways. First, sensing the value of the resistance of the selected cell is difficult due to the series resistance of the diode in the sense path. It is essential to limit the voltage over the MTJ to 100 mV. In case the total voltage over the MTJ-diode series is kept at 1 V, for a MTJ showing 10% change ratio, a relative voltage change of 0.6% can only be retrieved due to the large voltage drop over the diode. Second, sensing power is higher due to the power dissipated in both the MTJ and the diode in the sense path. Thus, the one-diode-per-bit architecture of the prior art is of comparatively poor performance and have several practical limitations that have prevented their commercialization, and no operable MRAM has been built.

SUNEYLARY OF THE INWNTION An object of this invention is to provide a diode-free architecture for magnetic random access memories (MRAMs). By this architecture the diode- area constraint wili be overcome and the significant breakthrough in density will be achieved compared to the prior art memory-cefl-diode series design.

Another object is to increase the sensing and power efficiencies by the elimination of the diode per bit. Sensing and power efficiency are needed for high-capacity MRAMs useful for computer main storage.

Another object is to simplify the fabrication process, as only two interconnecting levels are necessary to address a matrix of bits in this architecture. By contrast, in the prior art designs, there is a need for a diode per bit, that functions as a unidirectional current valve. This, together with the sense current contacts, creates the need for three interconnecting metal levels.

In accordance with this invention, a novel diode-free cross-point array architecture for magnetic random access memories comprises two sets of lines, an array of magnetic memory cells (either vertical stacks or horizontal stripes) at each intersection, and a peripheral circuitry.

For a fuller understanding of the nature and advantages of the present invention, reference 0 should be made to the following detailed description taken together with the accompanying figures.

rz BREEF DESCRIMON OF THE DRAWING Fig. I is a schematic diagram of an MRAM architecture by combining memory cells and unidirectional current valves, representative of the prior art;

Fig.2 is a schematic diagram of the diode-free cross-point array architecture of this invention; Fig.3 illustrates the diode-free MRAM with magnetic memory cells located vertically at each intersection of and in contact with every word and bit line in this invention; Fig.4 is an illustration of a write operation in a diode-free MRAM of this invention; Fig.5 is an illustration of a read operation in the diode- free MRAM of this invention; Fig.6 illustrates the voltage and current levels on the word and bit lines during MRAM read and write operations corresponding to Fig-4 and 5; Fig.7 is an illustration of an alternative read operation in the diode- free MRAM of this invention; Fig.8 is a cross-sectional view of the diode-free MRAM of this invention formed on a substrate and illustrating the fabrication process steps; Fig.9 is a SEM (Scanning Electron Microscope) micrographs of a 2x2 bit diode-free SDT-MRAM chiplet; Fig. 10 is readout waveform of the chiplet of Fig. 9 by using the peripheral circuitries described in this invention; Fig. 11 illustrates an alternative embodiment of an MRAM using the CIP type spin-valve elements; Fig. 12 illustrates another alternative embodiment of an MRAM using the CPP type spinvalve elements.

Similar numbers refer to similar elements throughout the drawing.

DESCRIMON OF THE PREFERRED EMBODBIENTS In an embodiment of this invention, a diode-free cross-point array architecture for magnetic random access memories is described with reference to Fig.2. The array includes a set of electrically conductive traces that function as parallel word lines 60, 62 in a horizontal plane, and a set of electrically conductive traces that function as parallel bit lines 64, 66 in another horizontal plane. The bit lines are oriented in a different direction, preferably at right angles to the word lines, so that the two sets of lines intersect when viewed from above. A memory cell 11, 12, 21 or 22 is located at each crossing point of the word lines and bit lines in the intersection region. Two word lines 60, 62 and two bit lines 64, 66 are illustrated in Fig.2, but the number of lines would typically be much larger in practice. The memory cell in the array are controlled by only these two kinds of lines, the minimum needed to locate a cell in a two-dimensional array, which serve as well as the column and row contacts to the memory cell. Word line control circuitry 27 is attached to the word lines 60, 62 and bit line control circuitry 29 is attached to the bit lines 64, 66. Write and read operations are performed by selectively activating the cells with the aid of the peripheral circuitry 27, 29.

The write and read operations will be demonstrated respectively. In the embodiment, a 2x2 bit diode-free MRAM using the MTJs will be exemplified as shown in Fig.3, although the principle of diode-free architecture is applied to any MRAM with cross-point memory cell array. Two word lines 60, 62 and two bit lines 64, 66 are used, but the number of lines would typically be much larger in practice. Arranging the MTJs 11, 12, 2 1, 22 vertically at the intersection regions of the two lines can achieve the theoretical minimum MRAM surface cell area. This results in a compact arrangement for the MRAM that allows a much denser array than conventional RAMs. The sense current flows vertically through the selected memory cell, in contact to the word line and the bit line. As indicated by Wang et al. in "Perpendicular GMR random access memory using magnetic tunneling effect", Journal of the Magnetics Society of Japan, Vol. 19, No.S2, p. 108-111, October, 1995 and "Spin tunneling random access memory (STram)", Intermag, EC- 11, Seattle, USA, April 1996; IEEE Trans. Magn., Vol.32, No.5, p.4022-4024, September,1996, the density- independent signal level is the biggest advantage of current- perpendicular (CPP) type MRAM using the MTJs, compared with the conventional current-in-plane (CIP) type magnetoresistive (MR) or spin- valve (SV) MRAM, whose signal level is inversely proportional to the square root of the storage density. In principle, it is possible to fabricate the dense MRAM using the MTJs without signal degradation. As shown in Fig.3 and will be illustrated in detail in Fig.4, the entire word on the word line 60, comprising the cell 11 and 12, is chosen to be written by the coincident currents. The sign of the bit current applied to the bit line 64 or 66 will define the stored bit value, "0" in the cell 11 and " 1 " in the cell 12 in this example. While not shown in Fig. 3, the array is formed on a substrate, such as a silicon substrate on which there would be other circuitry. Also, a layer of insulative material is located between the bit lines and word lines at regions of the MRAM other than the intersecting regions.

As shown in Fig.3, a MTJ 21 in the preferred embodiment comprises a magnetically-hard ferromagnetic layer (HFM) 90, such as Co, a thin tunneling barrier layer 88 of alumina (A1203), a magnetically -soft ferromagnetic layer (SFM) 86, such as permalloy (NiFe). The tunneling resistance between two ferromagnetic metal layers 86 and 90 that are depends on the relative orientation of the magnetization 92, 94 of each layer.

The SFM layer is fabricated to have a preferred axis for the direction of magnetization called the easy axis. There are two possible directions of magnetization of the SFM layer along this easy axis which defines the two states of the memory cell. In contrast, the HFM layer is fabricated to have only one preferred direction of magnetization, called its unidirectional anisotropy direction, and this direction is parallel to the easy axis of the SFM layer. In a memory device, independent switching of the magnetically soft layer SFM (86) is achieved by making the other layer 90 either magnetically hard or exchange-biased by an antiferromagnetic (AF) layer e.g., doped NiO, C,O or M,,F,, (not shown in Fig.3).

OPERATION OF THE MRAM The operation of the MRAM to read and write memory celi will be described with reference to Figs.4-7. Only the word lines and the bit lines are required to read and write the magnetic state of the memory cells. No other control lines from outside the array are necessary to read or write. This provides a very efficient memory array.

WRITE OPERATION When a sufficiently large current is passed through both a word line and a bit line of the MRAM, the self-field of the combined current at the intersection of the write and bit lines will rotate the magnetization of the SFM of the single particular MTJ located at the intersection of the energized word and bit lines. The current levels are designed so that the combined self-field exceeds the switching field of the SFM. This is predominantly determined by the coercivity and the magnetic anisotropy of the SFM. This self-field is designed to be much smaller than the field required to rotate the magnetization of the HIM.

In principle, addressing any desired cell in the two dimensional array can be realized by the orthogonal word lines and bit lines. That is to say, neither the word current with selected value nor the bit current with selected value by themselves are able to switch the layer at their intersection by its induced fringe field, but the two in combination will. This is often called the coincident-current scheme. However a practical difficulty is encountered, that the coincident current scheme in the prior art wili result in a serious current leakage through the MTJs with subsequent damage, because the word lines and bit lines are electrically connected to the MTJ at their intersections.

In the preferred embodiment of Fig.4, two selected cells 11, 12 are written by passing current shown by arrow 65, through the Ist word line 60 and currents Ib,,, shown by arrow 61, 63, through the lst and 2nd bit lines 64, 66. A write voltage V,,,,,,, (80) is applied, through a load resistor R,,,,, (68), to one end of the chosen word line 60, whose other end is brought to ground 84. So, a write current (65) is imposed along the dotted path shown in the figure. Note that this write current is determined by and independent of the tunnel resistance. Similarly the bit line write current is. produced along the chosen Ist bit line (64) and 2nd bit line (66). The magnetic field produced by either " or lb,,, alone in the region of the cells is less than the magnetic field required to change the magnetic state in a cell, so half-selected cells 21, 22 (those over which only Ib,, , alone is passing) are not written. However, the combination of magnetic fields from and lb,,, is sufficient to change the state of the selected memory cells 11, 12. At least one of the currents " or Ib,, has to be reversible to write the two different magnetic states of the cell. In this example, the bit lines 64, 66 are chosen to have bidirectional currents and the sign of the bit current Ib- will define the stored bit value, "0" or "I". The bit lines are connected to the bit line control circuitry 29, so only the bit line control circuitry 29 has to connect to an external data channel. The array shown in Fig.4 has the entire word, comprising the two selected cell 11, 12 on the selected lst word line, to be written at a given time by energizing that word line and all the bit lines. This is a parallel write operation with high data transfer rate between the computer and its main storage.

Although the linear load resistors R,,,, (68) and Rb,,, (70), which supply the write currents for the selected cells, are used in the embodiment of Fig.4, the resistor could be implemented as a field effect device circuitry or a bipolar transistor circuitry as is well known in circuitry design.

Referring now to the write/read voltage and current levels of Fig.6, the voltage level of the 1 st word lines 60 and the 1 st and 2nd bit lines 64, 66 during a write operation is brought to (actual) ground 84. The ground voltage level of the lines ensures that all the cells in contact with the word and bit lines have zero voltage drop and do not conduct. That is to say, the currents and Ib. do not flow vertically through any memory cell.

The above write operation is based on an assumption that the lead line resistance is negligible. If the lead line resistance is not small compared to that of the MTJ devices then the voltage distribution along the chosen line will appear. Such a voltage distribution will possibly cause leakage currents through the MTJs. Parkin et al. found that the resistancearea products of magnetic tunnel junctions can be varied from 109 Q-Mm to 60 Q-/.1ml by varying the Al thickness and properly oxidizing it(Parkin, et al. in "Exchange-biased magnetic tunnel junctions and application to nonvolatile magnetic random access memory", Journal of Applied Physics, V61.85, No.8, 1999). Because the tunnel resistance is typically several orders of magnitude larger than the lead resistance, the assumption that the lead resistance is negligible is acceptable.

In addition, because the soft layer SFM is asymmetrically located between the word line and the bit line, the bit current (Iwb = Vwb / Rwb) should be set larger than the word current to switch the SFM with equilibrium. Different currents are supplied by a common voltage source through the load resistors 68, 70 with different values. This reduces the number of voltage power supplies. In the standby state, both of the word lines and the bit lines are at OV, so the array is prepared to begin a write operation as described above or a read operation as will be described below.

READ OPERATION The MTJ element has two stable magnetic states, which correspond to the two parallel/andparallel magnetization orientations in the MTJ. These two stable magnetic states 0 cause two different values of resistance to current passing through the tunnel barrier of the MTJ. Due to the mutual connection between all the MTJ 11, 12, 21 and 22 in the 2 x 2 array shown in Fig.3, measuring the value of any individual resistance (to determine "0" or "I") becomes a very difficult task. It is because any direct measurement would result in unavoidably introducing the contribution from the rest of the MTJs. This difficulty has been overcome by introducing a concept of "virtual ground" in operational amplifier. The memory state of the memory cell is detected or read by applying a voltage across the selected MTJ and measuring the current through the NTFJ. Conversely it is that voltage that is being used to read the memory cell in the prior art.

Referring to Fig.5, the preferred technique for sensing the resistance of a selected memory cell in the MRAM will be explained. One operational ampLifier 122 is shared by the whole memory matrix as its input line goes to all cells on the matrix. Since the input impedance of an operational amplifier 122 is considered very high or even infinite, no current can flow into or out of the input terminals 133, 134 for most practical purposes. (Instead, an input current must flow through a feedback resistor 121 which is attached to the inverting input terminal 133 and the output terminal 124 of the operational amplifier 122.) Because no current can flow into or out of the inverting input terminal 133, this point is at OV, commonly referred to as virtual ground. As shown in Fig-5, in a read operation a voltage across the selected cell 22 under a read condition is established by setting the selected 2nd word line (62) to an input sine-wave voltage excitation Vi,,2 (132), which is about 100 mV. 'ne bit lines 66 is clamped to virtual ground OV by setting the (electronic) switch 181 to read mode to create the voltage across the selected cells 22. The bit lines 64 is clamped to actual ground OV by setting the switch 180 to standby mode. Tle un-selected 1st word line (60) remain at the standby voltage level, OV. 'Mus the un-selected cells 11, 12 have zero voltage drop from word line to bit line and do not conduct. The un-selected cell 21 conducts but does not contribute to the read output. In other words, selection of a given cell for reading is accomplished by addressing one of the word lines and one of the bit lines with the aid of the switches 180,18 1. The sneak paths through other MTJ elements are avoided by virtually grounding the chosen bit line and (actually) grounding the other bit lines, and grounding all the word lines except the chosen word line.

The switches, used to switch the bit line between the standby mode and the read mode in the embodiment of Fig.5, could be a very simple field effect device circuitry or a bipolar transistor circuitry, which occupies a very small silicon area, as is well known in circuitry design.

The resistance of the selected memory cell 22 determines the sense current 1, (131) that flows from the 2nd word line (62) through the selected memory cell 22 to the 2nd bit line 66. In the bit line control circuitry 29 this current is converted to a voltage to read the datum stored in selected cell 22. The operational amplifier 122 has its noninverting input terminal 134 brought to ground 84. Since the input impedance of the operational amplifier 122 is considered very high or even infinite, no current can flow into or out of the inverting input terminal 133. This forces a sense current 1, (131) to flow through the feedback resistor Rf (121). Sense current 1., (131) Produces a sense voltage V,,.t at the output terminal 124. The low resistance state and high resistance state of NIR,-j, at the intersection of the i'th word line and the j'th bit line, produce different values of sense current 1, (13 1) in inverse proportion and therefore different values of output voltage V,,,t, as labeled in Fig.5. Referring again to Fig,.6, the output voltage V,,,ut has two discrete values corresponding to the two magnetic states of the. MTJ cell, which correspond to a datum I or 0. While not shown in Fig.5, the output voltage V,,ut will be compared to a reference voltage level set to a value halfway between the expected values for the two possible states of the memory cell and the difference will be amplified further to provide full logic levels, by use of well known circuit techniques. After the data is read, the voltage on 2nd word line is returned to the standby value. The magnetic state of memory cell remains unchanged after the read operation.

The output voltage V,,utj for the j'th bit line can be proven by the formula Vouti Rf Vi,i MR,j where "2' indicates an inverting amplifier, Rf is the feedback resistor 121, NIP,-j is the resistance of the NM 11, 12, 21 or 22, needed to be monitored at a given time, at the intersection of the i'th word line and the j'th bit line, and Vi,,i is the input voltage excitation applied to the i'th word line.

Similar to the write operation, the above read operation is based on an assumption that the lead line resistance is negligible. If the read line resistance is not small compared to that of the MTJ devices then the voltage across each MTJ cell along the chosen word line will vary and will depend on the state (i.e. resistance) of these MTJ cells. Tbus it is no longer possible to infer the resistance of the individual MTJ devices along the chosen word line. Parkin et al. found that the resistance-area products of magnetic tunnel junctions can be varied from 109 11-prn' to 60 n-pm? by varying the Al thickness and properly oxidizing it(Parldn, et al. in "Exchange-biased magnetic tunnel junctions and application to nonvolatile magnetic random access memory", Journal of Applied Physics, V01.85, No.8, 1999). Because the tunnel resistance is typically several orders of magnitude larger than the lead resistance, the assumption that the lead resistance is negligible is acceptable.

Me voltage clamping scheme described above provides several benefits. The applied voltage across the MTJ element is clamped to the order of 100 mV, which is near the voltage level at which the magnetoresistance for the MTJ is at its maximum value. It reduces the time to establish voltages on the conducting lines attached to the MTJ element because required voltage excursions are reduced. Ile sensing scheme also provides read signal gain approximately equal to the ratio between the feedback resistance'Rf (121) attached to the operational amplifier 122 and the MTJ resistance NIRj during reading.

Alternatively, referring now to Fig.7, multiple operational amplifiers are used to execute a parallel read operation. A voltage across the selected cell 21 or 22 under a read condition is established by setting the selected 2nd word line (62) to an input sine-wave voltage excitation Vi,2 (132), which is about 100 mV. All the bit lines 64, 66 are clamped to virtual ground OV, with the aid of operational amplifiers, to create the voltage across the selected cells 21, 22. The un-selected Ist word line (60) remain at the standby voltage level, OV. Although there are a large number of possible current paths in the cross-point organization, no ambient current path, except the dotted paths 1, (13 1) through the chosen bit 21 and 22, exists any longer because all the bit lines 64 and 66 are set to virtual ground. Thus the un-selected cells 11, 12 have zero voltage drop from word line to bit line and do not conduct.

In Fig.7, the resistance of the selected memory cell 21, 22 determines the sense current I, (13 1) that flows from the 2nd word line (62) through the selected memory cell 21 or 22 to the I st and 2nd bit lines 64, 66. In the bit line control circuitry 29 this current is converted to a voltage to read the datum stored in selected cell 21 or 22. Note that all the bits (bit 21 and bit 22) on the chosen 2nd word line (62), i.e. the entire word, give their readout collectively and simultaneously. This parallel read operation ensures a high data transfer rate between the computer and its main storage. However, the approach, shown in Fig.7, with a high data transfer rate has

a big penalty in memory size. Because it requires that all the MTJ elements along the chosen word line be read simultaneously, this would mean building a large number (N) of sense amplifiers per N x N memory array. Since a sense amplifier is likely to be very large (occupying the space of several hundred memory cells for reasonable performance) this would mean that the support peripheral circuits would take up a very large amount of silicon area compared to the memory cells themselves. This makes this approach, shown in Fig.7, somewhat un-practical for any application of the memory. In most cases, one should use the sharedamplifier scheme(Fig.5) rather than the an-amplifier-per-bit-line scheme(Fig.7).

PREFERRED STRUCTURE The preferred material structure and fabrication process of the MRAM using the MTJs are described with reference to the cross-sectional view of Fig. 8. On a substrate 40, bit lines 64 and 66 are formed. Next, the series of layers which make up the MTJ are deposited by sputter deposition uniformly on this surface. In order, a 10- 100 nm thick Co HFM layer 90, a 0.8-8 nin thick A1203layer 88, and a 10-100 nrn thick NiFe SFM layer 86 are deposited. Al is formed on top of HFM layer 90, by oxidation, to form the insulating tunnel barrier layer 88 of A1203. Uniaxial magneto-crystalline anisotropy in ferTomagnetic films 86 and 90, important both for data storage and for the way that a bit is selected, is induced by a magnetic field of several kA/m applied during sputtering. At this point, there is a single large MTJ that covers the entire surface of the substrate 40. This large MTJ is then patterned into many small MTJs by photoresist masking and Ar ion milling down through the stack of layers to the surface of the bit lines 64, 66. The individual MTJs are then covered with a thick layer 50 Of Si02. Contact windows are opened in insulator 50 to the top of the MTJs. Word lines are then formed on top of the structure. The word lines contact the layer SFM of the MTJs.

EXPERRVIENTAL ASSESSMENTS To realize the first demonstration of diode-free SDT-MRAM, reported to date, a 2x2 bit memory chiplet was fabricated. Fig.9 is its SEM (Scanning Electron Microscope) picture. The chiplet has 8 contact pads which provides the required flexibility in connecting the test site to the described peripheral circuitry. The MTJ dimensions varied between 2 and 50 Am. The sandwich MTJ Co(100 nm)/A1203(3-8nrn)/80NiFe(l00 nm) was prepared by sputtering with argon. The intermediate A1203was; formed by oxidation in the atmosphere. Contact windows were opened in the insulator in order for the top leads and bottom leads to directly access the junctions without any diode (transistor) selective component. The isolated MTJ element was tested yielding magnetoresistance change values of around 6% and low switching fields of 160 kA/rn for NiFe and 320 kA/rn for Co. The resistance-area product is around 10' Q_(AM)2.

The MTJs are designed with a circular or elliptic shape to benefit the formation of singledomain structure. For each MRAM element there should exist only two possible states of magnetization, e.g. left and right. This is the case for an elliptic or circular island. For a single domain island one can be sure that the island switches completely in a proper writing process. A multi-domain state found in the square patterned island would lead to a miscellaneous logic in a one-bit-per-island recording system. This is because more than two states are possible and after writing the island might not have switched completely. As a consequence, the magnetization of the island becomes unstable and the result of a next writing process may be unpredictable, as indicated by L. He, RZ.Wang et al., in "Size and shape effects of patterned polycrystalline islands", IEEE Trans. on Magnetics, 35(5), 3508(1999).

The operations to read and write memory cells have been successfully carried out by using the peripheral circuitries described in this invention. - As shown in Fig. 10, the output voltage V,,,tj has two discrete values (the voltage difference is 56 mV) corresponding to the two magnetic states of the MTJ 21, 22. While not shown in Fig. 10, the output voltage V,,.tj will be compared to a reference voltage level set to a value halfway between the expected values for the two possible states of the memory cell and the difference will be amplified further to provide full logic levels.

ALTERNATIVE EMBODEVIENTS Although the illustratin described above is based on a particular type of MRAM using the MTJs, this diode-free architecture is applied to any MRAM with cross-point memory cell array. Fig. 11 is an alternative embodiment of MRAM using the spin-valve (S V) elements as the individual memory cells. In the SV sandwich there are two kinds of ferromagnetic layers SFM (86) and HFM (90) spaced by an intermediate non-magnetic metallic layer 88', e.g., Cu. The SV memory cell operates on the general principle of storing a binary datum in the magnetically-soft layer SFM and independent switching of the niagnetically-soft layer is achieved by making the other layer either magnetically-hard or exchange-biased by an antiferromagnetic layer (not shown in Fig. 11). Each memory bit is made of a SV stripe. Since the stripe must be accessed electrically for reading purposes, a thin metallic via 101 is used. One end of the SV stripe would likely be connected by the via 101 in a higher level to the word line overlapping the stripe array while another end is in contact with the bit line. The read current flows along the word line, through the via 101 and then the SV stripe in a direction parallel to the substrate and out through the bit line. Such a current-in-plane (CEP) configuration ensures a large enough resistance since the thickness of the SV stripe is much ' smaHer than its width and length. However, this MRAM has current flow in the plane of the cell with the limitation of State-of-the-art silicon VLSI processes, and therefore occupies a total surface area that is the sum of the essential memory cell area plus the area for the electrical contact regions, and therefore do not achieve the theoretical minimum cell area. 'Me operation of the MRAM using the SV elements remains the same as described in the preferred embodiment of the MRAM using the MTJs, both write and read operations are performed using the word and bit lines. Ddring a write operation the ground voltage level of the lines ensures that all the cells have zero voltage drop and do not conduct. During a read operation the sense current is assumed to flow mainly along the intermediate layer 88' (e.g., Cu) of the SV sandwich due to its large conductivity. The 'T' and "0" states are distinguished by the parallel and antiparallel states between the magnetizations 92, 94 of the two ferromagnetic: layers 86, 90. A sense current is directed through the selected cell and measured without causing alternative cur-rent paths by clamping all the bit lines 64, 66 to either actual ground or virtual ground with the aid of an operational amplifier. Note that two word lines 60, 62 and two bit lines 64, 66 are illustrated in Fig. 11, but the number of lines would typically be much larger in practice.

Fig. 12 is another alternative embodiment of MRAM using the spin-valve (SV) elements as the individual memory cells. The layer 88' is an intermediate non-magnetic metallic layer, e.g., Cu. A memory cell 11, 12, 21 or 22 is located at each crossing point of the word lines 60, 62 and bit lines 64, 66 in the intersection region vertically spaced between the lines. Two word lines and two bit lines are illustrated in Fig.12, but the number of lines would typically be much larger in practice. The operation of the MRAM using the SV elements remains the same as described in the preferred embodiment of the MRAM using the MTJs. The memory cell in the array are controlled by only these two lines, which serve as well as the column and row contacts to this SV memory cell. During a write operation all the cells have zero voltage drop and do not conduct due to the ground voltage level of the lines. The cell contents are read by flowing sense currents through the SV stacks in a direction perpendicular to the substrate. A sense current is directed and measured without causing alternative current paths by clamping all the bit lines 64, 66 to either actual or virtual ground with the aid of an operational amplifier. Fig. 12 is a currentperpendicular-to-plane (CPP) configuration. From a fundamental point of view, the CIP configuration suffers from several drawbacks. First, the CEP magnetoresistance is diminished by shunting and channeling. Moreover, diffusive surface scattering reduces the MR for sandwiches and thin multilayers. Finally, the relative contributions of interface and bulk spin-dependent scatterings are difficult to obtain using the CIP geometry. Measuring the perpendicular resistance solves most of these problems, mainly because the electrons cross all magnetic layers, thereby yielding an enhanced giant magnetoresistance effect, which is typically an order of magnitude large for the CPP case than for the CIP case. However, this measurement is not straightforward at alL basically because the perpendicular resistance of an ultrathin multilayers typically is much smaller than the resistance of the contact leads. Reliable perpendicular resistance measurements of state-of-the-art can only be done at low temperature using superconducting word and bit lines..

In the preferred embodiments of this invention, the memory cell operates on the general principle of storing a binary datum in the magneticallysoft layer and independent switching of the magnetically-soft layer is achieved by making the other layer either magnetically-hard or exchangebiased by an antiferromagnetic layer. This memory mode has the advantage that a decreased switching current is required thereby decreasing power dissipation in the device application. Another embodiment of memory operation mode of storing a binary datum in the magnetically-hard layer is possible as well in a sandwichstructured memory cell with two kinds of ferromagnetic, layers which possess different coercivities. This memory mode has the advantage of a stability against field excursions.

There are variations and modifications of the embodiments described above that can also be implemented in- the present invention. 'Mere is a good process compatibility to combine the write and read circuits into onebody integration although there are differences to some extent between the write and read circuits (switch between them for read/write is necessary at this stage) in the embodiment. The sine-wave input voltage excitation during a read operatiorL can be replaced with a square-w ave or other forms of input voltage excitations. Tle polarity of applied voltage can be reversed, but the operation of the MRAM otherwise remains the same as described in the embodiment shown in Figs.4-12. The word lines and bit lines can be packed close to one another in the array structure by constraining the magnetic fields with. the use of the magnetically-soft or the superconducting films, thereby increasing the amount of information that can be stored in a unit area of the array. Also, the word lines can be located below the memory cells and connected to the memory cells, while the bit lines are located above the memory cells and connected to the cells. With such changes, the operation of the MRAM is the same as described with reference to Figs.4-12.

13 In the embodiments, an array of four memory cells is shown for example, although typically many more cells would be constructed by duplicating the column unit to increase in one direction, and duplicating the row unit to increase in the other direction. In the embodiment, the simplest case of the sandwich structure for the spin-valve (SV) element or magnetic tunnel junction (MTJ) has been used to simplify the embodiments in this invention. It should be apparent that modifications and improvements of the preferred embodiments, e.g., adding extra layers in the SV or MTJ sandwich for an enhancement of the magnetoresistance change ratio or other properties, or replacing the SV or MTJ sandwich with giant magnetoresistive (GMR) multilayers typicaliy constructed by duplicating the basic unit to increase in the thickness direction, or forming some layers of the memory cells as parts of the continuous lines to increase the shape anisotropy, may be made to the invention without departing from the spirit and scope of the invention as described in the following claims.

/4 References cited

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Claims (15)

CLAIMS What I claim as my invention are:

1. A diode-free cross-point array architecture for magnetic random access memories comprising: a substrate; a first group of electrically conductive lines formed on the substrate; a second group of electrically conductive lines formed on the substrate and overlapping the first group of lines at a plurality of intersection regions; a arTay of magnetic memory cells formed on the substrate; a peripheral circuitry coupled to two groups of the lines.

2. The architecture according to claim 1, in which each of the said magnetic memory cells is a vertical stack of layers with the bottom layer in contact with one of the said first group of lines and the top layer in contact with one of the said second group of lines, whereby during a read operation a sense current flows through the said magnetic memory cell in a direction perpendicular to the said substrate.

3. The architecture according to claim 1, in which each of the said magnetic memory cells is a horizontal stripe with one end in contact with one of the said first group of lines and another end in contact with one of the said second group of lines, whereby during a read operation a sense current flows through the said magnetic memory cell in a direction parallel to the said substrate.

4. Each of the magnetic memory cells according to claim I being a magnetic tunnel junction comprising in order:

a magnetically-hard ferromagnetic layer whose magnetization is prevented to rotate in the presence of an applied magnetic field caused by electrical current flowing through the said lines at the intersection region due to its relatively large coercivity; an insulating tunneling layer, a magnetically-soft ferromagnetic layer whose magnetization is free to. rotate in the presence of an applied magnetic field caused by electrical currents flowing simultaneously through both of the said lines at the intersection region.

5. Each of the magnetic memory cells according to claim I being a magnetic tunnel junction comprising in order:

a pinned ferromagnetic layer and an antiferromagnetic layer adjacent to and in contact with the pinned ferromagnetic layer for pinning the magnetization of the pinned ferromagnetic layer in a preferred direction; an insulating tunneling layer; a free ferromagnetic layer whose magnetization is free to rotate.

6. Each of the magnetic memory cells according to claim 1 being a spinvalve element comprising in order:

a magnetically-hard ferromagnetic layer; an intermediate non-magnetic metallic layer; a magnetically- soft ferromagnetic layer.

7. Each of the magnetic memory cells according to claim I being a spinvalve element comprising in order:

a pinned ferromagnetic layer and an antiferromagnetic layer; an intermediate non-magnetic metallic layer; a free ferromagnetic layer.

8 The architecture according to claim I further comprising a layer of insulative material located between the said first group of lines and the said second group of lines at regions other than the intersection regions for spacing apart the first and second groups of lines, whereby each of the groups of lines is formed in a separate plane on the said substrate.

9. The peripheral circuitry according to claim 1, whereby during a write operation write currents are supplied by a voltage source through load resistors and passing through the two groups of lines at an intersection recrions to generate magnetic fields acting on the 0 selected multiple magnetic memory cells on one selected line of the second group at the intersecting regions.

10. The peripheral circuitry according to claim 1, whereby during the said write operation the said first group of lines and the said second group of lines are brought to actual ground and all the said magnetic memory cells have zero voltage drop, so that no electric current passes through the said magnetic memory cells when write currents are passing through the lines at the intersection regions.

11. 'Me peripheral circuitry according to claim 1, whereby during a read operation a sense current is directed through the selected magnetic memory cell and measured when the predetermined voltage is applied across the said selected magnetic memory cell.

12. The peripheral circuitry according to claim 1, whereby during the said read operation the electrical potential of all the said first group of lines is clamped to either virtual ground by an operational amplifier or actual ground through a switch to block all alternative electric current paths.

13. The operational amplifier according to claim 12 having its inverting input terminal attached to the said first group of lines, its noninverting input terminal brought to ground and, and a feedback resistor attached to its inverting input terminal and output terminal.

14. The operational amplifier according to any preceding claim converting the said sense current through the selected magnetic memory cell to voltages during the said read operation, which are then compared to a reference voltage level set to a value halfway between the expected values for the two possible states of the magnetic memory cell to provide full logic levels.

15. A diode-free cross-point array architecture for magnetic random access memories comprising: a substrate; a first group of parallel electrically conductive lines formed on the said substrate; a second group of parallel electrically conductive lines formed on the said substrate generally perpendicular to the said first group of lines and overlapping the said first group of lines, the said second group of lines being spac ed from the said first group of lines in a direction generally perpendicular to the substrate surface to define a arra of intersection y regions; a array of magnetic memory cells, each magnetic memory cell being'a vertical stack of C, layers with the top and bottom layers in contact with the lines or a horizontal stripe with its two ends in contact with the lines, each of the said magnetic memory cells comprising first and second ferromagnetic layers separated by an insulating tunnel barrier or a non-magnetic metallic layer, one of the ferromagnetic layers having a magnetization direction that is generally fixed in a plane parallel to the substrate surface and the other of the ferromagnetic: layers having a magnetization direction capable of orientation parallel or antiparallel to the magnetization direction of the said first ferromagnetic: layer; a peripheral electrical circuitry coupled to the two groups of lines, during a write operation, for passing write electric currents, supplied by a voltage source through load resistors, through the lines to generate magnetic fields in the vicinity of the ferromagnetic: layers in the selected magnetic memory cells to reorient the magnetizations of the ferromagnetic layers, wherein no electric current passes through the magnetic memory cells because the two groups of lines are brought to actual ground and all the magnetic memory cells have zero voltage drop, and, during a read operation, for converting a sense current through the selected magnetic memory cell to voltage by an operational amplffier to provide full logic levels for the two possible states, wherein the electrical potential of all the said first group of lines is clamped to either virtual ground by the said operational amplifier or actual ground to block all alternative electric current paths.

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