GB2350954A

GB2350954A - Self-diagnosis method for use in a digital broadcasting receiver to indicate which components of the receiver are defective

Info

Publication number: GB2350954A
Application number: GB0012970A
Authority: GB
Inventors: Shuichi Ninomiya
Original assignee: Matsushita Electric Industrial Co Ltd
Current assignee: Panasonic Holdings Corp
Priority date: 1999-06-02
Filing date: 2000-05-26
Publication date: 2000-12-13
Anticipated expiration: 2020-05-26
Also published as: CN1276652A; JP2000349842A; GB0012970D0; GB2350954B

Abstract

In a normal operation mode, a receiver Rx performs predetermined processing on a digital broadcasting signal from an artificial satellite to generate sound. The receiver Rx also executes a self-diagnostic mode as required. In the self-diagnostic mode, a controller 19 runs a diagnostic check as to whether an operating keypad 17 operates correctly. Further, the controller 19 runs a diagnostic check on the level of the receive sensitivity of the receiver Rx using either a received digital signal S<SB>DB</SB> or a simulated broadcasting signal S<SB>SIM</SB>. Through the use of an idle time in the above two diagnostic checks, the controller 19 checks whether each generated drive voltage is within each appropriate range; whether synchronization can be established in a PLL circuit 20 required for generating an intermediate-frequency signal S<SB>IF</SB>; whether synchronization can be established in a QPSK demodulator 21 required for QPSK-demodulating the intermediate-frequency signal S<SB>IF</SB>; whether the head of a reproduced master frame b can be detected correctly; and whether the head of a reproduced audio data frame a can be detected correctly. The receiver Rx thus can reliably and quickly carry out a diagnostic check as to whether each of components comprising thereof is defective or not.

Description

2350954 SELF-DIAGNOSIS METHOD IN SATELLITE BROADCASTING RECEIVER The

present invention relates to self-diagnosis methods that are executed as required by a receiver for receiving digital broadcasting signal from an artificial satellite and generating sound to check whether the receiver has a defect or not.

In recent years, various projects for digital broadcasting services through artificial satellites have been going forward. Among such projects, WorldSpace covers Africa, Asia, and South and Central America as service areas. In WorldSpace, audio programs are distributed to these service areasthrough a stationary satellite above the equator. Signal processing at the broadcasting side in WorldSpace is now described.

(1) Generation of audio data frame a First, n channels of digital audio data is generated in the broadcasting side. Here, in WorldSpace, n is a natural number equal to or less than 96. Each audio data is digitally compressed according to MPEG1 Audio Layer 3 standards (hereinafter referred to as MP3). Each compressed audio data is encoded, as shown in FIG. 18, so as to form a frame that repeatedly appears every 1 predetermined time period T,, thereby generating audio data frames a for n channels. Each audio data frame a includes CH sync information (channel sync information), SCH (Service Control Header), and audio data. Audio data of each channel is provided with SCH that indicates auxiliary information about the contents of the audio data that follows SCH. The CH sync information is added at the head of each audio data frame a, that is, just before SCH. The CH sync information is a starting code of each audio data frame, and is constructed in a predetermined bit pattern. Audio data represents audio corresponding to each channel. (2) Encoding for error correction Next, Reed-Solomon encoding and Viterbi encoding are carried out for error correction of each audio data frame a generated in the above process (1).

(3) Time-division multiplexing and generation of master frame 8 Next, each audio data frame a encoded in the above process (2) is subject to time-division multiplexing. Then, the auxiliary information is added to each multiplexed audio data frame a thereby generating a master frame is generated. More specifically, each audio data frame a is divided into blocks, as shown in (a) of-FIG. 19 by dotted lines. Then, data blocks represented by dotted areas in (a) of FIG. 19 are selected, for example. That is, one data block is selected from the audio data f rame a of each channel. Then, as shown in (b) of FIG - 19, the 2 master f rame is generated based on the selected data blocks. In (b) of FIG. 19, the master frame includes the selected n data blocks, frame sync information, and FCH (Frame Control Header). The selected n data blocks are arranged on a time axis. 5 FCH indicates auxiliary information such as information for specifying the data block. The frame sync information is added at the head of each master frame, that is, just before FCH. The frame sync information indicates a starting part of the master frame 0.

A plurality of above- structured master frames are generated with each different combination of data blocks. For example, the master frame 0 positioned at far left in (b) of FIG. 19 includes a combination of the data blocks represented by the dotted areas in (a) of FIG. 19. The master frame positioned 15 at second left in (b) of FIG. 19 includes a combination of the data blocks represented by hatched areas in (a) of FIG. 19. Moreover, the master frame 3 is generated so as to repeatedly appear every predetermined period T2' (4) QPSK (Quadrature Phase Shift Keying) and transmission 20 Next, digital modulation is performed to each master frame generated in the above process (3). More specifically, two carriers with their components 90 degrees apart in phases are modulated with each master frame 3. The signal resulted from this modulation is sent out from the stationary satellite to the 25 service areas as a digital broadcasting signal S,, of an L band 3 (1.5 GHz band).

Reversing the above procedure at the broadcasting side, receivers for WorldSpace process the above digital broadcasting signal SDB to reproduce required audio data. The receivers, 5 however, have to ensure a high level of quality when being shipped. Therefore, manufacturers make quality inspection (inspection of operating conditions) immediately before shipment. It is desirable that this quality inspection be carried out quickly and accurately.

Moreover, receivers may become out of order under operation.

In this case, a user brings a failed receiver to a local service center or the like. The service center inspects the operating conditions of the failed receiver to find out a failed part of the receiver. It is also desirable that this inspection be carried out quickly and accurately.

Furthermore, various inspection devices are used for the above inspection. Among such devices is a signal generator that is connected to the receiver f or inspection and generates a simulation signal S,,, simulating the above digital broadcasting signal S,,,, - Referring to a response of the receiver provided with the simulation signal Ss,,, the inspector of the manufacturer or service center tries to find out a def ective part of the receiver. However, such inspection devices, especially signal generators, are very expensive, and some service centers may be unwilling to keep such devices with a view to cutting investment in equipment 4 Therefore, receivers capable of checking their operating conditions without requiring the signal generator are desired.

Therefore, an object of the present invention is to provide a receiver capable of reliably and quickly carrying out a diagnostic check whether each of components comprising thereof is defective or not. Another object of the present invention is to provide a receiver capable of carrying out a diagnostic check whether each of components comprising thereof is defective or not without much spending on equipment.

The present invention has the following features to achieve the objects above.

A first aspect of the present invention is directed to a self -diagnostic method that is executed as required by a receiver for receiving digital broadcasting signal from an artificial satellite and generating sound to check whether the receiver has a defect or not, the digital broadcasting signal being generated by time -division -multiplexing audio data frames generated based on audio data for a predetermined number of channels, constructing a master frame based on the multiplexed audio data frames, and then QPSK modulating a carrier with the constructed master f rame, the method comprising the steps of:

checking whether each drive voltage f or driving the receiver is within a predetermined range and notifying an inspector of a check result; checking whether synchronization can be established In a PLL circuit required f or down- conversion by mixing an input signal to the receiver and a local oscillation output to generate an intermediate - frequency signal, and notifying the inspector of a check result; checking whether synchronization can be established in a QPSK demodulator required for QPSK-demodulating the intermediate-frequency signal generated through the down- conversion and reproducing the master frame, and notifying the inspector of a check result; checking, in frame synchronization processing for detecting a head of the master frame reproduced through the QPSK demodulation, whether the head is correctly detected, and notifying the inspector of a check result; checking, in channel synchronization processing for detecting a head of the audio data frame reproduced based on the master frame with the head thereof detected through the frame synchronization processing, whether the head of the audio data frame is correctly detected, and notifying the inspector of a check result; checking whether an operating keypad as a user interface operates correctly; and 25 detecting a plurality of C/N ratios (Carrier to Noise 6 Ratios) of the intermediate-f requency signal inputted to the QPSK demodulator, calculating an average value of the detected CIN ratios, and checking on a level of receive sensitivity of the receiver based on the average value, wherein the drive voltage checking step, the PLL circuit checking step, the QPSK demodulator checking step, the frame synchronization checking step, and the channel synchronization checking step are carried out during an idle time in the operating keypad checking step and the receive sensitivity checking step.

In the first aspect, the receiver carries out seven diagnostic steps to run a self-check for a defective part. In a diagnostic step for the operating keypad, human key operation is required, and therefore the receiver has to wait for key operation even though being capable of high-speed operation. In a receive sensitivity diagnostic step, for the purpose of accurate determination of the level of receive sensitivity that varies with time, it is required to place an interval between measurements of the C/N ratio. Therefore, assuming that only the diagnostic step for the operating keypad and the receive sensitivity diagnostic step are carried out, the controller 19 tends to be in a stand- by state, and a time period during which the receiver is not operating (that is, idle time) occurs. Therefore, according to the first aspect, by using this idle time, the other steps are carried out. The receiver can thus perform more diagnostic processing through the effective use of time, enabling 7 quick checks as to whether each component of the receiver is defective or not.

Furthermore, the receiver automatically checks whether the each component thereof is defective or not in each diagnostic step, and notifies of the inspector of the diagnostic result. The inspector thus can reliably detect a defective part of the receiver.

According to a second aspect, in the first aspect, the receiver is so designed that a signal generator for generating a simulation signal simulating the digital broadcasting signal can be connected thereto, and in the PLL circuit checking step, the simulation signal generated by the signal generator is used as the input signal to the receiver.

As known, the signal generator is often used for running a strict inspection. In the second aspect, the receiver checks whether each of the components in the receiver is defective based on the simulation signal generated by the signal generator. Therefore, the receiver can carry out the check automatically and more reliably.

According to a third aspect, in the first aspect, the receiver is so designed that an antenna can be connected thereto to receive the digital broadcasting signal, and in the PLL circuit checking step, the digital broadcasting signal inputted through the antenna is used as the input signal 8 to the receiver.

In normal operation, the receiver receives the digital broadcasting signal to generate sound. In the third aspect, the digital broadcasting signal is used for checking whether a defect occurs in the receiver or not. The receiver can thus execute each step without using expensive signal generators as mentioned in the second aspect, thereby cutting investment in equipment in relation to the receiver.

These and other objects, features, aspects and advantages of the present invention will become more apparent from the following detailed description of the present invention when taken in conjunction with the accompanying drawings.

FIG. 1 is a block diagram showing the general structure of a receiver Rx according to one embodiment of the present Invention; FIGS. 2, 3, 4 are a flow chart showing the procedure to be executed by a controller 19 shown in FIG. 1; FIG. 5 is a flow chart showing the detailed procedure in step S8 of FIG. 3; FIG. 6 is a flow chart showing the detailed procedure in step S10 of FIG. 3; FIG. 7 is a flow chart showing the detailed procedure in step S12 of FIG. 3; 9 FIG. 8 is a flow chart showing the detailed procedure in step S14 of FIG. 3; FIG. 9 is a flow chart showing the detailed procedure in step S15 of FIG. 3; FIG. 10 is a table for self -diagnostic modes shown by the states of an operation mode selector 16 shown in FIG. 1; FIG. 11 is a diagram illustrating an operating keypad 17 shown in FIG. 1; FIG. 12 is a diagram illustrating flags Fl,, F20, F2.1 and FFRA14E to be used by the controller 19 of FIG. 1 in the procedure such as shown in FIG. 3; FIG. 13 is a diagram illustrating messages on a display 18 shown in FIG. 1; FIG. 14 is a diagram showing the block structure of a voltage detector 15 shown in FIG. 1 in detail; FIG. 15 is a diagram showing one example of transition among diagnostic phases shown in FIGS. 2 to 9; FIG. 16 is a diagram partially showing the structure of the receiver Rx when a BER detector 29 is provided therefor; FIG. 17 is a diagram showing the relation between C/N ratio and BER; FIG. 18 is a diagram showing the data structure of an audio data frame a; and FIG. 19 is a diagram showing a method of generating a master frame and its data structure.

FIG. 1 is a block diagram showing the general structure of a receiver Rx according to one embodiment of the present invention.

In FIG. 1, the receiver Rx includes an input terminal 1, a tuner 2, a PLL sync detector 3, a QPSK demodulating part 4, a CH decoding part 5, an MPEG decoder 6, a D/A converter 7, a low-frequency amplifier 8, a speaker 9, a first switch for muting 10, a power supply 11, a second switch for power supply, a first regulator 13, a second regulator 14, a voltage detector 15, an operation mode selector 16, an operating keypad 17, a display 18, and a controller 19.

The tuner 2 includes a PLL circuit 20. The tuner 2 also includes other various components, but both components are not shown in the drawing because they are not relevant to self - diagnostic modes (will described later) that are unique to the present invention. The QPSK demodulating part 4 includes a QPSK demodulator 21, a QPSK sync detector 22, and a C/N detector 23. 20 The CH decoding part 5 includes a CH decoder 24, a frame sync detector 25, and a CH sync detector 26. The controller 19 operates according to the procedures shown In flow charts of FIGS. 2 to 9 to control a 'factory self-diagnostic mode, "normal operation mode", or "service self-diagnostic mode", which are described below.

11 1. Factory self-diagnostic mode First, an inspector at a factory makes a setup for the factory self - diagnostic mode in quality inspection for shipment. At this time, a signal generator (not shown) is connected to the 5 input terminal 1 of FIG. 1.

The operation mode selector 16 has two switches (not shown) and two terminals A and B (refer to FIG. 1). One of the switches is connected to the terminal A, while the other is to the terminal B. The two switches are set ON or OFF, and the tree modes as mentioned above are specified by combinations of ON and OFF.

In FIG. 10, the switch connected to the terminal A is represented by a switch A, while the switch connected to the terminal B is by a switch B. Further, "0" represents that the switch A or B is OFF, while "l' represents that the switch A or B i s ON.

(1) When the switch A is "1" (ON) and the switch B is "0" (OFF), the receiver Rx is set to the f actory self -diagnostic mode. (2) When the switch A is 'C (OFF) and the switch B is "1" (ON), the receiver Rx is set to the service self -diagnostic mode. (3) When the switches A and B are both "1" (ON), the receiver Rx is set to the normal operation mode. Here, the inspector operates the operation mode selector 16 to set the receiver Rx to the factory self - diagnostic mode for execution. 25 When the second switch 12 shown in FIG. 1 is turned ON, a 12 power supply voltage V,, is supplied to the second regulator 14. The second regulator 14 generates drive voltages V,, V,, and V,. The drive voltage Vt is supplied to the tuner 2 for operation. The drive voltage V, is supplied to the QPSK demodulating part 4 and the D/A converter 7 for operation. The drive voltage Vd is supplied to the CH decoding part 5 and the MPEG decoder 6 f or operation. Thus, the receiver Rx starts operation.

Since it is not necessary to generate sound in the factory selfdiagnostic mode, the first switch 10 is turned OFF.

Therefore, the low-frequency amplifier 8 does not operate, and the receiver Rx is in a mute state.

After the above setup, the controller 19 determines a mode to be executed. That is, the states of the switches A and B in the operation mode selector 16 are read (step S1, FIG. 2). Next, the controller 19 determines whether the state of the operation mode selector 16 indicates the factory self-diagnostic mode or not (step S2). At this point, the state indicates the factory self -diagnostic mode, and therefore the procedure goes to step S3. If the state indicates otherwise, the procedure goes to step S22, which will be described later.

In a storage area of the receiver Rx, end f lags F,., F201 F,,, and F,,,m as shown in FIG. 11 are provided in advance. The end f lag F14 'S set to either 0 or 1 by the controller 19 to indicate whether a diagnostic phase of the second regulator 14 has ended or not. Similarly, the end f lag F2. indicates whether a diagnostic 13 phase for the PLL circuit has ended or not. The end flag F,, indicates whether a diagnostic phase for the QPSK demodulator 21 has ended or not. The end f lag F..... indicates whether a f rame sync diagnostic phase has ended or not. 5 In step S3, the controller 19 sets the end flags F14, F20 F21, and FFRAMEE t 0 0, as shown in (a) of FIG. 11. Therefore, each end flag indicates that its diagnostic phase has not ended. The operating keypad 17 includes various keys such as shown In (a) of FIG. 12. These keys may be constructed by using connectors or through soldering. However, poor contact of the connectors or poor soldering may occur before shipment. Since the receiver Rx must not be shipped in such defective conditions, the controller 19 is required to check the conditions of the operating keypad 17. For this diagnostic check, the controller 19 executes a diagnostic phase for the operating keypad 17. 1-1. Diagnostic phase for the operating keypad 17 In this diagnostic phase, the controller 19 first makes a predetermined message displayed on the display 18, for example, to prompt the inspector to operate all keys. The operating keypad 17 generates a signal specifying the operated key. The controller 19 accesses to the operating keypad 17 in order to receive the input of the key on the operating keypad 17 (step S4). That is, the controller 19 accesses to the operating keypad 17 in order to receive the generated signal. When receiving the key input successfully (step S5), the controller 19 identif ies the operated 14 key, and causes the display 18 to display the state (step S6). For example, as shown in (b) of FIG. 12, when a key "B" is operated by the inspector, the operating keypad 17 generates a signal S, specifying the key "Bo. The generated signal S, is received by the controller 19. The controller 19 identifies the received signal S,, and causes the display 18 to display the state indicating th.at the key "B" has been operated. Note that, in (b) of FIG. 12, keys operated are drawn by solid lines, while keys not yet operated are by dotted lines.

After step S6, or when not receiving the key input successfully in step S5, the procedure exits the diagnostic phase for the operating keypad 17 to go to step S7 of FIG. 3. Then, the controller 19 determines whether the diagnostic phase for the second regulator 14 has been executed or not (step S7). In step S7, the controller 19 refers to the above described end flag F,,. The end flag F,. has been indicating 0 since step S3. Therefore, the controller 19 determines that the diagnostic phase for the second regulator 14 has not yet been executed. Then, the procedure goes to step S8.

1-2. Diagnostic phase for the second regulator 14 For correct operation of the tuner 2, its operating voltage has to be within a predetermined range. Now, assuming a minimum operating voltage of the tuner 2 'S VMIN, and a maximum operating voltage thereof is V.. 1, the drive voltage V, supplie'd to the tuner 2 has to satisfy V,,,, 5 Vt 5 V.,,,,. Similarly, assuming a minimum operating voltage of the QPSK demodulating part 4 and the D/A converter 7 'S V.IN2 and a maximum operating voltage thereof is VMAX21 the drive voltage V, has to satisf yVMIN2 'S Va VMAX2 'Similarly, assuming a minimum operating voltage of the CH decoding part 5 and the MPEG decoder 6 'S VMIN3 and a maximum operating voltage thereof is V,,,,, the drive voltage V, has to satisfy V,,,,:5 V d 5 VMM3' Note that, although it is assumed for the sake of convenience in the present embodiment that the operating voltages of the QPSK demodulating part 4 and the D/A converter 7 are equal, they may be different instead. The same goes for the operating voltages of the CH decoding part 5 and the MPEG decoder 6.

If VMIN1 < Vt < VMAX10 VMIN2 < Va < VMAX2. and/or VMIN3 Vd < VMAX3 is not satisfied, that is, if the second regulator 14 cannot generate the drive voltage Vt, V,, and/orVd the receiver Rx with such defect also must not be shipped.

For this reason, the receiver Rx executes the diagnostic phase for the second regulator 14. In this diagnostic phase, the detection result by the voltage detector 15 is used. The voltage detector 15 includes, as shown in FIG. 13, a switch 27 and an A/D converter 28. The switch 27 is connected to the second regulator 14. The switch 27 selectively receives the drive voltage V, V,, or Vd that is specified by the controller 19, and then supplies the received voltage to the A/D converter 28. The A/D converter 28 converts the drive voltage Vt, V,, or Vd from analog to digital, 16 that is, digitizes the drive voltage. The digitized drive voltage Vt, V, or Vd is received by the controller 19 as the detection result.

With reference to a flow chart shown in FIG. 5, the detailed ' procedure of the diagnostic phase (step S8 of FIG. 3) is now described. In step S81 of FIG. 5, the controller 19 flips the switch 27 of the voltage detector 15 to specify either drive voltage Vt, V, orVd The specif ied drive voltage Vt, V, or Vd 'S supplied to the A/D converter 28 via the switch 27. The supplied voltage Vt, V, or Vd is digitized by the A/D converter 28, and then received by the controller 19 (step S81).

Next, it is determined whether the received drive voltage or 5 vt, V, or Vd satisf ies V,,, 5 Vt: VMM1 1 VKIN2:5 Va 5 VMM21 VIIN3 V d =5 V,,, respectively (step S82). If the above inequality is not satisfied, the controller 19 causes the display 18 to display "VOLT NW as shown in (a) of FIG. 14 indicating anomalies in the drive voltage generated by the second regulator 14 (step S83).

For example, assuming that the drive voltage Vt is specified In step S81, it is determined in step S82 whether the digitized drive voltage Vt satisfies the inequalityVMIN1:S Vt:!:5 V,_,, or not.

If this inequality is not satisfied, the display 18 notifies the inspector of a defect in the second regulator 14 in step S83.

On the other hand, if the above inequality is satisfied in step S82, it is determined whether all drive voltages Vt, V,, and V, have been selected or not (step S84). If any of these drive 17 voltages V, V,, andVd is left unselected, the procedure returns to step S81, in which the controller 19 specifies the unselected one to continue the present diagnostic phase.

On the other hand, if the all drive voltages Vt, V,, and Vdhave been selected, the controller 19 determines that the second stabilized voltage supply 14 is normal and that the present diagnostic phase may end. Therefore, the end flag F,, is set 1 as shown in (b) of FIG. 11 (step S85) and thereby it is displayed that the diagnostic phase f or the second power supply 14 has ended.

Then, a setup for the following diagnostic phase for the PLL circuit is performed (step S86). In step S86, a timer (not shown) is reset, that is, a time tE is set to 0, and the timer starts measuring the time t,. After step S86, the controller 19 ends the diagnostic phase for the second regulator 14, that is, ends step S8 of FIG. 3.

As described above, in the present diagnostic phase, it is determined whether the drive voltages V,, V,, and Vd are within each predetermined range or not. If any drive voltage is detected as not being within that range, the display 18 notifies the inspector of a defect in the second regulator 14. The inspector thus can prohibit shipment of the receiver Rx with the defect in the second regulator 14.

After step S8, the procedure returns to step S4 of FIG. 2, that is, the diagnostic phase f or the operating keypad 17.

Therefore, the inspector operates one of the keys, the operated 18 key is displayed on the display 18 (steps S4 to S6). Then, the controller 19 determines whether the diagnostic phase for the second regulator 14 has been executed or not by referring to the end flag F14 (step S7 of FIG. 3). The end flag F,, has been set 1 since step S85. Therefore, the controller 19 determines that the diagnostic phase f or the second regulator 14 has been executed, and the procedure goes to step S9. In step S9, the controller 19 refers to the above described F2.. The end flag FE, remains 0 since step S3. Therefore, the controller 19 determines that the diagnostic phase for the PLL circuit 2 0 has not yet been executed, and the procedure goes to step S10.

1-3. Diagnostic phase for the PLL circuit 20 The signal generator is connected to the input terminal 1. The signal generator generates the simulation signal Ss,m simulating the digital broadcasting signal SDB. The simulation signal Ss:rm is obtained by modulating (QPSK -modulating) two carriers perpendicular to each other in phase with the master frame (refer to (b) of FIG. 19). The simulation signal Ss,, is provided to the tuner 2 via the input terminal 1. The tuner 2 mixes the received simulation signal S,,, and a local oscillation output from a voltage controlled oscillator in frequency, thereby down- converting the received simulation signal Ss,, into an intermediate-f requency signal S,,. The frequency and phase of the local oscillation output are adjusted by the PLL circuit 20 to synchronize with a reference frequency and reference phase 19 generated by a crystal oscillator or the like (not shown). Here, a time period from start of operation of the PLL circuit 20 to establishment of synchronization is referred to as a lock time tLl The lock time tL1 can be obtained by actually operating the receiver Rx. The lock time tRI serves as a basis for a reference time tR1 The reference time tRI 'S calculated by adding a required time margin t,l (t,, > 0) to the lock time tLl. For example, if tLI 'S selected as the time margin t,l, the reference time tR1 'S 2 X tLl. Therefore, if normal, the PLL circuit 20 can always establish synchronization within the reference time t,l.

The PLL circuit 20 may also be defective at quality inspection. The defective PLL circuit 20 cannot establish synchronization within the time f rom starting of operation to the reference time t,,,. The receiver Rx with such defect in the PLL circuit 20 is not suitable for shipment.

For this reason, the receiver Rx executes the diagnostic phase for the PLL circuit 20. In this phase, the detection result of the PLL sync detector 3 is used. The PLL sync detector 3 is connected to the PLL circuit 20. The PLL sync detector 3 detects whether synchronization has been established in the PLL circuit 20 or not. If synchronization is detected, the detection result indicating as such is sent from the PLL sync detector 3 to the controller 19.

With reference to a flow chart shown in FIG. 6, the detailed procedure of the present diagnostic phase (step S10 of FIG. 3) is now described. In FIG. 6, it is determined whether the service self - diagnostic mode is being executed or not (step S101). At this point, since the factory self-diagnostic mode is being executed, the procedure goes to step S102. If the service self -diagnostic mode is being executed, the procedure goes to step S109, which will be described later. Assume herein that the simulation signal SsIm is included in an occupied

bandwidth B,j with a center frequency f,,. Also assume that the inspector operates the operating keypad 17 to select and input the occupied bandwidth Bc, of the simulation signal Ssjm, In response to the inspector's input, the operating keypad 17 transmits a signal SC1 f or specifying the occupied bandwidth Bc, to the controller 19. Based on the received signal Scl, the controller 19 sends frequency control data DFREQ (step S102).

The frequency control data DFREQ sets the receiving frequency band of the tuner 2 to the occupied bandwidth Bc, The tuner 2 thus starts receiving the simulation signal Ssjm to carry out the above described downconverslon.

Next, the detection result of the PLL sync detector 3 is received (step S103). Based on the received detection result, the controller 19 determines whether synchronization has been established in the PLL circuit 20 or not.(step S104).

If synchronization has not yet been established, the controller 19 fetches the reference time tR1 previously stored in a predetermined storage area. The controller 19 f urther 21 obtains the time value tE currently indicated by the timer. The value tE represents an elapsed time after step S86 (refer to FIG.

5). The controller 19 compares the elapsed time tE with the reference time t,, to determined whether t, > t,, ornot (step S105).

If not tE > t1l synchronization may possibly be established within the reference time tRI in the PLL circuit 20. Therefore, the controller 19 exits the present diagnostic phase to return to the above described diagnostic phase for the operating keypad 17. At this time, if the inspector operates one of the keys, the operated key is displayed on the display 18 (step S4 to S6). Then, after executing step S7 of FIG. 3, the controller 19 determines whether the diagnostic phase for the PLL circuit 20 has been executed or not by referring to the end f lag F,, (step S9). Since the end flag F20 is 0 the diagnostic phase for the PLL circuit 20 is executed again.

On the other hand, if tE > tRI in step S105, synchronization has not been established within the reference time t,j in the PLL circuit 20. In other words, the PLL circuit 20 is defective. Therefore, the controller 19 causes the display 18 to display 'PLL NGw as shown in (b) of FIG. 14 indicating a def ect in the PLL circuit 20 (step S106).

As described above, in the present diagnostic phase, it is determined whether the PLL circuit 20 is defective or not. If a defect is detected, the display 18 notifies the inspector as such. The inspector thus can prohibit shipment of the receiver 22 Rx with the defect in the PLL circuit 20. Further, in step S104, if synchronization has been established, it is determined that the PLL circuit 20 is normal, and that the-present diagnostic phase may end. Therefore, the 5 end flag F20 is set to 1, as shown in (c) of FIG. 11 (step S107). Further, a setup for the following diagnostic phase for the QPSK demodulator 21 is carried out (step S108). That is, the controller 19 starts the timer measuring the time t,. After step S108, the procedure exits the diagnostic phase for the PLL circuit 20.

After step S10, the procedure returns to step S4 of FIG. 2. If the inspector operates one of the keys, the operated key is displayed on the display 18 (steps S4 to S6). Then, since the end flags F.4 and F,, are both 1, the procedure goes to step S11.

The controller 19 determines whether the diagnostic phase for the QPSK demodulator 21 has been executed or not by referring to the end flag F21 (step S11). At this time, the end flag F21 is 0 1 and therefore the controller 19 determines that the diagnostic phase for the QPSK demodulator 21 has not yet been executed. The procedure then goes to step S12. 1-4. Diagnostic phase for the QPSK demodulator 21 In FIG. 1, the signal SIF is provided to the QPSK demodulator 21. The QPSK demodulator 21 carries out sync demodulation (sync detection), that is, QPSK demodulation, on the received signal S,,. Thus, a baseband signal SBBI that is, the master frame 23 (refer to (b) of FIG. 19) is reproduced. Since the above sync demodulation is similar to down-conversion in the tuner 2, a PLL circuit that is different from the PLL circuit 20 is provided in the QPSK demodulator 21. That is, also in the QPSK demodulator 21, the frequency and phase of the local oscillation output is made synchronized with those of a reference signal provided by a crystal oscillator or the like. Here, a time period from start of operation of the QPSK demodulator 21 to establishment of synchronization is referred to as a lock time tL2, The lock time tL2 can be obtained by actually operating the receiver Rx. The lock time tL2 serves as a basis for a reference time tR2, Like the reference time tR1 I the reference time tR2 is calculated by adding a required time margin t., to the lock time tL2 If synchronization is not established within the time from starting of operation of the QPSK demodulator 21 to the reference time tR21 the QPSK demodulator 21 is determined to be defective.

The receiver Rx with a def ect in the QPSK demodulator 21 is not suitable f or shipment. For this reason, the controller 19 executes the diagnostic phase for QPSK demodulator 21 in step S12.

In the present phase, the detection result of the QPSK sync detector 22 is used. The QPSK sync detector 22 is implemented by the structure similar to that of the PLL sync detector 3. The QPSK sync detector 22 is connected to the QPSK demodulator 21.

The QPSK sync detector 22 detects whether synchronization has been established in the QPSK demodulator 21. If synchronization has 24 been established, the QPSK sync detector 22 generates the detection result indicating as such. This detection result is received by the controller 19.

With reference to a flow chart shown in FIG. 7, the detailed procedure of the present diagnostic phase (step S12 of FIG. 3) is now described. In FIG. 7, the controller 19 receives the detect-ion result of the QPSK sync detector 22 (step S121). The controller 19 determines whether the received detection result indicates that synchronization has been established in the QPSK sync detector 22 (step S122). If synchronization has not been established, the controller 19 fetches -the reference time tR2 previously stored in a predetermined storage area. The controller 19 f urther obtains the value tE of the timer. The value tE represents an elapsed time af ter step S108. The controller 19 compares the elapsed time tE with the reference time tR2 to determine whether tE > t,, or not (step S123).

If not tE > tR21 the procedure exits the present diagnostic phase to return to step S4 of FIG. 2. Therefore, if the inspector operates one of the keys, the operated key is displayed on the display 18 (steps S4 to S6). Then, the controller 19 executes steps S7 and S9 of FIG. 3. Since the end f lag F2. is not 0, the procedure returns to the diagnostic phase f or the QPSK demodulator 21 (step S12).

On the other hand, if tE > tR2 in step S123, synchronization has not been established within the reference time tR2 in the QPSK demodulator 21. Therefore, the controller 19 causes the display 18 to display "QPSK NG" as shown in (c) of FIG. 14 indicating that the QPSK demodulator 21 is defective (step S124).

With this diagnostic phase, the controller 19 can detect whether the QPSK demodulator 21 is defective or not. If a defect is detected in the QPSK demodulator 21, the display 18 notifies the inspector as such. The inspector can thus prohibit shipment of the receiver Rx with the defect in the QPSK demodulator 21.

If synchronization has been established in step S122, the QPSK demodulator 21 is normal, and the controller 19 thus determines that the present diagnostic phase may end. Therefore, the end f lag F2. -is set to 1 as shown in (d) of FIG. 11 (step S125). Further, a setup for the following frame sync diagnostic phase is carried out (step S126). That is, the timer starts measuring the time t,;. Furthermore, a setup for the following receive sensitivity diagnostic phase is carried out (step S127). In the receive sensitivity diagnostic phase, a C/N ratio detected by the C/N detector 23 are used. Since the C/N ratio varies with time, the receiver Rx measures the C/N ratio a plurality of number of times, and calculates an average value C/N.. of these C/N ratios.

To count the number of measurements, a counter (not shown) is provided in the receiver Rx. In step S127, a counter value 'C/N is set to 0. After step S127, the procedure exits the present diagnostic phase (step S12 of FIG. 3).

After step S12, the procedure returns to step S4 of FIG.

26 2. Therefore, if the inspector operates one of the keys, the operated key is displayed on the display 18 (steps S4 to S6). Then, the controller 19 executes steps S7, S9, and S11, and the procedure goes to step S13. The controller 19 determines whether the frame 5 sync diagnostic phase has been executed or not by referring to the end flag F E: M (step S13). At this time, the end flag FFR E is 0. Theref ore, the controller 19 determines that the f rame sync diagnostic phase has not been executed, and the procedure goes to step S14.

1-5. Diagnostic phase for the CH decoder 24 As shown in FIG. 1, the master frames (baseband signals S,,) reproduced by the QPSK demodulator 21 are sequentially provided to the CH decoder 24. To identify the head of each master frame 0, the CH decoder 24 detects the frame sync information (ref er to (b) of FIG. 19) f rom each master f rame. This detecting operation is hereinafter referred to as frame synchronization.

Here, a time period between start of frame synchronization by the CH decoder 24 and establishment thereof is hereinafter referred to as a sync time tFS, The sync time tFS can be obtained by actually operating the receiver Rx. The sync time t,, serves as a basis f or ref erence times tR3, Like the ref erence time t,,,, the ref erence time t13 is calculated by adding a required time margin tM3 to the sync time t,,.

If f rame synchronization cannot be established within the time from starting of operation to the reference time t131 the 27 CH decoder 24 is defective. The receiver Rx with a defect in the CH decoder 24 is not suitable for shipment.

For this reason, the controller 19 executes the frame sync diagnostic phase in step S14. In the present phase, the detection result of the frame sync detector 25 is used. Here, the frame sync detector 25 is connected to the CH decoder 24 to determine whether frame synchronization has been established in the CH decoder 24. If frame synchronization has been established, the detection result indicating as such is generated. This detection result is received by the controller 19.

1-5-1. Frame sync diagnostic phase With reference to a f low chart shown in FIG. 8, the detailed procedure of the present diagnostic phase (step S14 of FIG. 3) is now described. In FIG. 8, the controller 19 receives the detection result of C/N detector 23 (step S141), and keeps the detection result in its internal storage area. Then the counter vale 'C/N is incremented by 1 (step S142). Note that steps S141 and S142 are included in the receive sensitivity diagnostic phase - If synchronization has been established in the QPSK modulator 21, the C/N ratio can be detected. Therefore, in the present embodiment, steps S141 and S142 are carried out immediately after the diagnostic phase for the QPSK demodulator 21. That is, the receive sensitivity diagnostic phase is carried out at the earliest stage in the present embodiment. As a result, the receive sensitivity diagnostic phase ends at the earliest. Thus, 28 the factory diagnostic mode can be quickly carried out.

After step S142, the controller 19 receives the detection result of the frame sync detector 25 (step S143). The controller 19 then determines whether frame synchronization has been established or not in the CH decoder 24 based on the received detection result (step S144). If frame synchronization has not yet been established, the controller 19 fetches the reference time t,, previously stored in a predetermined storage area. Further, the controller 19 obtains the timer value tE The value tE is an elapsed time after step S126. The controller 19 compares the elapsed time tE with the reference time tR, to determine whether tE > tR3 (step S145).

If not tE > tR3P the procedure exits the present diagnostic phase to return step S4 of FIG. 2. Therefore, if the inspector operates one of the keys, the operated key is displayed on the display 18 (step S4 to S6). Then, the controller 19 executes steps S7, S9, S11, and S13 of FIG. 3, and the procedure returns to the frame sync diagnostic phase (step S14).

On the other hand, if tE > tR3 in step S145, frame synchronization has not been established in the CH decoder 24 within the reference time tR3' In this case, the controller 19 recognizes that the CH decoder 24 is defective, and causes the display 18 to display "FRAME NG" as shown in (d) of FIG. 14 indicating that the frame synchronization in the CH decoder 24 is failed (step S146). As described above, in the present phase, 29 if frame synchronization is detected to be failed, the display 18 notifies the inspector as such. The inspector thus can prohibit shipment of the receiver Rx with a def ect in the CH decoder 24.

Further, if it is determined in step S144 that frame synchronization has been established, frame synchronization processing is normal. Therefore, the controller 19 determines that the present diagnostic phase may end. The end flag FFRMIM is set to 1 as shown in (e) of FIG. 11 (step S147). Further, the controller 19 carries out a setup for the f ollowing channel sync diagnostic phase (step S148). That is, the timer starts measuring the time tE" By the time of this diagnostic phase, the inspector has already selected a receive channel by operating the operating keypad 17. In response to the input by the inspector, the operating keypad 17 sends a signal SCH for specifying the receive channel to the controller 19. Based on the received signal SCHO the controller 19 further generates CH control data Dc, for specifying the receive channel in step S148. The CH control data DcH is transmitted to the CH decoder 24. Thus, the audio data frame a to be reproduced is specified among those included in master frames 3 (refer to (b) of FIG. 19).

After step S148, the procedure exits the frame sync diagnostic phase. After step S14 of FIG. 3, the procedure returns to step S4 of FIG. 2. Therefore, if the inspector operates one of the keys, the operated key is displayed on the display 18 (steps S4 to S6). Then, the controller 19 executes steps S7, S9, S11, and S 13. Since the end flag F indicates 1, the procedure goes to step S15.

1-5-2. Channel sync diagnostic phase As described above, the receive channel is specified in the CH decoder 24. The CH decoder 24 extracts the data block of the receive channel from each master frame 3. The CH decoder 24 rearranges the extracted data blocks to reproduce the audio data f rames a (ref er to (a) of FIG. 19). To identif y the head of each audio data frame a, the CH decoder 24 then detects the CH sync inf ormation f rom each audio data f rame a (ref er to FIG. 18). This detecting operation is hereinafter referred to as channel synchronization. The CH decoder 24 outputs the audio data frames a f rom its head based on the detected CH sync inf ormation. Here, a time period between start of channel synchronization by the CH decoder 24 and establishment thereof is hereinafter referred to as a sync time tcs, These sync time t,, can be obtained also by actually operating the receiver Rx. The sync time t,s serves as a basis for a reference time t,,. Like the reference time t,l, the reference time tR, is calculated by adding a required time margin tM4 to the sync time tcs If channel synchronization cannot be established within the time from starting of operation to the reference time tR41 the CH decoder 24 is defective. The receiver Rx with a defect in the CH decoder 24 is not suitable for shipment.

31 For this reason, the controller 19 executes the channel sync diagnostic phase in step S15. In the present phase, the detection result of the CH sync detector 26 is used. Here, the CH sync detector 26 is connected to the CH decoder 24, detecting whether 5 channel synchronization has been established in the CH decoder 24. If channel synchronization has been established, the CH sync detector 26 generates the detection result indicating as such. This detection result is received by the controller 19.

With reference to a flow chart shown in FIG. 9, the detailed procedure of the present diagnostic phase (step S15 of FIG. 3) is now described. In FIG. 9, the controller 19 receives the detection result of the CIN detector 23 (step S151), and keeps the detection result in its internal storage area. Then, the counter value 'C/N is incremented by 1 (step S152). Like steps S141 and S142, steps S151 and S152 are included in the receive sensitivity diagnostic phase.

The controller 19 then receives the detection result of the CH sync detector 26 (step S153). The controller 19 determines whether frame synchronization has been established or not in the CH decoder 24 based on the detection result (step S154). If channel synchronization has not been established, the controller 19 obtains the reference time t,, previously stored in a predetermined storage area. The controller 19 further obtains the timer value tEl which is an elapsed time after step S148. The controller 19 compares the elapsed time t, with the reference time 32 t,, to determine whether t, > t,, or not (step S155).

If t, > t,,, channel synchronization has not been established within the reference time tR4. In this case, the controller 19 can recognize a def ect in the CH decoder 24. The controller 19 then causes the display 18 to display "CH NG" as shown in (e) of FIG. 14 indicating that channel synchronization is failed (step S156). As described above, in the present diagnostic phase, if channel synchronization is detected as being failed, the display 18 notifies the inspector as such. The inspector thus can prohibit shipment of the receiver Rx with the defect in the CH decoder 24.

On the other hand, If not tE > t,, in step S155, or if synchronization has been established in step S154, the procedure exits the present phase and goes to step S16 of FIG. 4. That is, the procedure goes to the receive sensitivity diagnostic phase. 1-6. Receive sensitivity diagnostic phase As described above, the QPSK demodulator 21 of FIG. 1 is provided with the signal S,,,. The input signal S,, includes carrier power (C) and noise power (N). The CIN detector 23 detects a carrier(C) -to-noise (N) ratio, that is, C/N ratio. This CIN ratio indicates the level of receive sensitivity of the receiver Rx to radio waves. If the CIN ratio is low, the receiver Rx is not suitable f or shipment. For this reason, the controller 19 executes the receive sensitivity diagnostic phase to detect the level of receive sensitivity for notification to the inspector.

33 In FIG. 4, the controller 19 then determines whether the value i,,, becomes a predetermined threshold 'th, that is, whether 'C/N! it, is satisfied (step S16). In other words, it is determined whether measurement of the C/N ratio is carried out for a required 5 number of times 'th' If not 'C/N 2! i th I the controller 19 determines that measurement of the C/N value is further required, and the procedure exits the present diagnostic phase. That is, the procedure returns to step S4 of FIG. 2. Therefore, if the inspector operates one of the keys, the operated key is displayed on the display 18 (step S4 to S6). The procedure goes through steps S7, S9, S11, S13, and S15 and then returns to step S16. In step S15 of this procedure, the C/N ratio is detected and the counter value 'C/N is incremented (steps S151 and S152 of FIG. 9).

On the other hand, if 'C/N 'th' the C/N ratio has been measured for the required number of times 'th. Then, as a step in the diagnostic phase for the operating keypad 17, the controller 19 determines whether all key inputs have been received or not (step S17). If it is determined that not all have been received, the procedure returns to step S4 to continue the present diagnostic phase. Here, in some cases, the display 18 displays the state of one key as not being operated even though all keys have been operated. Such key is defective due to poor contact of its connector and the like. Therefore, the inspector can recognize the defect in the operating keypad 17 by referring to 34 the screen on the display 18. For example, even though a key "A" has been operated by the inspector, the key "A" is not displayed, in some cases. Therefore, the inspector can recognize the defect in the key "A". The display 18 notifies the inspector of the 5 defect in the operating keypad 17 in the above described manner. Thus, the inspector can prohibit shipment of the receiver Rx with the defect in the operating keypad 17.

On the other hand, if all key inputs have been received, the operating keypad 17 is not defective. Theref ore, the procedure exits the diagnostic phase for the operating keypad 17 and returns to the receive sensitivity diagnostic phase, calculating an average value C/NAvE of the 'th C/N ratios (step S18). Then, it is determined whether the average value C/Nv, is larger than a predetermined threshold C/Nth (step S19). The threshold C/Nth is a threshold value for determining the level of receive sensitivity of the receiver Rx. If the average value C/NAVE is equal to or smaller than the threshold C/Nth, sound generated in the receiver Rx is supposed to include much noise, and therefore the receiver Rx is not suitable for shipment.

If not C/NVE > C/Nth' the controller 19 causes the display 18 to display "C/N NG" as shown in (g) of FIG. 14 indicating that receive sensitivity is low (step S20). That is, if the receive sensitivity is determined to be low, the display 18 notifies the inspector as such. The inspector can thus prohibit shipment of the receiver Rx with low receive sensitivity.

On the other hand, if it is determined in step S19 that C/NAVE > C/Nth, the controller 19 determines that the receive sensitivity is high. Consequently, the controller 19 recognizes that the operating keypad 17, the second regulator 14, the PLL circuit 20, the QPSK demodulator 21, the CH decoder 24, and the receive sensitivity of the receiver Rx are all normal. The controller 19 then causes the display 18 to display "CHECK OK" as shown in (h) of FIG. 14 indicating good diagnostic results of the receiver Rx (step S21). The inspector thus can allow only shipment of the receiver Rx that operates normally.

After the above factory self-diagnostic mode, the controller 19 provides a switch control output SW to the first switch 10 to set it ON. Therefore, the power supply voltage Vc, is also supplied to the low-frequency amplifier 8, enabling the speaker 9 to generate sound. The inspector can thus determine whether the receiver Rx normally generates sound or not by actually listening to the sound after the factory self -diagnostic mode. This switch control output SW enables more detailed quality inspection.

Finally, the inspector operates the operation mode selector 16 to set the mode of the receiver Rx to the normal operation mode.

That is, the switches A and B on the operation mode selector 16 are both set ON (ref er to FIG. 10). Thereafter, the normal receiver Rx is shipped to a user.

2. Normal operation mode 36 The user enjoys sound through the receiver Rx. Atthistime, the normal operation mode is executed in the receiver Rx. Since this mode is well known, its description is simplified herein. First, the user connects an antenna (not shown) to the input 5 terminal 1.

After the second switch 12 is set ON, the states of the switches A an B of the operation mode selector 16 are read (step S1, FIG. 2). Based on the read states, the controller 19 then determines whether the factory self -diagnostic mode is now to be executed or not (step S2). As stated above, the states of the switches A and B are set in the normal operation mode at the time of shipment (refer to FIG. 10). Therefore, the procedure goes to step S22. The controller 19 deterTnines whether the service self -diagnostic mode is now to be executed or not (step S22). At this time, the mode to be executed is the normal operation mode, and therefore the procedure goes to step S23.

As mentioned in the Background Art section, satellite broadcasting service of the WorldSpace system covers a wide range of service areas. The digital broadcasting signal S,, from the stationary satellite occupies different frequency bands in predetermined different areas. Therefore, the user has to set the receive area when using the receiver Rx. At this time, the display 18 displays 'SERVICE AREA No.?_" as shown in (i) of FIG. 14 to prompt the user to enter information for specifying the receive area. Also as stated in the Background Art section, the

37 digital broadcasting signal S,, is multiplexed with audio data for predetermined n channels. Therefore, the user has to enter the channel to enjoy digital broadcasting through the receiver Rx. For these reasons, the user operates the operating keypad 17 to specify the receive area and the channel. The operating keypad 17 generates a signal S,,,, for specifying the receive area and the signal S, , for specifying the channel.

In step S23, the controller 19 first receives the signal S... generated by the operating keypad 17. The controller 19 adjusts the receiving frequency band using frequency control data DFREQ generated based on the signal SAREA. The tuner 2 thus starts receiving the digital broadcasting signal S,,.

The digital broadcasting signal S,, from the stationary satellite is received by the tuner 2 through the antenna and then the input terminal 1, and down-converted to the intermediatefrequency signal SIF, The signal S,, is provided to the QPSK demodulator 21.

The QPSK demodulator 21 demodulates the QPSK-modulated signal SIF to the baseband signal SBB to reproduce the master frame 0 (refer to (b) of FIG. 19). The reproduced master frame is provided to the CH decoder 24.

As described above, the controller 19 receives the signal SAREA and also the signal S,,, for specifying the channel. Based on the signal SCHI the controller 19 generates CH control data DCH The CH control data DCH specif ies the audio data frame a to 38 be decoded by the CH decoder 24.

As shown in (b) of FIG. 19, the master f rame 8 is sent out for each time T2. Therefore, the CH decoder 24 is provided with the master frames in sequence. First, the CH decoder 24 carries out frame synchronization to identify the head of each master frame. After frame synchronization is established, the CH decoder 24 extracts the data block of the channel specified by the CH control data DcH from each master frame. The CH decoder 24 then rearranges the extracted data blocks to reproduce the audio data frames a. After carrying out channel synchronization, the CH decoder 24 provides the audio data frames a from head to the MPEG decoder 6.

The MPEG decoder 6 decompresses the audio data frame a digital-compressed by MP3 for reproduction, and provides the decompressed audio data to the D/A converter 7. The D/A converter 7 converts the received audio data from digital to analog, and then provides the analog audio data to the low-f requency amplif ier 8. The low-frequency amplifier 8 amplifies the received analog audio data to drive the speaker 9. The speaker 9 generates sound based on the received audio data.

With the above described normal operation mode, the user can enjoy digital broadcasting. However, the receiver Rx may break down while being used by the user. In this case, the user asks a local service center or the like to repair the receiver Rx. At the service center, in order to specify a defective part 39 of the receiver Rx, the service self -diagnostic mode is executed in the receiver Rx, which is described next below. 3. Service self-diagnostic mode As stated above, the simulation signal

S,,, from the signal generator is used in the factory self-diagnostic mode because quality inspection with high accuracy is required. However, signal generators are expensive, and some service centers cannot afford to have such signal generators. For this reason, in the service self diagnostic mode for running a diagnostic check for its defective part, the receiver Rx uses the digital broadcasting signal S,, actually sent from the stationary satellite. The service self- diagnostic mode is described below in detail, but the processing similar to that in the f actory self -diagnostic mode is briefly described.

An inspector at a service center or the like makes a setup for inspecting the receiver Rx. First, the inspector connects the antenna (not shown) to the input terminal 1. Further, the inspector operates the operation mode selector 16 to set the operation mode to be executed as the service self -diagnostic mode, set the switch A to 0 (OFF), and set the switch B to 1 (ON) (refer to FIG. 10).

As described above, the occupied bandwidth for the digital broadcasting signal S,, differs according to the areas. Therefore, when the receiver Rx uses the digital broadcasting signal S,,, for running a diagnostic check for a defective part, the inspector has to enter the receive area, that is, the frequency band of the signal to be received by the receiver Rx. Furthermore, the digital broadcasting signal S,, is multiplexed with the audio data for the predetermined n channels. Therefore, the inspector has to enter any one of the channels f or the receiver Rx to execute the service self-diagnostic mode. For these reasons, the inspector operates the operating keypad 17 to specify the receive area and the channel. The operating keypad 17 generates the signal S,,,,, for specifying the receive area and the signal Sc, for specifying the channel.

In step S24, the controller 19 first receives the signals SARSA and ScH generated by the operating keypad 17. These signals SAREA and ScH are kept in storage area in the controller 19 (step S24). Then the controller 19 executes the above described step S3. Note that the signal SAREA is used in a diagnostic phase for the PLL circuit 20 (refer to step S109, FIG. 6) In the service self-diagnostic mode, as described above, the digital broadcasting signal S,, actually sent out to the service areas is used. Therefore, the tuner 2 has to selectively receive the digital broadcasting signal S,, varying in occupied bandwidth according to the location of the service center. For this reason, in the diagnostic phase for the PLL circuit 20 as shown in FIG. 6, step S101 is included to determine whether the service self-diagnostic mode is now being executed or not.

If it is determined in step S101 that the service self- 41 diagnostic mode is being executed, the controller 19 generates the frequency control data DFRE, based on the signal SAREA kept in step S24. As described above, the receiver Rx has been provided with the digital broadcasting signal S DB The digital broadcasting signalSDB is obtained by QPSK-modulating the carrier of a frequency fC2 assigned to the receive area with the master frame shown (b) of FIG. 19. Therefore, the digital broadcasting signal SDB 'S included in an occupied bandwidth B,, with its center frequency as the frequency fC2 The controller 19 sends the generated frequency control data DFREO (step S109) to set the receiving frequency band of the tuner 2 to the occupied bandwidth BC2. The tuner 2 thus starts receiving the digital broadcasting signal S,,, and down-conversion is carried out.

After step S109, the procedure goes to step S103.

As described in the foregoing, in the normal operation mode, the receiver Rx receives the digital broadcasting signal S,, generated based on time division multiplex and QPSK modulation techniques and then generates sound. The receiver Rx executes the two types of self-diagnostic modes as required. In either self -diagnostic mode, the controller 19 of the receiver Rx checks whether each part consisting the receiver Rx is defective or not.

That is, the receiver Rx runs diagnostic checks on itself, thereby reducing the inspector's workload of quality inspection or inspection f or defect. Furthermore, the controller 19 can reliably determine whether each part works normally or not through 42 decision steps of its own procedure (FIGS. 2 to 9).

Both of the self -diagnostic modes include the diagnostic phases for the operating keypad 17, the second regulator 14, the PLL circuit 20, the QPSK demodulator 21, frame synchronization, channel synchronization, and receiver sensitivity. In the diagnostic phase for the operating keypad 17, a signal corresponding to the key operated by the inspector is generated. Based on the signal generated by the operating keypad 17, the controller 19 causes the display 18 to display the operated key.

In this way, since human operation is required in the diagnostic phase for the operating keypad 17, the controller 19 has to wait for the human operation even though being capable of high-speed operation. Furthermore, the level of receive sensitivity is determined based on the C/N ratio that varies with time. For accurate determination, it is required to measure the C/N ratio several times and place an interval between measurements. Therefore, assuming that only the diagnostic phase for the operating keypad 17 and the receive sensitivity diagnostic phase are sequentially carried out, the controller 19 tends to be in a wait state in both phases. That is, an idle time occurs. Such idle time should be minimized in order to reduce inspector's work hours. Therefore, in the present embodi-ment, with the procedure shown in FIGS. 2 to 9, the diagnostic phases for the second 25 regulator 14, the PLL circuit 20, the QPSK demodulator 21, frame 43 synchronization, and channel synchronization are carried out during the diagnostic phase for the operating keypad 17 or the receive sensitivity diagnostic phase. In other words, these diagnostic phases can be executed using an idle time of the controller 19. By way of example only, FIG. 15 shows phase transition in the factory self-diagnostic mode. Thus, the controller 19 can execute more phases through the effective use of time, enabling quick checks for determining whether each component of the receiver Rx is defective or not. In other words, processing time required for the entire procedure in each of the above two self-diagnostic modes can be reduced.

The receiver Rx is so constructed to be connected to the signal generator, and uses the simulation signal S,j, from the signal generator in the factory self -diagnostic mode. Therefore, strict quality inspection before shipment can be carried out on the receiver Rx.

Further, in the service self -diagnostic mode, the digital broadcasting signal S,,, from the stationary satellite can be used. Therefore, the service center can easily and reliably find a defective part without using expensive signal generators.

Note that, nevertheless, if the service center has a signal generator, the factory self -diagnostic mode may be executed for finding a defective part.

In the above embodiment, the controller 19 determines the level of receive sensitivity based on the C/N ratio. However, 44 the CIN ratio is one example of indicators designating receive sensitivity, and BER (Bit Error Rate) may be used alternatively. FIG. 16 is a diagram showing the structure of a receiver Rx for determining receive sensitivity based on BER. The receiver Rx of FIG. 16 is different from that of FIG. 1 only in that a BER detector 29 is provided instead of the CIN detector 23. Therefore, FIG. 16 explicitly depicts the difference only.

The BER detector 29 is inserted between the CH decoder 24 and the controller 19. The BER detector 29 detects BER based on the decoding result of the CH decoder 24, and sends BER to the controller 19. There is the correlation as shown in FIG. 17 between BER and CIN ratio. Therefore, the controller 19 can determine the level of receive sensitivity using the received BER as well as using the C/N ratio.

Furthermore, In the above embodiment, the display 18 notifies the inspector of the defective part of the receiver Rx. However, the speaker 9 can also easily notify the defective part through sound. That is, the receiver Rx: may include any component that can notify the inspector of the diagnostic result of the controller 19.

While the invention has been described in detail, the foregoing description is in all aspects illustrative and not restrictive. It is understood that numerous other modifications and variations can be devised without departing from the scope of the invention.

Claims

C L A I M S

1. A self -diagnostic method that is executed as required by a receiver for receiving digital broadcasting signal from an artificial satellite and generating sound to check whether the receiver has a defect or not, said digital broadcasting signal being generated by time -division -multiplexing audio data frames generated based on audio data for a predetermined number of channels, constructing a master frame based on the multiplexed audio data frames, and then QPSK (Quadrature Phase Shift Keying) modulating a carrier with the constructed master frame, said method comprising the steps of:

checking whether each drive voltage for drivingsaid receiver is within a predetermined range and notifying an inspector of a check result; checking whether synchronization can be established in a PLL circuit required f or down-conversion by mixing an input signal to said receiver and a local oscillation output to generate an intermediate- frequency signal, and notifying the inspector of a check result; checking whether synchronization can be established in a QPSK demodulator required for QPSK-demodulating the intermediate-frequency signal generated through said down conversion and reproducing the master frame, and notifying the 46 inspector of a check result; 25 checking, in frame synchronization processing for detecting a head of the master frame reproduced through said QPSK demodulation, whether the head is correctly detected, and notifying the inspector of a check result; checking, in channel synchronization processing for detecting a head of the audio data frame reproduced based on the master frame with the head thereof detected through said frame synchronization processing, whether the head of the audio data frame is correctly detected, and notifying a check result; checking whether an operating keypad as a user interface operates correctly, and detecting a plurality of C/N ratios (Carrier to Noise Ratio) of the intermediate - frequency signal inputted to said QPSK demodulator, calculating an average value of the detected CIN ratios, and checking on a level of receive sensitivity of said receiver based on the average value, wherein said drive voltage checking step, said PLL circuit checking step, said QPSK demodulator checking step, said frame synchronization checking step, and said channel synchronization checking step are carried out during an idle time in said operating keypad checking step and said receive sensitivity checking step.

2. 1 The self -diagnostic method according to claim 1, wherein 47 said receiver is so designed that a signal generator for generating a simulation signal simulating said digital broadcasting signal can be connected thereto, and in said PLL circuit checking step, the simulation signal generated by said signal generator is used as the input signal to said receiver.

3. The self -diagnostic method according to claim 1, wherein said receiver is so designed that an antenna can be connected thereto to receive said digital broadcasting signal, and in said PLL circuit checking step, the digital broadcasting signal inputted through the antenna is used as the input signal to said receiver.

4. A self-diagnostic method that is executed as required by a receiver substantially as hereinbefore described with reference to the accompanying drawings.

48