GB2349998B - Techniques of fabricating integrated circuits having interfaces compatible with different operating voltage condotions - Google Patents

Techniques of fabricating integrated circuits having interfaces compatible with different operating voltage condotions

Info

Publication number
GB2349998B
GB2349998B GB0020337A GB0020337A GB2349998B GB 2349998 B GB2349998 B GB 2349998B GB 0020337 A GB0020337 A GB 0020337A GB 0020337 A GB0020337 A GB 0020337A GB 2349998 B GB2349998 B GB 2349998B
Authority
GB
United Kingdom
Prior art keywords
condotions
techniques
integrated circuits
operating voltage
different operating
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
GB0020337A
Other versions
GB2349998A (en
GB0020337D0 (en
Inventor
Rakesh H Patel
John E Turner
John D Lam
Wilson Wong
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Altera Corp
Original Assignee
Altera Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Altera Corp filed Critical Altera Corp
Priority claimed from GB9710966A external-priority patent/GB2313968B/en
Publication of GB0020337D0 publication Critical patent/GB0020337D0/en
Publication of GB2349998A publication Critical patent/GB2349998A/en
Application granted granted Critical
Publication of GB2349998B publication Critical patent/GB2349998B/en
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
    • H03K19/0021—Modifications of threshold
    • H03K19/0027—Modifications of threshold in field effect transistor circuits
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
    • H03K19/003—Modifications for increasing the reliability for protection
    • H03K19/00315—Modifications for increasing the reliability for protection in field-effect transistor circuits
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
    • H03K19/0175—Coupling arrangements; Interface arrangements
    • H03K19/0185—Coupling arrangements; Interface arrangements using field effect transistors only
    • H03K19/018507—Interface arrangements
    • H03K19/018521—Interface arrangements of complementary type, e.g. CMOS
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
    • H03K19/0175—Coupling arrangements; Interface arrangements
    • H03K19/0185—Coupling arrangements; Interface arrangements using field effect transistors only
    • H03K19/018585—Coupling arrangements; Interface arrangements using field effect transistors only programmable

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Physics & Mathematics (AREA)
  • Computing Systems (AREA)
  • General Engineering & Computer Science (AREA)
  • Mathematical Physics (AREA)
  • Semiconductor Integrated Circuits (AREA)
GB0020337A 1996-05-28 1997-05-28 Techniques of fabricating integrated circuits having interfaces compatible with different operating voltage condotions Expired - Fee Related GB2349998B (en)

Applications Claiming Priority (7)

Application Number Priority Date Filing Date Title
US1849496P 1996-05-28 1996-05-28
US1846596P 1996-05-28 1996-05-28
US1851096P 1996-05-28 1996-05-28
US2283796P 1996-07-31 1996-07-31
US3161796P 1996-11-27 1996-11-27
US4681097P 1997-05-02 1997-05-02
GB9710966A GB2313968B (en) 1996-05-28 1997-05-28 Techniques of fabricating integrated circuits having interfaces compatible with different operating voltage conditions

Publications (3)

Publication Number Publication Date
GB0020337D0 GB0020337D0 (en) 2000-10-04
GB2349998A GB2349998A (en) 2000-11-15
GB2349998B true GB2349998B (en) 2001-02-28

Family

ID=27562938

Family Applications (2)

Application Number Title Priority Date Filing Date
GB0020337A Expired - Fee Related GB2349998B (en) 1996-05-28 1997-05-28 Techniques of fabricating integrated circuits having interfaces compatible with different operating voltage condotions
GB0020344A Expired - Fee Related GB2349999B (en) 1996-05-28 1997-05-28 Techniques of fabricating integrated circuits having interfaces compatible with different operating voltage conditions

Family Applications After (1)

Application Number Title Priority Date Filing Date
GB0020344A Expired - Fee Related GB2349999B (en) 1996-05-28 1997-05-28 Techniques of fabricating integrated circuits having interfaces compatible with different operating voltage conditions

Country Status (1)

Country Link
GB (2) GB2349998B (en)

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
GB2374475B (en) * 2000-12-15 2005-05-11 Micron Technology Inc Input-output buffer circuit and method for avoiding inadvertent conduction of a pull-up transistor

Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0116820A2 (en) * 1983-02-21 1984-08-29 Kabushiki Kaisha Toshiba Complementary MOS circuit
US4675557A (en) * 1986-03-20 1987-06-23 Motorola Inc. CMOS voltage translator
US4857763A (en) * 1985-01-26 1989-08-15 Kabushiki Kaisha Toshiba MOS semiconductor integrated circuit in which the production of hot carriers near the drain of a short n channel conductivity type MOS transistor is decreased
US4959561A (en) * 1989-01-04 1990-09-25 Motorola, Inc. MOS output buffer with reduced supply line disturbance
GB2237945A (en) * 1989-11-09 1991-05-15 Intel Corp Output buffers
US5300835A (en) * 1993-02-10 1994-04-05 Cirrus Logic, Inc. CMOS low power mixed voltage bidirectional I/O buffer

Family Cites Families (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5521530A (en) * 1994-08-31 1996-05-28 Oki Semiconductor America, Inc. Efficient method and resulting structure for integrated circuits with flexible I/O interface and power supply voltages

Patent Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0116820A2 (en) * 1983-02-21 1984-08-29 Kabushiki Kaisha Toshiba Complementary MOS circuit
US4857763A (en) * 1985-01-26 1989-08-15 Kabushiki Kaisha Toshiba MOS semiconductor integrated circuit in which the production of hot carriers near the drain of a short n channel conductivity type MOS transistor is decreased
US4675557A (en) * 1986-03-20 1987-06-23 Motorola Inc. CMOS voltage translator
US4959561A (en) * 1989-01-04 1990-09-25 Motorola, Inc. MOS output buffer with reduced supply line disturbance
GB2237945A (en) * 1989-11-09 1991-05-15 Intel Corp Output buffers
US5300835A (en) * 1993-02-10 1994-04-05 Cirrus Logic, Inc. CMOS low power mixed voltage bidirectional I/O buffer

Also Published As

Publication number Publication date
GB2349999A (en) 2000-11-15
GB2349998A (en) 2000-11-15
GB0020344D0 (en) 2000-10-04
GB0020337D0 (en) 2000-10-04
GB2349999B (en) 2001-01-31

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Legal Events

Date Code Title Description
727 Application made for amendment of specification (sect. 27/1977)
727A Application for amendment of specification now open to opposition (sect. 27/1977)
727B Case decided by the comptroller ** specification amended (sect. 27/1977)
732E Amendments to the register in respect of changes of name or changes affecting rights (sect. 32/1977)
PCNP Patent ceased through non-payment of renewal fee

Effective date: 20080528