GB2348766A - Wipe pattern signal generator combining two wipe solids - Google Patents

Wipe pattern signal generator combining two wipe solids Download PDF

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Publication number
GB2348766A
GB2348766A GB9908241A GB9908241A GB2348766A GB 2348766 A GB2348766 A GB 2348766A GB 9908241 A GB9908241 A GB 9908241A GB 9908241 A GB9908241 A GB 9908241A GB 2348766 A GB2348766 A GB 2348766A
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ramp
generator according
generator
solid
registers
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GB2348766B (en
GB9908241D0 (en
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Jonathan Mark Greenwood
James Hendrie Mcintyre
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Sony Europe BV United Kingdom Branch
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Sony United Kingdom Ltd
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    • HELECTRICITY
    • H04ELECTRIC COMMUNICATION TECHNIQUE
    • H04NPICTORIAL COMMUNICATION, e.g. TELEVISION
    • H04N5/00Details of television systems
    • H04N5/222Studio circuitry; Studio devices; Studio equipment
    • H04N5/262Studio circuits, e.g. for mixing, switching-over, change of character of image, other special effects ; Cameras specially adapted for the electronic generation of special effects
    • H04N5/265Mixing
    • HELECTRICITY
    • H04ELECTRIC COMMUNICATION TECHNIQUE
    • H04NPICTORIAL COMMUNICATION, e.g. TELEVISION
    • H04N5/00Details of television systems
    • H04N5/222Studio circuitry; Studio devices; Studio equipment
    • H04N5/262Studio circuits, e.g. for mixing, switching-over, change of character of image, other special effects ; Cameras specially adapted for the electronic generation of special effects
    • H04N5/2622Signal amplitude transition in the zone between image portions, e.g. soft edges

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  • Engineering & Computer Science (AREA)
  • Multimedia (AREA)
  • Signal Processing (AREA)
  • Studio Circuits (AREA)
  • Controls And Circuits For Display Device (AREA)

Abstract

A signal generator for use in a wipe generator of a video mixer comprises a first input for receiving a first solid A representing a first wipe pattern, a second input for receiving a second solid B representing a second wipe pattern, an input for receiving a clip level control signal k, and means for combining the first and second solids as a function f(k) of the clip level control signal. Preferably the function is:<BR> f(k)*A + (1-f(k))*B.<BR> where f(k) may be k, or a linear, non-linear or discontinuous function of k. The effect is to change the shape of the solid at the same time as the wipe progresses. Each solid is produced by combining a plurality of ramp signals. The solids may be edge modulated and/or solid-modulated.

Description

SIGNAL GENERATOR The present invention relates to a signal generator. Such a signal generator is preferably for generating a'solid'used in a video wipe generator of a vision mixer.
A solid is an electrical signal representing a three dimensional surface of a desired shape. It comprises at least one ramp signal and typically comprises a combination of at least two ramp signals which themselves may be modified. It may also comprise a signal defined by a polar coordinate system representing a curved surface.
Reference will now be made to Figures 1 to 3 of the accompanying drawings which show background to the present invention.
Figure 1 illustrates a known simple wipe between two video sources X and Y.
As the wipe proceeds as indicated by arrow W, video X is replace across the display by video Y (or vice versa). The effect of a wipe is achieved by mixing the video sources X and Y according to KX + (1-K) Y where K is a keying signal. The keying signal K is derived from a'solid'. This will be explained with reference to Figures 2 and 3 i. e. a function having a value depending on the h and v co-ordinates within the picture, where v represents line number and h represents pixel position along a line.
Figure 2 a illustrates a known example of a'solid'which is a simple ramp. As shown in Figure 2, a clip level CP is defined. It will be appreciated that over a field or frame, the clip level defines a plane referred to herein as the clip plane, which will be described in more detail with reference to Figure 4 below. The keying signal K is, in known manner, derived from the solid by applying high gain to the solid and limiting the result, as shown in Figure 2B. The keying signal has two levels 0 and 1. The transition between the levels occurs where the solid intersects the clip plane CP. The position of intersection is varied, to produce the wipe, by adding an offset to the solid.
Figure 3 is a schematic block diagram of a wipe generator of a vision mixer comprising a solid generator, a clip element, a gain element, a limiter and a mixer which mixes video sources X and Y in dependence upon the keying signal K.
The solid generator produces a solid, for example a ramp as shown in Figure 2A.
The clip element applies an offset to the ramp to vary the intersection of the ramp with the clip plane CP as shown in Figures 2A to 2C. Gain is applied to the offset ramp, in the gain element and the result limited in the limiter to produce the signal K. The amount of gain applied may be varied as shown in Figure 2B: that varies the slope of the transition between the limit values of the keying signal K.
The mixer mixes the video sources X and Y according to KX + (1-K) Y.
This is K=1, the output is X, if K=0 the output is Y.
If the gain applied to the solid is unity and the clip offset is zero, the solid and the keying signal are identical.
It is desired to produce new solids for the production of new wipe effects.
According to the present invention, there is provided a signal generator comprising a first input for receiving a first solid A, a second input for receiving a second solid B, an input for receiving a control signal k, and means for combining the first and second solids as a function g (k) of the control signal.
The effect is to change the shape of the solid at the same time as the control signal changes.
In a preferred embodiment of the invention the function is: g (k) =f (k) *A + (1-f (k)) *B, where 0 < K < 1.
In embodiments of the invention : f (k) = k; f (k) is a linear function of k; f (k) is a nonlinear function of k; or f (k) is a discontinuous function of k.
In a preferred embodiment of the invention, k is a clip level control signal which causes a wipe to occur. The shape of the solid thus changes with the progression of the wipe.
For a better understanding of the present invention, and to show how the same may be carried into effect, reference will now be made, by way of example, to the accompanying drawings in which: Figure 1 illustrates a wipe; Figure 2 illustrates a solid together with a clip level; Figure 3 is a schematic block diagram of a known vision mixer; Figure 4 is a diagram illustrating a solid together with a clip level ; Figure 5 is a block schematic diagram of an illustrative ramp generator; Figure 6 illustrates negating a ramp coefficient; Figure 7 illustrates examples of limiting the value of the ramp signal ; Figure 8 is a block diagram of a solid generator system; Figures 9A to E are diagrams illustrating absolutely, negating, lift and combining operations; Figure 10 is a block diagram of a ramp combiner; Figure 11 is a block diagram of a non-additive mixer of the combiner of Figure 10; Figure 12 is a schematic block diagram of a solid generation system according to an embodiment of the invention; Figure 13 is a schematic block diagram of a circuit for implementing the mixing function of the mixing stage of Figure 12; and Figure 14 illustrates in simplified form a possible wipe effect.
Reference will first be made to Figures 12,13 and 14 which illustrate an embodiment of a solid generation system according to the present invention. Then reference will be made to Figures 4 to 11 which describe examples of the solid generators of the system of Figure 12.
Referring to Figure 12, a solid generation system comprises first and second solid generators 120 and 121 which produce solids A and B. Examples of solids are a box solid and a triangular pyramid. A solid combiner 122 combines the two solids according to the function g (k) =f (k) *A + (1- (f (k)) *B, where k is a control signal for example the clip level which is applied to a key generator 123. The following assumes K is the clip level control signal. The clip level control signal K is produced by a wipe control 125 such as a potentiometer. A function generator 129 converts the clip level control signal k to a function f (k).
An example of the combiner is shown in Figure 13. The combiner implements the equation k (a-b) + B, which equals kA+ (1-k) B, because that equation requires only one multiplication. The combiner comprises an adder 126 which subtracts B from A, a multiplier 127 which multiplies the output of the adder 126 by k and another adder 128 which adds B to the output of the multiplier 128.
In the following example of the invention f (k) = k and k varies continuously and monotonically. Figures 12,13 and 14 will be described on the assumption that f (k) = k.
As shown in figure 14 if the wipe begins with k=1, only the solid A, the box solid, is output. The solid A is fed to the generator 123 with the level k=1 and in this example the arrangement is such that a wipe begins with a small square. As k reduces from 1 towards 0 the square increases in size, i. e. the wipe progresses, but at the same time the solids A and B are combined so that at some intermediate point in the wipe the solid is a combination of the square and the triangle defined by the pyramidal solid B. When k = 0 the solid comprises only the triangle.
As discussed above f (k) may be a non-linear or alternatively a discontinuous function of k. The function generator may comprise one or more look-up tables stored in a ROM 130 to define the function f (k). If more than one function is stored a select address is provided to the ROM to select the desired function. An example of a nonlinear function is a sine function. An example of a discontinuous function is a function which alternately selects A and B as the wipe progresses although such a function may result in an image which is very uncomfortable to watch.
The solid generators of Figure 12 may each comprise a plurality of ramp generators and a combining means as described with reference e to Figure 8. An example of a ramp generator is shown in Figure 5.
The ramp generator of Figure 5 produces a solid according to the equation R=Ah+Bv+C where A, B, and C are selectable coefficients, v is line number and h is pixel position along a line. The equation defines a three dimensional ramp R in three dimensional space as shown by way of example in Figure 4. The ramp value R is calculated from A, B and C individually for each pixel h on each line y. The values are represented by signed numbers, preferably twos complement numbers. As will be explained in more detail hereinafter, the value of h ranges from 0 to n and the value of v ranges from 0 to m.
The lines v of a field or frame over which the ramp is produced are selectable and the pixels h within those lines are also selectable provided the lines ~ are a contiguous set of lines and the pixels h are a contiguous set of pixels. The ramp may be generated in a field or in a frame. For ease of explanation the following description is based on the assumption that a progressively scanned frame is used.
The ramp values R can range from a negative maximum value-M through zero to a positive maximum value +M. The dynamic range DR of a ramp is such that the ramp may effectively be much larger in area than the area of an active frame of a video.
Referring to Figure 4 lines v of a whole progressively scanned TV frame are shown numbered 0,1,2... m. Pixel positions h of whole lines are shown as 0 to m. An illustrative ramp R is shown which is offset from a reference plane RP at-M by C.
By way of initial and simplified explanation a clip plane represented by plane CP is shown in Figure 4 intersecting the ramp R along a line L. The position at which the ramp intersects the clip plane CP is defined by the offset C. On line v=0 the ramp has slope A. For pixel h = 0 on lines v, the ramp has slope B. The transition region of the keying signal K occurs along the line L. Where K exceeds the clip plane CP video from one source Y forms part of a displayed image and where K is equal to or less than the clip plane video from another source X forms the other part of the displayed image, as described above with reference to Figures 1 and 3.
The solid generator of Figure 5 comprises registers R1 (INC A), R2 (INC B) and R3 (Start C) for storing preselected values of the coefficients A, B and C. The registers Rl, R2 and R3 are coupled to an increment selector SEL1 which selectively couples the registers RI to 3 to an adder 1 via a register REG1 which is clocked by a pixel rate clock signal HFCK~SYS. Feedback registers FB 1 and FB2 are coupled to another, feedback selector SEL2 which selectively connects the feedback registers FB 1 and 2 and an input of ZERO to the adder 1. The output of the adder is connected to an output register REG2 also clocked by the pixel clock HFCK~SYS. The registers R1 to 3 and FB1 and FB2 and the selectors SEL1 and 2 are controlled by a real-time controller which receives line pulses IPH and frame pulses IPV and the clock HFCK~SYS and produces IncSel and AccSel signals for controlling the selectors SEL 1 and 2. The controller also controls the loading of the coefficients A, B and C into the registers R 1 to R3.
A computer 6 generates the coefficients A, B and C and control data for each frame, in advance of the frame, and provides the coefficients and the control data to the real-time controller 2. The controller 2 feeds the coefficients to the registers R1, R2, R3.
The computer 6 acts as an interface between operator controls and the controller 2. It generates the coefficients A, B and C in accordance with the setting of the controls by the operator.
The generator operates as follows with reference to Figure 4. The basic principe is that the adder 1 adds an increment from one of the registers R1 to R3 to an accumulated value stored in one of the registers FB 1 and FB2 and feeds the sum back to one of the registers FB 1, FB2 for addition to another increment.
Referring to Figure 4, assume for ease of description that a ramp R is to start at pixel h=0 of line v=0 with an offset C and coefficients A and B. Assume A, B and C are loaded into the registers R1 to R3 once per frame. The controller, on receiving a frame start pulse IPV indicating the start of the active lines of a frame, causes selector SEL1 to select the value C in register R3 and feed it to the adder 1 via the register REG1 on a first HFCK~SYS pulse. At the same time, the selector SEL2 selects the value ZERO and feeds it to the adder 1. The sum C+0 is fedback to the registers FB 1 and FB2 and stored in both of those registers. The sum is also fed to the output register REG2 for outputting on the next HFCK~SYS pulse coefficient (A) is selected from register R1 by selector SEL1, and FBI is selected from by selector SEL2. Register FBI now accumulates successive increments of C+hA along line v=0 for h=0 to n. At the end of the line the store FBI contains C+nA. Pulse IPH,indicating the beginning of a new line, occurs and increment B is selected from register R2 by selector SEL1, and selector SEL2 selects the content C of register FB2. Coefficient B from register R2 and C from FB2 are added in adder 1 to produce a new sum B+C which is fed back to both registers FBI and FB2.
Thus both contain the ramp value B+C for the beginning of line v=l at position h=0.
The selector SEL2 selects register FBI which now accumulates C+B+hA for h=0 to n along line v=1 until the end of the line when the next IPH pulse occurs. At the end of line v=1 the register FB 1 contains C+B+nA. The selectors again select coefficient B in register R2 and register FB2 to increment the contents of FBI and FB2 to C+2B at the beginning of line v=2. Register FBI then accumulates by A along line v=2 until pulse IPH occurs and registers FBI and 2 are again incremented by coefficient B. The process repeats line by line until the next pulse IPV occurs indicating the end of the frame and the beginning of the next frame. The whole process repeats for each frame.
It will be appreciated that the ramp is built up pixel by pixel in synchronism with the clock signals HFCK~SYS.
The foregoing description assumes that the ramp occupies a whole frame. A ramp may occupy only a part of a frame as will be described with reference to Figures 29 to 39, for example.
Inverted Ramps The foregoing description describes ramps in which the value R of the ramp is successively incremented i. e. increased for each addition of a coefficient A or B. The generator of Figure 5 allows a ramp value to be successively decremented to produce an inverted ramp. This is done using a negate circuit 3, comprising an EXOR circuit and the register REG1, and which negates the increments held in the registers R1 to R3 after selection by the selector SEL1. The increments are in 2s complement form. Negating a 2s complement number is done by inverting the bits of the number and adding one. The EXOR circuit inverts the bits of the selected increment in response to a negate control bit negCtrl and the negate control bit is fed into the register REG1 as a carry bit to add one.
Thus as shown in Figure 6A for a one dimension of a ramp 60, a positive ramp 60 is produced in the manner described above upto a desired maximum level and then as shown in figure 6B it is successively decremented using the negated increments. The operation of the ramp generator is otherwise unchanged. The negate control bit neg Ctrl is provided by the controller. It is possible to produce an inverted ramp over a frame by negating the coefficient A and/or B.
Umitins Ramps.
In order to prevent over or under flow, a limiter 4 is provided in the feedback path from the adder to the feedback registers FBI and FB2. Another limiter 5 is provided at the output of the generator. Referring to Figure 7 this output limiter 5 may limit a positive extreme ramp value to a positive limit or a negative limit as shown in Figure 7a and 7b or limit a negative extreme value to either a negative or a positive limit as shown in Figures 7c and d. The limiter is controlled by the controller to select the desired limiting property.
Effects of VarYing A, B and C Increment A defines the slope of the ramp in the line direction. Increment B defines the slope of the ramp in the frame direction, perpendicular to the line direction.
A and B together can have the effect of rotating the ramp in space if they are scaled differently. C offsets the ramp in a direction perpendicular to the line and frame directions. C has the effect of shifting the intersection of the ramp with the clip plane.
By varying C the position of a ramp can be moved in a frame.
Example of a Solid Generation System Combining Ramps Referring to Figure 8, there is shown a simplified block diagram of a solid generation system. The generation system comprises a plurality of ramp generators 80 as described for example with reference to Figures 5 to 7. The system of Figure 8 has only two, ramp generator (and only one is shown) but there may be many more, for example 8 ramp generators. The ramps are combined in a combiner 86. In the combiner, the ramps are combined in a manner defined by control signals.
Each ramp generator produces a ramp which may be'edge modulated'81 as described with reference to Figures 12 to 15. The ramp may also be subject to absoluting, negating, offsetting and limiting as indicated by blocks 82 to 85. A"box solid"produced by combining two absolute ramps will be described with reference to Figures 9,10 and 11. Ramps may be combined in the combiner 86 as will be described with reference to Figure 10. The level and scale of the solids relative to the clip plane may be adjusted by an adjuster 89. A solid selector 87 selects the solid from the combiner 86 or a solid generated externally.
It will be appreciated that the system of Figure 8 is illustrative only. The techniques of ramp generator, edge modulation and solid modulation, may be used in other solid generator systems as will also be described hereinbelow.
The system is controlled by a controller 802. The controller 802 stores and implements algorithms which define wipe patterns which are selected by a control panel 803.
Figure 9A shows a single ramp which has a dynamic range of-M through to zero to +M. The ramp is represented by (signed) twos complement numbers. An absolute function (82), in known manner, transforms all the numbers representing the ramp to positive numbers, thus producing a ramp as shown in Figure 9B. The ramp of Figure 9B may be negated 83 as shown in Figure 9C, i. e. it is represented by negative numbers.
The absolute ramp may be subject to an offset 84 by adding a fixed value to the ramp.
Figure 9D shows the negated, absolute ramp of Figure 9C with an offset. The ramp of Figure 9B may be offset in similar manner.
In general a ramp may be modified by any one or more of absoluting, negating and offsetting. Figure 9E shows, as an example of a solid, a"square"solid, which is a rectangular pyramid formed by combining two ramps shown in Figure 9D, one ramp being at right angles to the other.
An example of a preferred combiner is shown in Figure 10. Two ramps A and B (which may be modified by the processing circuits 81 to 85) are fed to a selector 96 having inputs 0 to 3. Input 0 receives ramp A. Input 1 receives ramp B. Input 2 receives a first combination of the ramps from a first combining circuit 97 and a divide by-2 circuit 98. Input 3 receives a second combination of the ramps from a second combining circuit 99. The one of the inputs 0 to 3 to be coupled to the output of the selector is selected by a two bit selection signal SEL. The output of the selector 96 is coupled to the output of the combiner 93 via another selector 100 which selects the output of the selector 96 or zero according to a zero select signal. If the select signal SEL is 0 or 1, ramp A or B is passed to the output unmodified. The combiner 93 then acts as a switch or signal router.
The first ramp combining circuit comprises an adder 97 and a divide by two circuit 98. The divide by two circuit has a control input for receiving a divide-by-2 control signal. The divide-by-2 control signal selectively actuates the divide-by-2 circuit 98. Thus input 2 of the selector 96 receives either (A+B) or (A+B)/2.
The second ramp combining circuit 99 is a Non-Additive Mixer also known as a NAM an example of which is shown in Figure 11. Referring to Figure 11, the NAM comprises first second and third selectors 101 102 and 103 and a comparator 104. The comparator compares the instantaneous values of the ramps A and B. If A > B then it outputs logic 0 otherwise it outputs logic 1. The first and second selectors select input 0 or 1 according to the output of the comparator. The third selector selects the first or second selector according to the value of a POS/NEG signal. The overall truth table of the NAM is: COMPARISON OF RAMPS POS/NEG OUTPUT OF NAM A > B POS A B > A POS B A > B NEG B B > A NEG A For POS/NEG POS, the NAM outputs whichever of A and B is greater at any moment in time, i. e. at any pixel position. For POS/NEG NEG the NAM outputs whichever of A and B is smaller.
Overall, the combiner 93 selects one of the ramps A and B, an additive combination of the ramps, a non-additive combination of the ramps or zero.
Box Solid A'box solid'is a well known solid. Referring to Figures 9,10 and 11, it may be produced by absoluting two ramps at right angles to each other and combining them using a negative NAM function. The result is a square pyramid as shown in Figure 9E.
Another solid may be produced using a positive NAM function. Other solids can be produced using the add function.

Claims (19)

  1. CLAIMS 1. A signal generator comprising a first input for receiving a first solid A, a second input for receiving a second solid B, an input for receiving a control signal k, and means for combining the first and second solids as a function g (k) of the control signal.
  2. 2. A generator according to claim 1, wherein the function is: g (k) =f (k) *A + (1-f (k)) *B, where 0 < Ksl.
  3. 3. A generator according to claim 2, wherein f (k) = k.
  4. 4. A generator according to claim 2, wherein f (k) is a linear function of k.
  5. 5. A generator according to claim 2, wherein f (k) is a non-linear function of k.
  6. 6. A generator according to claim 2, wherein f (k) is a discontinuous function of k.
  7. 7. A generator according to any preceding claim further comprising a key generator for generating a key from the combined solids.
  8. 8. A generator according to any preceding claim, comprising means for producing the control signal K.
  9. 9. A generator according to any preceding claim, comprising means for producing the solids A and B.
  10. 10. A generator according to claim 9, wherein each solid producing means comprises a plurality of ramp generators and means for combining the ramps produced by the generators.
  11. 11. A generator according to claim 10, further comprising means for modifying the ramps before they are combined.
  12. 12. A generator according to claim 10 or 11 wherein each ramp generator produces a video ramp signal R for each pixel of a predetermined set of pixels where h=0 to n of each of a predetermined set of video lines v where v= 0 to m, wherein R=Ah+Bv+C where A, B, and C are coefficients each having a magnitude equal to or greater than zero.
  13. 13. A generator according to claim 12, wherein each ramp generator comprises means for storing the coefficients A, B, and C and first and second accumulated values, adding means for incrementing the first accumulated value by A and the second accumulated value by B, and control means by which, for each of the said lines v, the second accumulated value is incremented by the adding means by B to form C+Bv which is stored as both the first and the second accumulated values, and for each pixel of the said set of pixels on each of the said lines the first accumulated value is incremented by the adding means to form C+Bv+Ah which is stored as the first accumulated value and is output as R.
  14. 14. A generator according to claim 13, wherein the storing means comprises coefficient registers for storing respective ones of A, B and C and feedback registers for storing the first and second accumulated values, and means for selectively coupling the registers to the adding means and for storing the output of the adding means in at least one of the feedback registers.
  15. 15. A generator according to claim 14, wherein the control means comprises selecting means for selectively couplina the registers to the adding means, and the output of the adding means is coupled to the feedback registers, the control means selectively enabling the registers to store the accumulated values.
  16. 16. A generator according to claim 13,14, or 15, wherein the coefficients are signed numbers and wherein each ramp generator further comprises means for selectively inverting the sign of the coefficients before application to the adding means.
  17. 17. A generator according to claim 12,13,14,15 or 16, wherein each ramp generator comprises means for selectively limiting the value of the ramp signal R
  18. 18. A generator according to claim 12,13,14,15,16 or 17 wherein each ramp generator comprises means for selecting the values of the coefficients A, B and C.
  19. 19. A signal generator substantially as hereinbefore described with reference to Figures 12 and 13 optionally together with Figures 4 to 11 of the accompanying drawings.
GB9908241A 1999-04-09 1999-04-09 Signal generator Expired - Fee Related GB2348766B (en)

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Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5608465A (en) * 1994-01-28 1997-03-04 Scitex Im Acquisition Corp. Video mixer control signal generator modular element

Patent Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5608465A (en) * 1994-01-28 1997-03-04 Scitex Im Acquisition Corp. Video mixer control signal generator modular element

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GB2348766B (en) 2003-12-17
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