GB2347533B - A method and apparatus for interfacing a device compliant to first bus protocol to an external bus - Google Patents

A method and apparatus for interfacing a device compliant to first bus protocol to an external bus

Info

Publication number
GB2347533B
GB2347533B GB0014623A GB0014623A GB2347533B GB 2347533 B GB2347533 B GB 2347533B GB 0014623 A GB0014623 A GB 0014623A GB 0014623 A GB0014623 A GB 0014623A GB 2347533 B GB2347533 B GB 2347533B
Authority
GB
United Kingdom
Prior art keywords
bus
interfacing
device compliant
protocol
external bus
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
GB0014623A
Other versions
GB0014623D0 (en
GB2347533A (en
Inventor
Byron Gillespie
Marc Goldschmidt
Terry Sych
Bruce Young
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Intel Corp
Original Assignee
Intel Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Priority claimed from US08/580,130 external-priority patent/US5751975A/en
Application filed by Intel Corp filed Critical Intel Corp
Publication of GB0014623D0 publication Critical patent/GB0014623D0/en
Publication of GB2347533A publication Critical patent/GB2347533A/en
Application granted granted Critical
Publication of GB2347533B publication Critical patent/GB2347533B/en
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/10—Program control for peripheral devices
    • G06F13/105—Program control for peripheral devices where the programme performs an input/output emulation function
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/38—Information transfer, e.g. on bus
    • G06F13/40—Bus structure
    • G06F13/4004—Coupling between buses
    • G06F13/4027—Coupling between buses using bus bridges
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/38—Information transfer, e.g. on bus
    • G06F13/40—Bus structure
    • G06F13/4004—Coupling between buses
    • G06F13/4027—Coupling between buses using bus bridges
    • G06F13/404—Coupling between buses using bus bridges with address mapping

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • General Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Bus Control (AREA)
GB0014623A 1995-12-28 1996-12-27 A method and apparatus for interfacing a device compliant to first bus protocol to an external bus Expired - Fee Related GB2347533B (en)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US08/580,130 US5751975A (en) 1995-12-28 1995-12-28 Method and apparatus for interfacing a device compliant to a first bus protocol to an external bus having a second bus protocol and for providing virtual functions through a multi-function intelligent bridge
GB9812475A GB2324182B (en) 1995-12-28 1996-12-27 A method and apparatus for interfacing a device compliant to first bus protocol to an external bus

Publications (3)

Publication Number Publication Date
GB0014623D0 GB0014623D0 (en) 2000-08-09
GB2347533A GB2347533A (en) 2000-09-06
GB2347533B true GB2347533B (en) 2000-11-08

Family

ID=26313832

Family Applications (3)

Application Number Title Priority Date Filing Date
GB0014628A Expired - Fee Related GB2347535B (en) 1995-12-28 1996-12-27 A method and apparatus for interfacing a device compliant to first bus protocol to an external bus
GB0014627A Expired - Fee Related GB2347534B (en) 1995-12-28 1996-12-27 A method and apparatus for interfacing a device compliant to first bus protocol to an external bus
GB0014623A Expired - Fee Related GB2347533B (en) 1995-12-28 1996-12-27 A method and apparatus for interfacing a device compliant to first bus protocol to an external bus

Family Applications Before (2)

Application Number Title Priority Date Filing Date
GB0014628A Expired - Fee Related GB2347535B (en) 1995-12-28 1996-12-27 A method and apparatus for interfacing a device compliant to first bus protocol to an external bus
GB0014627A Expired - Fee Related GB2347534B (en) 1995-12-28 1996-12-27 A method and apparatus for interfacing a device compliant to first bus protocol to an external bus

Country Status (1)

Country Link
GB (3) GB2347535B (en)

Families Citing this family (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6823418B2 (en) * 2001-06-29 2004-11-23 Intel Corporation Virtual PCI device apparatus and method
US20090157949A1 (en) * 2007-12-18 2009-06-18 Leibowitz Robert N Address translation between a memory controller and an external memory device

Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5548730A (en) * 1994-09-20 1996-08-20 Intel Corporation Intelligent bus bridge for input/output subsystems in a computer system

Family Cites Families (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5446869A (en) * 1993-12-30 1995-08-29 International Business Machines Corporation Configuration and RAM/ROM control of PCI extension card residing on MCA adapter card
US5608876A (en) * 1995-05-22 1997-03-04 International Business Machines Corporation Add-in board with enable-disable expansion ROM for PCI bus computers

Patent Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5548730A (en) * 1994-09-20 1996-08-20 Intel Corporation Intelligent bus bridge for input/output subsystems in a computer system

Also Published As

Publication number Publication date
GB0014627D0 (en) 2000-08-09
GB2347535A (en) 2000-09-06
GB0014628D0 (en) 2000-08-09
GB2347534B (en) 2000-11-08
GB0014623D0 (en) 2000-08-09
GB2347535B (en) 2000-11-08
GB2347534A (en) 2000-09-06
GB2347533A (en) 2000-09-06

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Legal Events

Date Code Title Description
PCNP Patent ceased through non-payment of renewal fee

Effective date: 20151227