GB2347524A - Matched reference current sources - Google Patents

Abstract

Circuit 8 provides matched currents I1 and I2 to the inputs of a compound current mirror circuit 7 which has plural outputs OUT1 -OUTN. Operational amplifier OP5 and first MOS transistor M70 provide a first output current I1 in dependence on the input voltage VREF5 and the value of the resistance RREF3. Second MOS transistor M71 receives the same gate voltage as the first transistor M70. Voltage follower OP6 drives the source of the second transistor to equal the voltage of the source of the first transistor. Because the gate-source voltages of the transistors M70 and M71 are equal, the output currents I1 and I2 are matched.

Description

2347524 High Precision Current Output Circuit This application is a

divisional Of GB 2 308 031 (9623438.0) The present invention relates to a high precision current output circuit, more particularly a current amplification circuit, a reference current generation circuit and a voltage/current conversion circuit.

The current output circuit according to the present invention is preferably applied to a case where a current mirror circuit operates at a low input/output voltage.

As a current amplification circuit for supplying an output current in proportion to an input current, a current mirror circuit has been used. If a high, precision current - is needed, the current mirror circuit in a cascade form has been employed to obtain a high output resistance.

The explanation about a conventional cascade current mirror circuit is provided hereinafter, by referring to the drawings.

Fig.1 is a circuit diagram showing a structure of 2 a conventional cascade current mirror circuit.

In this f igure, M100 through M103 indicate N channel MOS transistors. The N-channel MOS transistors M100 and M102 configure a current mirror circuit of a first stage, while the N-channel MOS transistors M101 and M103 configure a current mirror circuit of a second stage. The current mirror circuit of the first stage and the current mirror circuit of the second stage are connected in tandem.

By inputting a reference current Iref to a drain of the N-channel MOS transistor M100, an output current Io is output to a drain of the N-channel MOS transistor M102. In this case, a value of a gate voltage of the N-channel MOS transistor M103 results in Vth + a, and a value of a gate voltage of the Nchaxinel MOS transistor M102 results in 2(Vth+a).

Vth is a value of threshold voltage of the Nchannel MOS transistors M100 through M103, and a i4s a value obtained by subtracting the value of threshold voltage Vth f rom. a voltage between a gate and a source VGS of the N- channel MOS transistors M100 through M103(on the condition that a drain current "ID" is equal to the input reference current Iref).

Fig.2 shows the relationship between an output voltage Vo and an output current Io. If a value of the I 3 output voltage Vo "is equal to or less than 2cx, the Nchannel MOS transistors M102 and M103 operate in a non-saturation region (triode region). If the value of the output voltage Vo is between 2a and Vth--2a, -,he N-channel MOS transistor M102 operates in a nonsaturation region, and the N-channel MOS transistor M103 operates in. a saturation region (pinch-off region). If the value of the output voltage Vo is equal to or greater than Vth+2a, the N-channel MOS transistors M102 and M103 operate in the sauration region.

That is, if the value of the output voltage Vo is equal to or greater than Vth+2a, a slope of a Vo-Io curve is very small, so that an output resistance can be significantly increased in order to obtain a high precision output current Io.

Provided next is the explanation about a conventional compound current mirror circuit, b"y referring to the drawings.

Fig.3 is a circuit diagram showing a structure o f the conventional compound current mirror circuit.

In this figure, M110 through M114 indicate N channel MOS transistors. A proportion "W/L" of gate length to gate width of the N-channel MOS transistor M110 is one fourth of a proportion "W/L" of gate 4 length to gate width of the N-channel MOS transistors Mlll through M114.

A drain terminal of the N-channel MOS transistor M110 is connected to an outout side of a first input current I1, and a gate terminal of the N-channel MOS transistor M110 is connected to the drain terminal of the N-channel MOS transistor M110. A source terminal of the N-channel MOS transistor M110 is connected to a ground GND.

A drain terminal of the N"channel MOS transistor M111 is connected to an output side of a second input current 12, and a gate terminal of the N-channel. MOS transistor M111 is connected to the gate terminal of the N-channel MOS transistor M110.

A drain terminal of the N-channel MOS transistor M112 is connected to a source terminal of the Nchannel MOS transistor M111, and a gate terminal of the N-channel MOS transistor M112 is also connectecT to the output side of the second input current 12. A source terminal of the N-channel MOS transistor M112 is connected to the ground GND.

A drain terminal of the N-channel MOS transistor M113 is connected to an output terminal, and a gate terminal of the N-channel MOS transistor M113 is connected to the gate terminal of the N-channel. MOS I I r __ transistor M111.

A drain terminal of the N-channel MOS transiszor M114 is connected to a source terminal of the channel MOS transistor M113. A gate terminal of N-channel MOS transistor M114 is also connected to output side of the second input current 12, and a source terminal of the N-channel MOS transistor M114 is connected to the ground GND.

By supplying the input currents Il and 12 to the drains of the N-channel MOS transistors M110 and M 111 respectively, an output current Io is output to the drain of the N- channel MOS transistor M113.

In this -case, a voltage VGS' between a gate and a source of the Nchannel MOS transistor M110 resulzs in Vth+2a according to the following calculation.

Assume that a voltage between a gate and a source of the N-channel MOS transistors M111 ti-irouzh M114 is VGS, and the proportion W/L of gate length to gate width of the N-channel MOS transistor M110 -is c:e fourth of the proportion W/L of 'gate length to ge---width of the N- channel MOS transistors Mlll throu:-h M114. Therefore:

K - k - W/L (VGS' - Vth)z = K - W/L (VGS - Vth)z 6 is obtained. Accordingly, (VGS' - Vth)2 4(VGS - Vth)2 5 As a result, VGS' = Vth + 2(VGS - Vth) = Vth + 2a In the above described equations, K is a constant and Vth is a threshold voltage of the N-channel MOS transistors M110 through M114.

As a result, a gate voltage of the N-channel MOS 'transistors Mlll and M113 results in Vth + 2a.

Since a gate voltage of the N-chaxmel MOS transistors M112 and M114 results in Vth+a, the N- channel MOS transistors M113 and M114 operate in a saturation region when the value of the output voltage Vo is equal to or greater than 2a as shown in Fig. 47.' In addition, a voltage on the input current Il side which requires a higher v oltage at an input terminal results in Vth+ 2a.

Accordingly, input and output voltages required f or operating in a highresistance region become lower than those of the cascade current mirror circuit shown in Fig.13, by the value of the threshold voltage.

I 7 To obtain a high precision current using a conventional cascade current mirror circuit, the circuit must operate at the input voltage equal to or higher than 2(Vth+a), and at the output voltage Vo equal to or higher than Vth+2a. Since the range of the voltages where a high precision current can be obtained is narrow, the conventional cascade current mirror circuit is sometimes unavailable in a low voltage power supply circuit.

To return a current, for example, by connecting an output of the N-channel cascade current mirror circuit and an input of a P-channel cascade current mirror circuit, a voltage whose value is equal to. or greater than 2(Vth,, + a,) + (Vthp + 2ap) is required.

If VthN Vthp = iv, C'N = al 0 - 1VI the conventional circuit cannot be used at a power supply voltage of 3.3V.

In the above described equations, Vth, is a threshold Voltage of an N-channel MOS transistor, and Vth, is a threshold voltage of a P-channel MOS transistor. cr, is A value obtained by subtracting the threshold voltage VtN from a voltage VGS between a gate and a source of the N-channel MOS transistor (on the condition that the drain current ID is equal to 8 the input current Iref). a, is a value obtained by subtracting the threshold value Vth. from the voltage VGS between the gate and the source of the P-channel MOS transistor (on the condition that the drain current ID is equal to the input current Iref)- The conventional compound current mirror circuit operates at a voltage lower than that of a cascade current mirror circuit, but two input currents 11 and 12 are required. Specifically, to generate an initial reference current in an IC, how to generate these two input currents 11 and 12 is a problem.

- If back gates of the N-channel MOS transistors mill and M113'included in the compound current mirror circuit are connected to a ground GND, the threshold voltage of the N-channel MOS transistors Mill and M113 is higher than that of the N-channel MOS transistors M110, M112, and M114. An electric potential of a drain of the N-channel MOS transistor M112 becomes lowepr' than the voltage a and cannot operate in a saturation region, in this case, so that a relative precision of the input and output currents is significantly degraded.

An embodiment of the present invention can I 9 provide a current amplification circuit that can operate with high precision at low input/output voltages.

other embodiments of the present invention can provide a reference current generation circuit which can generate a plurality of currents with high precision, and a voltage/current conversion circuit.

According to a first aspect of the present invention, there is provided a reference current generation circuit, comprising: a first reference current generation circuit for generating a first reference current by inputting a result of a comparison between a source potential of a first transistor and a reference voltage, to a gate of the first transistor; and a second reference current generation circuit for generating a second reference current by inputting the reference voltage to a source of a second transistor via a voltage follower, and inputting the result of the comparison to a gate of the second transistor.

According to a second aspect of the present invention, there is provided a current - amplification circuit, comprising: means for supplying a first reference current generated by inputting a result of a comparison between an electric potential of a source of a first transistor and a reference voltage to a gate of the first transistor, to a first current input terminal of a compound current mirror circuit; and means for supplying a second reference current generated by inputting the reference voltage to a source of a second transistor via a voltage follower, and inputting the result of the comparison to a gate of the second transistor, to a second current input terminal of the compound current mirror circuit.

According to a third aspect of the present invention, there is provided a voltage/current - conversion circuit, comprising: a first transistor whose source is connected to a voltage input terminal via a resistance element, and whose gate is connected to an output terminal of a first operational amplifier to which a reference voltage is input as a non-inverting input and a voltage of the source of the first transistor is input as an inverting input; and a second transistor whose source is connected to an output terminal of a second operational amplifier to which the reference voltage is input as a non-inverting input, and an output voltage is input as an inverting input, and whose gate is connected to the output terminal of the first operational amplifier.

In the above-recited reference current generation circuit, the result of a comparison between a voltage of a source and a reference voltage is input to a gate of the first transistor, the reference voltage is input to a source of the second transistor via a voltage' follower, and the result of the I .. /--I-- comparison is input to its gate. As a result, supplying only one reference voltage allows output of a plurality of high precision reference currents In an embodiment of the present invention, the first reference current generated by inputting the result of the comparison between the voltage of the source of the first transistor and the reference voltage to the gate of the first transistor, is supplied to the first current input terminal of the current amplification circuit, as recited above, the reference voltage is input to the source of the second transistor via a voltage follower, and the second reference current generated by inputting the result of the comparison to the gate of the second transistor, is supplied to the second current input terminal of the current amplification circuit as recited above. As a result, supplying only one reference voltage allows output of a plurality of high pfecision reference currents at a low output voltage.

According to a further embodiment, the first reference current generated by inputting to the source of the second transistor the result of the comparison between the voltage of the source of the first transistor and the reference voltage is supplied to the second current input terminal of the compound current mirror circuit, the reference voltage is input to the source of the second transistor via a voltage follower, and the second reference current generated by inputting the result of the comparison to the gate of- the second transistor is supplied to the second current input terminal of the compound current mirror circuit. As a result, supplying only one reference voltage allows output of a plurality of high precision reference currents at a low output voltage.

According to a still further embodiment, the source of the first transistor is connected to a voltage input terminal via a resistance element, its gate is connected to an output terminal of a first operational amplifier to which a reference voltage is supplied in a non-inverting input and the voltage of the source is supplied in an inverting input, a source of the second transistor is connected to an output terminal of a second operational amplifier to which the reference voltage is supplied in a non-inverting input and an output voltage is supplied in an inverting input, and its gate. is connected to the output terminal of the first operational amplifier. As a result, supplying only.one I 13 reference voltage allows output of a plurality of high precision reference currents.

Reference is made, by way of example, to the accompanying drawings in which Fig. 1 is a circuit diagram showing a structure o'Z a conventional cascade current mirror circuit; Fig-2 is shows voltage/current characteristics of the conventional cascade current mirror circuit; Fig.3 is a circuit diagram showing a con. ventional compound current mirror circuit; 14 Fig. 4 shows voltage/current characteristics of the conventional compound current mirror circuit; Fig. 5 is a circuit diagram showing a structure of a current mirror circuit which may be employed in the present invention; Fig. 6 shows voltage/current characteristics of the current mirror circuit of Fig. 5; Fig. 7 is a circuit diagram showing a structure of another current mirror circuit; Fig-8 is a circuit diagram showing a structure of further current mirror circuit; is Fig.9 is a circuit diagram showing a structure of still further current mirror circuit; Fig.10 is a block diagram showing a structure of reference current generation circuit to which the present invention may be applied; Fig-11 is a circuit diagram showing a structure of a reference current generation circuit embodying the present invention; Fig.12 is a circuit diagram showing a structure of Ying another reference current generation circuit embod%i I /-1 P - the present invention; Fig. 13 is a circuit diagram showing a structure of further reference current generation circuit embodying the present invention; Fig. 14 is a circuit diagram showing a structure of voltage/current conversion circuit embodying the prese nt invention; Fig.15 is a circuit diagram showing a structure of another voltage/current conversion circuit embodying the present invention; and Fig.16 is a circuit diagram showing a structure of a further voltage/current conversion circuit embodying the present invention.

First, there will be described various current mirror circuits which may be employed in an embodiment of the present invention.

Fig.5 is the circuit diagram showing the structure of a first such current mirror ci'rcuit.

In this figure, M1 through M5 indicate N-channel MOS transistors, The -proportion W/L of gate length to gate width of each of the N-channel MOS transistors Ml through M5 is the same. Il indicates a first 16 current mirror input current, while 12 indicates a second current mirror input current. A value of the first current mirror input current Il is equal to that of the current mirror input current 12. DO indicazes a voltage drop device. It is desirable that a value of voltage drop VDO produced -by the voltage drop device DO is set to a value between "0" and a threshold voltage Vth of the N-channel MOS transistor Ml, and especially that the voltage drop VDO produced by the voltage drop device DO is set to a value equal to or close to the threshold voltage Vth of the Nchannel MOS transistor Ml.

A drain terminal of the N-channel MOS transistor MI is connected to an output side of the first current mirror input current Il via the voltage drop device DO. A gate terminal of the N-channel MOS transistor Ml is connected to the output side of the f irst current mirror input current Il, and a source terminal of the N- channel MOS. transistor Ml is connected to a ground GND.

Drain and gate terminals of the N-channel MOS transistor M2 are connected to an output side of the second current mirror input current 12.

A drain terminal of the N-channel MOS transistor M3 is connected to a source terminal of the N-channel I MOS transistor M2, and a gate terminal of the N- channel MOS transistor M3 is connected to an output side of the first current mirror input current Il. A source terminal of the N-channel MOS transistor M3 is connected to the ground GND.

A drain terminal of the N-channel MOS transistor M4 is connected to an output terminal, and a' gate terminal of the N-channel MOS transistor M4 is connected to the output side of the second current mirror input current 12..

A drain terminal of the N-channel MOS transistor M5 is connected to a source terminal of the N7channel MOS transistor M4, and a gate terminal of the Nchannel MOS transistor M5 is connected to the output side of the first current mirror input current 11. A source terminal of the N-channel MOS transistor M5 is connected to the ground GND. I That is, by connecting the drain terminal of the N-channel MOS transistor Ml to the output side of the first current mirror input current Il via the voltage drop device DO, supplying the first current mirror input current 11 to the gate terminals of the Nchannel MOS transistors Ml, M3, and M5, and supplying the second current mirror input current 12 to-the gate terminals of the N-channel MOS transistors M2 and M4, 18 an output current 10 is Output to the drain of the Nchannel MOS transistor M4.

Provided next is the explanation about operations performed by the current mirror circuit of Fig. 5.

This explanation is based on the assumption that the voltage drop VDO produced by the voltage drop device DO is equal to a value of the threshold voltage Vth of the-N-channel MOS transistor Ml.

In Fig.5, an electric potential of the gate of the N-channel MOS, transistor Ml (electric potential at node (1)) is equal to a voltage "VG$l" between a gate and a source of the N-channel MCS transistor M1, that is, Vth+a. Accordingly, an electric potential of the drain (electric potential at node (2)) of theN- channel MOS transistor Ml becomes lower than that of the node (1) by the threshold voltage Vth, and results in a voltage a. 91 Since an electric potential of the gate of the N- channel MOS transistor M3 is equal, to that of the gate of the N-channel MOS transistor Ml, the electric potential of the drain of the N-channel MOS transistor M3 (electric potential at node (4)) becomes equal to that of the drain of the N-channel MOS transistor M1, that is, the voltage a.

I 19 A voltage "VG82" between a gate and a source of the N-channel MOS transistor M2 is equal to the voltage "VGS1" between the gate and the source of the N-channel MOS transistor Mi, that is, Vth+a.

Accordingly, the electric potential of the gate of the N-channel MOS transistor M2 (electric potential at node (3)) results in VGS2 + a = Vth + 2a.

That is, the electric potential of the drain of the N-channel MOS transistor M5 (electric potential at node (6)) results in the voltage a, the electric potential of the drain of the N-channel MOS transistor M4 (electric potential at node (5)) results in the voltage 2a, and accordingly the minimum value of the output voltage Vo operating in a saturation region results in 2a-.

Assume that the values of the first and the second current mirror input currents Il and 12 are equal to the reference current Iref, and the voltage drop VD@ produced by the voltage drop device DO is equal to the value of the threshold voltage Vth of the N-channel MOS transistor Ml. Fig.6 shows the relationship between the output voltage Vo and the output current Io in this case. That is, the output voltage Vo is proportional to the output current Io at a- voltage equal to or lower than 2a, and becomes almost constant I I I at a voltage equal to or higher than 2a. Therefore, the output current Io equal to the reference current Iref can be obtained on the condition that the output voltage-Vo is 2a or higher.

If the value of voltage drop VDO produced by the voltage drop device DO is less than that of the threshold voltage Vth of the N-channel MOS transistor Ml, the minimum value of the output voltage Vo operating in a saturation region results in 2a + Vth - VDO.

if the value of voltage drop VDO produced by the voltage drop device DO is larger than that of the threshold voltage Vth of the N-channel MOS transistor Ml, the N-channel MOS transistor Ml operates in a non saturation region. As a result, a precision of a current mirror is degraded.

As described above, with the current mirror circuit -of Fig. 5, 91 the electric potential of the gate of the N-channel MOS transistor M4 can be set to Vth+2a, and the minimum value of the output voltage Vo operating in a saturation region can be set to 2a.

Furthermore, a voltage at the output side of the first current mirror input current. Il which- requires a higher voltage at an input terminal, results in Vth I 21 + a, which is lower than that of the cascade current mirror circuit shown in Fig. 1 by the threshold voltage Vth- A voltage required to provide a current by connecting an output of an N-channel cascade current mirror circuit and an input of a P-channel cascade current mirror circuit, results in (Vth+ 2a) + (2a), thereby lowering the required voltage by 2Vth in comparison with the cascade current mirror shown in Fig.l.

Additionally, by iftaking the voltage drop VDO produced by the voltage drop device DO equal to or less than the threshold voltage Vth, the current mirror circuit can operate in a saturation region even if the threshold voltage of the N-channel MOS transistors M2 and M4 is higher than that of the N-channel MOS transistors M3 and M5. 10.

Another current mirror circuit useful for understanding the present invention is implemented by using an N-channel MOS transistor MO as the voltage drop device DO shown in Fig.5.

22 Fig. 7 is the circuit diagram showing the structure of this current mirror circuit.

In this figure, MO through M5 indicate N-channel MOS transistors. Il indicates a first current mirror input current, while 12 indicates a second current mirror input current.

Here, a ratio between a value of the first current mirror input current 11 and a proportion "Wl/Ll" of gate length to gate width of the N-channel MOS transistor Ml, is set to be equal to a ratio between a value of the second current mirror input current 12 and a proportion "W3/L3" of gate length to gate width of the N-channel MOS transistor M3.

A ratio between the proportion "W3/L3" of gate length to gate width of the N-channel MOS transistor M3, and a proportion "W5/L5" of gate length to gate width of the MOS transistor M5, is set to be equal te a ratio between a proportion "W2/L2" of gate length to gate width of the N-channel MOS transistor M2 and the proportion "W4/L4" of gate length to gate width of the N-channel MOS transistor M4.

That is, the ratios are set as follows:

Il: (Wl/Ll) = 12: (W3/L3) I 23 (W3/L3): (W5/L5) = (W2/L2): (W4/L4) Then, a proportion "WO/LO" of gate length to gate width of. the N-channel MOS transistor MO is set, so that the voltage VDSO between a drain and a source of the N-channel MOS transistor MO is equal to or less than the threshold voltage Vth of the N- channel MOS transistor Ml. Especially, it is desirable that the value of the voltage VDSO between the drain and the source of the N-channel MOS transistor MO is set to a value equal to or close to the threshold voltage Vth of the N-channel MOS transistor Ml.

As a result, the electric potential of the drain (electric potential at node (2)) of the N-channel MOS transistor Ml can be lowered by the value of the voltage VDSO between the drain and the source of the N-channel MOS transistor MO while running the Nchannel MOS transistors MO through M5 in a saturation region, thereby outputting a high precision current at a low voltage.

Since the electric potential of the drain of the N-channel MOS transistor Ml is lowered by the value of the voltage VDSO between the drain and the source of the N-channel MOS transistor MO, the --electric potential of the drain of the N-channel MOS transistor 24 M3 (electric poten'tial at node (4)) drops by the value of the voltage VDSO between the drain and the source of the N-channel MOS transistor MO, and at the same time, the electric potential of the drain of the N- channel MOS transistor M5 (electric potential at node (6)) drops by the value of the voltage VDSO between the drain and the source of the N- channel MOS transistor MOAccordingly, the minimum value of the output voltage Vo operating in a saturation region drops by the value of the voltage VDSO 'between the drain and the source of the N-channel MOS transistor Mo.

Assume that the values of the first and the second current mirror input currents Il and 12 are equal to the value of the referepce current Iref, the voltage VDSO between the drain and the source of the N-channel MOS transistor MO is equal to the threshold voltage Vth of the N-channel MOS transistor Ml, the gatle lengths Ll through L5 of the N-channel MOS transistors Ml through M5 are the same, and the gate widths W1 through W5 of the N- channel MOS transistors Ml through M5 are the same.

In this case, the relationship between the output voltage Vo and the output current Io is like that shown in Fig.6. The output current Io equal to the I I reference current Iref can be obtained on the condition that the output voltage Vo is equal to or higher than 2a.

with. the current mirror circuit of Fig. 7 as described above, by equalizing the value of the voltage VDSO between the drain and the source of the N-channel MOS-transis,tor MO to the threshold voltage Vth of the N-channel MOS transistor Ml, the electric potential of the gate of the N-channel MOS transistor M4 can be set to Vth+2a, and the minimum value of the output voltage Vo operating in a saturation region can be set to 2a.

Furthermore, a voltage at the output side of the first current mirror input current Il which requires a higher voltage at an input terminal, results in Vth+a, which is lower than that of the cascade current mirror circuit shown in Fig.1 by the threshold voltage Vth.

If this circuit is applied to a CMOS circuit, a voltage required to return a current by connecting an output of an N-channel cascade current mirror circuit and an input of a P-channel cascade current mirror circuit results in (Vth+2a) + (2a),- thereby lowering the required voltage by 2vth in comparison 26 with the cascade current mirror circuit shown in Fig.l.

In addition, by making the voltage VDSO between the drain and the source of the N-channel mos transistor MO equal --o or lower than the thresholdvoltage Vth of the N- channel MOS transistor Ml, the current mirror circuit of Fig. 7 can operate in a saturation region even if the threshold voltage of the N- channel MOS transistors m2 and M4 is higher than that of the N-channel MOS transistors M3 and M5.

To make the voltage VDSO between the drain and the source of the Nchannel MOS transistor MO equal to-or lower than the threshold voltage Vth of the N-channel MOS transistor Ml, the proportion "WO/LO" of gate length to gate width of the N-channel MOS transistor MO, f or example, is set to be equal to or greater than the proportion "Wl/Ll" of gate length to gate width of the N- channel MOS transistor Ml.

Fig.8 is a circuit diagram showing the structure of a further current mirror circuit.

I 27 In this figure, Ml through M5 indicate N-channel MOS transistors. Il indicates a first current mirror input current, while 12 indicates a second current mirror input current. The current mirror circuit shown in Fig.8 is implemented by replacing the voltage drop device DO shown in Fig-5 with a resistance element RO.

Here, a ratio between a value of the first current mirror input current Il and a proportion "Wl/Ll" of gate length to gate width of the N-channel MOS transistor M1 is set to be equal.to a ratio between a value of the second current mirror input current 12 and a proportion "W3/L3" of gate length to gate width of the N-channel MOS transistor M3.

Then, a ratio between the proportion "W3/L3" of gate length to gate width of the N-channel MOS transistor M3 and a proportion "W5/L5" of gate length to gate width of t'he N-channel MOS transistor M5 is set to be equal to a ratio between a proportion "W2/L2" of gate length to gate width of the N-channel MOS transistor M2 and a proportion "W4/L4" of gate length to gate width of the N-channel MOS transistor m4.

A resistance value of the resistance element RO is 28 set so that a voltage VRO between terminals of the resistance element RO is equal to or lower than the threshold voltage Vth of the N-channel MOS transistor Ml. Especially, it is desirable that the value of the voltage VRO between terminals of the resistance element RO is set to be equal to or close to the threshold voltage Vth of the N.-channel MOS transistor Ml.

As a result, an electric potential of a drain of the N-channel MOS transistor Ml (electric potential at node (2)) drops by the value of the voltage VRO between terminals of the resistance element RO.

Since the electric potential of the drain of the N-channel MOS transistor Ml drops by the value of the 15- voltage VRO between terminals of the resistance element RO, the electric potential of the drain of the N-channel MOS transistor M3 (electric potential at node (4)) drops by the value of the voltage VRCI between terminals of the resistance element RO, and at the same time, the electric pot ential of the drain of the N-channel MOS transistor M5 (electric potential at node (6)) drops by the value of the voltage VRO between terminals of the resistance element RO. As a result, the minimum value of the output voltage Vo operating in a saturation region drops by the value I 29 of the voltage VRO-between terminals of the resistance element RO.

Assume that the values of the first and the second current mirror input currents Il and 12 are equal to the reference current Iref, the voltage VRO between terminals of the resistance element RO is -equal to the threshold voltage Vth of the N- channel MOS transistor Ml, gate lengths Ll through L5 of the N-channels MOS transistors Ml through M5 are the same, and gate widths Wl through W5 of the N-channel MOS transistors Ml through M5 are the same- In this case, the relationship between the output voltage Vo and the output current Io is like that shown in Fig.6. The output current Io equal to the reference current Iref can be obtained on the condition that the output voltage Vo is equal to or higher than 2a.

By equalizing the value of the vc-11tage VRO between terminals of the resistance element RO to the value of the threshold voltage Vth of the N-channel MOS transistor Ml, the electric potential of the gate of the N-channel MOS transistor M4 results in Vth+2a, and the minimum value of the output voltage operating in a saturation region results in 2aAdditionally, a voltage at an output side of the first current mirror input current Il which requires a higher voltage at an input terminal results in Vth+a, which is lower than that of the cascade current mirror circuit shown in Fig. 1 by the value of the threshold voltage Vth.

A voltage required to return a current by connecting an output of an Nchannel cascade current mirror circuit and an input of a P-channel cascade current mirror circuit, results in (Vth+2a) + (2a), which is lower than that of the cascade current mirror circuit shown in Fig.1 by 2Vth.

Furthermore, by making the voltage VRO between terminals of the resistance element RO equal to or lower than the threshold voltage Vth of the N-channel MOS transistor Ml, the current mirror circuit can operate in a saturation region even if the threshold -voltage of the N-channel MOS transistors M2 and M4 is higher than that of the N-channel MOS transistors M3 and M5.

Fig-9 is the circuit diagram of a still further I current mirror circuit.

In this figure, Ml through M5 indicate N-channel MOS transistors. Il indicates a first current mirror input current, while 12 indicates a second current mirror input current. The current mirror circuit shown in Fig-9 is implemented by. replacing the voltage drop device DO shown in Fig. 5 with a diode Dl.

A ratio between a value of the f irst current mirror input current Il and a proportion "Wl/Ll" of gate length to gate width of the N-channel MOS transistor M is set. to be equal to a ratio between a value of the second current mirror input current 12 and a proportion "W3/L3" of gate length to gate width of the N-channel MOS transistor M3.

Then, a ratio between the proportion "W3/L3" of gate length to gate width of the N-channel MOS transistor M3 and a proportion "W5/LS" of gate length to gate width of the N-channel MOS transistor M5 is set to be equal to a. ratio between a proportion "W2/L2" of gate length to gate width of the N-channel MOS transistor M2 and a proportion "W4/L4" of gate length to gate width of the N-channel MOS transistor I I I e I 32 m4.

A type of the diode Dl is selected so that a value of the voltage VD1 between terminals of the diode Dl is equal to or less than the value of the threshold voltage Vth. Especially, it is desirable that the value of the voltage VD1 between terminals of the diode D1 becomes equal to, or close to the value of the threshold voltage Vth.

As a result, an electric potential of the drain of the N-channel MOS transistor Ml (electric potential at node (2)) drops by the value of the voltage VD1 between terminals of the diode Dl.. Since the electric potential of the drain of the N-channel MOS transistor Ml drops by the value.of the voltage VD1 between terminals of the diode Dl, the electric potential of the drain of the N-channel MOS transistor M3 (electric potential at node (4)) drops by the value of the voltage VDI between terminals o the diode Dl, and at the same time, the electric potential of the drain of the N-channel MOS transistor M5 (electric potential at node (6)) drops by the value of the voltage VD1 between terminals of the diode Dl. As a result, the minimum value of the output voltage Vo operating in a saturation region drops by the value of the voltage VD1 between terminals of the diode Dl.

I 33 Assume that t he values of the first and the second current mirror input currents Il and 12 are equal to a value of the reference current Iref, the value of the volt - age VD1 between terminals of the Diode D1 is equal to the value of the threshold voltage Vth of the N-channel MOS transistor M1, the gate lengths Ll through L5 of the N-channel MOS transistors Ml through M5 are the same, and the gate widths W1 through W5 of the N-channel MOS transistors M1 through M5 are the same.

In this case, the relationship between the output voltage Vo and the output current Io is like that shown'in Fig.6. The output current Io equal to the reference current Iref can be obtained on the condition the output voltage Vo is equal to or higher than 2a.

With the current mirror circuit as described above, by equalizing the value of the voltage VD1 between terminals of the diode Dl to a value of the threshold voltage Vth of the N-channel MOS transistor Ml, the electric potential of the gate of the N-channel MOS transistor M4 can be set to Vth+2a, and the minimum value of the output voltage Vo operating in a saturation region can be set to 2a.

- 34 Additionally, a voltage at an output side of the first current mirror input current Il which requires higher voltage at an input terminal results in Vth+a, which is lower than that of the cascade current mirror circuit shown in Fig.1 by the threshold voltage Vth.

Furthermore, a voltage required to return a current by connecting an output of an N-channel cascade current mirror and an input of a P-channel cascade current mirror, results in (Vth+2a) + (2a), thereby lowering the required voltage by 2Vth in comparison with the cascade current mirror shown in Fig.l.

In the meantime, by setting the value of the voltage VD-1 between terminals of the diode Dl to a value equal to or less than the threshold voltage Vth of the N-channel MOS transistor Ml, the circuit can operate in a saturation region even if the threshold voltage of the N-channel MOS transistors M2 and M4 i4 higher than that of the N-channel MOS transistors M3 and M5.

Next, there will be described various reference current generation circuits embodying the present invention, which I generate one of two input currents required by a first current mirror circuit in a second current mirror circuit.

Fig. 10 is a block diagram of a basic structure of such a reference current generation circuit.

In this figure, a current mirror circuit 1 is implemented by a P-channel transistor, and includes two input terminals IN1 and IN2, and "N" output terminals OUT1 through OUTN. A current mirror circuit 2 is implemented by an N-channel transistor, and includes two input. terminals IN11 and IN12, and one output terminal OUT.

The input terminal IN2 of the current mirror circuit 1 is connected to the output terminal OUT of the current mirror circuit 2, and the output terminal OUT1 of the current mirror circuit 1 is connected to the input terminal IN11 of the current mirror 2. The output terminal OUT2 of the current mirror circuit 1 is connected to the input terminal: IN12 of the current mirror circuit 2.

A current mirror ratio between the input terminal IN2, the output terminal OUT1, and the output terminal OUT2 of -the first -current mirror circuit 1, is made equal to a ratio between the output terminal OUT, the 36 input terminal IN11, and the input terminal IN12 of the current mirror circuit 2.

Reference current generation circuits of the con-Eiguration shown in Fig. 10 function as follows.

In Fig.10, by externally supplying_ an input current Il to the input terminal IN1 of the current mirror circuit 1, an input current 12 is supplied from the output terminal OUT of the -current mirror circuit 2 to the input terminal IN2 of the current mirror circuit 11 an input current'13 is supplied from the output terminal OUT1 of the current mirror circuit 1 to the input terminal IN11 of the current mirror circuit 2, and an input current 14 is supplied from the output terminal OUT2 of the current mirror circuit 1 to the input terminal IN12 of the current mirror circuit 2. If.

That is, externally supplying one input current Il allows the output terminals OUT3'through OUTN of the current mirror circuit 1 to externally output a plurality of output currents I.ol through Io(n-2).

As described above, the reference current generation circuit of Fig. 10, employs the two-input current I 37 mirror circuits 1 and 2, and generates the input current 12 to the current mirror circuit 1 using feedback from the current mirror circuit 2. Two input currents'to the current mirror circuit 2 are generated by currents 13 and 14 among the output currents 13, 14, and Iol through Io(n-2) from the current mirror circuit 1. That is, by externally supplying one input current I1, a plurality of output currents Iol through Io(n-2) can be output dependant on the precisions of the current mirror circuits 1 and 2.

When this circuit is employed in an IC or an LSI, it will be very effective.

Additionally, if this circuit is employed as a power supply for a. circuit which requires a plurality of high precision input currents according to a ratio of a size of an input transistor, such as the curren-t; mirror circuit shown in Fig.5, the compound current mirror circuit shown in Fig.3, etc., the current mirror circuit shown in Fig.5 and the compound current mirror circuit shown in Fig.3 can operate with high precision.

Provided next is the explanation about a reference current generation circuit embodying the invention, 38 which -- employs a current amplification circuit shown in Fig.7 replaced by a P-channel MOS transistor as the current mirror circuit 1 shown in Fig. 10, and also employs. the current amplification circuit including an N-channel MOS transistor shown in Fig.7 as the current mirror circuit 2 shown in Fig.10.

Fig.11 is a circuit diagram showing this reference current generation circuit.

In this figure, a current mirror circuit 1 is composed of P-channel MOS transistors M10 through M21, and includes two input terminals IN1 and IN2, and "N" output terminals OUT1 through OUTN.

Here, the input terminal IN1 is connected to a drain of the P-channel MOS transistor M13, the inpujt terminal IN2 is connected to a drain of the Pchannel MOS transistor Mll, the output terminal OUT1 is connected to a drain of the P-channel MOS transistor M15, the output terminal OUT2 is connected to a drain of the P-channel MOS transistor M17, the output terminal OUT3 is connected to a drain of the P-channel MOS transistor M19, and the output terminal OUTN is I 39 connected to a drain of the P-channel m0S transistor M2 1.

Source terminals of the P-channel MOS transistors M10, M12-1 M14, M16, M18, and M20 are connected to an output terminal of a voltage VD, and drain terminals of the P-channel MOS transistors M10, M12, M14, M16, M18, and M20 are respectively connected to source terminals of the P-channel MOS transistors Mll, M13, M15,-M17, and M19.

A gate terminal of the P-channel MOS transistor Mll is connected to the drain terminal of the P channel MOS transistor,Mll, and this transistor Mll serves as a voltage drop device.

Gate terminals of the P-channel MOS transistors M10, M12, M14, M16, M18, and M20 are connected to the input terminal IN2 to configure a current mirror, and gate terminals of the P-channel MOS transistors M13, M15, M17, M19, and M21 are connected to the input terminal IN1 to configure a current mirror A current mirror circuit 2 is composed of N channel MOS transistors M22 through M27, and includes two input- terminals IN11 and IN12, and one output terminal OUT.

The input terminal IN11 is connected to a drain of the N-channel MOS transistor M24, the input terminal IN12 is connected to a drain of the N-channel MOS transistor M26, the output terminal OUT is connected to a drain of the N-channel MOS transistor M22.

Source terminals of the N-channel MOS transiszors M23, M25, and M27 are connected to a ground GND, while source terminals of the N-channel MOS transistors M22, M24, and M206 are respectively connected to drain terminals of the N-channel MOS transistors M23, M25, and M27.

10. A gate terminal of the N-channel MOS transistor M26 is connected to the drain terminal of the N channel MOS transistor M26, and this transistor M26 serves as a voltage drop device.

. Gate terminals of the N-channel MOS transistors m22 and M24 are connected to the input terminal _INl to configure a current mirror, and the gate terminals of the N-channel MOS transistors M23, M25, and M27 are connected to the input terminal IN12 to configure i current mirror.

The input terminal IN2 of the current mirror circuit 1 is connected to the output terminal OUT of the current mirror circuit 2, and the output terminal OUT1 of the c urrent mirror circuit 1 is connected to the input terminal IN11 of the current mirror circuit 2. The output terminal OUT2 of the current mir-ror I 41 circuit 1 is connected to the input terminal IN12 of the current mirror circuit 2.

A current mirror ratio between the input terminal IN2, the'output terminal OUT1, and the output terminal OUT2 of the current mirror circuit 1 is equalized to a ratio between the output terminal OUT, the input terminal IN11, and the input terminal IN12 of the current mirror circuit 2.

The operation of the above circuit will now be described.

in Fig.11, by externally supplying an input current 11 to the input terminal IN1 of the current mirror circuit 1-J -an input current 12 is supplied from the output terminal OUT of the current mirror circuit 2 to the input terminal IN2 of the current mirror circuit 1, an input current 13 is supplied from th4 output terminal OUT1 of the current mirror circuit 1 to the input terminal IN11 of "the current mirror circuit 2, and an input current 14 is supplied from the output terminal OUT2 of the current mirror circuit 1 to the input terminal IN12 of the current mirror circuit 2.

That is, the input current 12 of the two input 42 currents Il and 12 of the current mirror circuit 1 is supplied from the output terminal OUT of the current mirror circuit 2, and the-two input currents 13 and 14 of the current mirror circuit 2 are supplied -Erom the output terminals OUT1 and OUT2 of the current mirror circuit 1.

As a result, externally supplying only one input current Il allows the two-input current mirror circuits 1 and 2- to operate, and also allows the output terminals OUT3 through OUTN to output a plurality of output currents lol through Io(n-2) of the current-mirror circuit 1._ The above described embodiment refers to the case where the input current 12 fromthe current mirror circuit 2 is supplied to the input terminal IN2 of the current mirror circuit 1. However, the input current 12 from the current mirror circuit 2 may be supplied to the input terminal IN1 of the current mirro; circuit 1 Additionally, the above described embodiment refers to the case where the current amplification circuit shown in Fig.7 is employed as the current mirror circuits 1 and 2. Alternatively, the current amplification circuits shown in Fig.8 or Fig.9 may be used.

I 43 The compound current mirror circuit shown in Fig. 3 may be also used as- the current mirror circuits 1 and 2.

Alternatively, N-channel MOS transistors and P- channel MOS transistors may be used in the current mirror circuits 1 and 2 respectively.

In the above circuit, two-input current mirror circuits 1 and 2 are used, and the input current 12 to the current mirror circuit 1 is generated by feedback from the current mirror circuit 2. Therefore, externally supplying one input current Il allows output of a plurality of output currents Iol through Io(n-2), dependant on the precisions of the current mirror circuits 1 and 2.

Provided next is the explanation about another reference current generation circuit embodying the present invention, where the input current Il of the reference current generation circuit shown in Fig.11 is generated by a voltage/current conversion circuit.

44 Fig. 12 is a circuit diagram showing a structure of this reference current generation circuit.

In this figure, current mirror circuits 1 and 2 are the same as those shown in Fig.11.

A voltage/current conversion circuit 3 is composed of an operational amplifier OP1, an N-channel MOS_ transistor M28, and a resistor RREF1. An output terminal of the operational amplifier OP1, is connected to a gate terminal of the N-channel MOS transistor M28. A source terminal of the N-channel MOS transistor M28 is connected to an inverting input terminal of the operational amplifier OP1, and also connected to a ground GND via the resistor RREF1.

is A drain terminal of the N-channel MOS transistor M28 is connected to an input terminal IN1 of the current mirror circuit 1.

By inputting a reference voltage VREF to a nonT inverting input terminal of the operational amplifier OP1, the reference voltage VREF can be supplied to -zhe resistor RREF1, and a reference current Iref=VREF/RREF1 can be generated in a drain of the Nchannel MOS transistor M28. As a result, the reference current Iref is supplied to the input terminal IN1 of the current mirror circuit 1- I The operation of this circuit will now be described.

In Fig.12, the reference current Iref is supplied from the -voltage/current conversion circuit 3 to the input terminal IN1 of the current mirror circuit 1, an input current 12 is supplied from the output terminal OUT of the current mirror circuit 2 to the input terminal IN2 of the current mirror circuit 1, an input current 13 is supplied from the output terminal OUT1 of the current iftirror circuit 1 to the input terminal IN11- of the current mirror circuit 2, and an input current 14 is supplied from the output terminal OUT2 of the current mirror circuit 1 to the input terminal IN12 of the current mirror circuit 2.

That is, input current 12, which is one of the two input currents Il and 12 of the current mirror circuit 1, is supplied from the output terminal OUT of the current mirror circuit 2, and t;,o input currents 13 and 14 to the current mirror circuit 2 are supplied from the output terminals OUTI and OUT2 of the current mirror circuit 1.

As a result, supplying the reference voltage VREF to the voltage/current conversion circuit 3 allows the 46 two-input current mirror circuits 1 and 2 to operate, and also allows output terminals OUT3 through OUTN of the current mirror circuit 1 to externally output a plurality of output currents Iol through Io(n-2).

The above described embodiment refers to the case where the input current 12 from the current mirror circuit 2 is supplied to the input terminal IN2 of the current mirror circuit 1. However, the input current 12 from the current mirror circuit 2 may be supplied to the input terminal IN1 of the current mirror circuit 1.

Additionally, the above described embodiment refers to the case where the current amplification circuit shown in Fig.7 is employed as the current mirror circuits 1 and 2. Alternatively, the current amplification circuits shown in Fig.4 or Fig.5 may be used.

- Alternatively, N-channel MOS transistors and P channel MOS transistors may be used in the current mirror circuits 1 and 2 respectively. In this case, the P-channel MOS transistor replaces the N-channel MOS transistor M28, and a power supply voltage VD replaces the ground GND.

With the reference current generation circuit I of Fig. 12 as described above, two-input current mirror circuits 1 and 2 are used, and the input current 12 to the current -mirror circuit 1 is generated by feedback' from the current mirror circuit 2. In addition, the reference current Iref from the voltage/current conversion circuit 3 is supplied to the input terminal IN1 of the current mirror circuit 1. As a result, supplying only the reference voltage VREF to the voltage/current conversion circuit 3 allows output of a plurality of output currents Iol through Io(n-2), dependant. on the precisions of the current mirror circuits 1 and 2.

There will now be described a further reference current generation circuit embodying the invention, implemented by using the compound current mirror circuit shown in Fig.3 as the current mirror circuits 1 and 2 shown in Fig.12.

Fig. 13 is a circuit diagram showing a structure of this reference current generation circuit- In Fig. 13, a compound current mirror circuit 4 is composed of P-channel MOS transistors M30 through M42, 48 and includes two i:nput terminals IN1 and IN2, and "N" output terminals OUT1 through OUTN.

The input terminal IN1 is connected to a drain of the P-cliannel MOS transistor M32, the input terminal IN2 is connected to a drain of the P-channel Mos transistor M30, the output terminal OUT1 is connected to a drain of the P-channel MOS transistor M34, the output terminal OUT2 is connected to a drain of the P- channel. MOS transistor M36, the output terminal OUT3 is connected to a drain of the P-channel MOS transistor M38, the output terminal OUT4 is connected to a drain of the P-channel MOS transistor M40, and the output terminal OUTN is connected to a drain of the P-channel MOS transistor M42.

Source terminals of the P-channel MOS transistors M30, M31, M33, M35, M37, M39, and M41 are connected to an output terminal of a voltage VREFO, and drain terminals of the P-channel MOS transistors M31, M33w M35, M37, M39, and M41 are respectively connected to source terminals of the P-channel MOS transistors M32, M34, M36, M38, M40, and M42.

A gate terminal of the P-channel MOS transistor M30 is connected to a drain terminal of the P-channel MOS transistor M30.

Gate terminals of the P-channel. MOS transistors I 49 M31, M33, M35, M37, M39, and M41 are connected to the input terminal IN1 to configure a current mirror, and gate terminals of the P-channel MOS transistors M32, M34, M36, M38, M40, and M42 are connected to the input terminal IN2 to configure a current mirror.

A compound current mirror circuit 5 is composed of N-channel MCS transistors M43 through M47, and includes two input terminals IN11 and IN12 and o ne output terminal OUT.

The input terminal IN11 is connected to a drain of the N-channel MOS transistor M45, while the input terminal IN12 is connected to a drain of the N-channel MOS transistor M47. The output terminal OUT is connected to a drain of the N-channel MOS transistor M43 Source terminals of the N-channel MOS transistors M44, M46, and M47 are connected to an output terminal of a voltage VREF2. Source terminals of the N-chennel MOS transistors M43 and M45 are connected to drain terminals of the N-channel MOS transistors M44 and M46 respectively.

A gate terminal of the N-channel MOS transistor M47 is connected to a drain terminal of the N-channel MOS transistor M47.

Gate terminals of the N-channel MOS transistors M44 and M46 are connected to the input terminal IN11 to configure a current mirror, while gate terminals of the N-channel MOS transistors M43, M45, and M47 are connected to zhe input terminal IN12 to configure a current mirror.

A proportion of gate length to gate width of the P-channel MOS transistor M30 is set to one fourth of a proportion W/L of gate length to gate width of the P-channel MOS transistors M31 through M42. A proportion of gate length to gate width of the Nchannel MOS transistor M47 is set to one f ourth of a proportion W/L of gate length to gate width of the Nchannel MOS transistors M43 through M46.

The input terminal IN1 of the compound current mirror circuit 4 is connected to a drain of the Nchannel MOS transistor M48, while-the input terminal IN2 of the compound current mirror circuit 4 is connected to the output terminal OUT of the compounj current mirror circuit 5. The output terminal OUT1 of the compound current mirror circuit 4 is connected to the input terminal IN11 of the compound current mirror circuit 5, while the output terminal OUT2 of the compound current mirror circuit 4 is connected to the input terminal IN12 of the compound current mirror circuit 5.

I 51 A current mirror ratio between the input terminal IN2, the output terminal OUT1, and the output terminal OUT2 of the compound current mirror circuit 4 is set to be a rati.o equal to that between the output terminal OUT, the input terminal IN11, and the input terminal IN12 of the compound current mirror circuit 5.

A voltage/current conversion circuit 6 is composed of an operational amplifier OP2, an N-channel MOS transistor M48, and a resistor RREF2. An output terminal of the operational amplifier OP2 is connected to a gateterminal of the N- channel MOS transistor M48. A source terminal of the N-channel MOS transistor M48 is connected to an inverting input terminal of the operational amplifier OP2, and also connected to an output terminal of a voltage VREF3 via the resistor RREF2.

A drain terminal of the N-channel MOS transistor M48 is connected to the input terminal INI of the current mirror circuit 4.

As a result, by inputting the reference voltage VREF1 to a non-inverting input te=inal of the operational amplifier OP2 and the reference voltage VREF1 to the resistor RREF2, the reference current Iref=VREFl/RREF2 can be generated in the drain of the 52 N-channel MOS transistor M48. As a result, the reference current Iref can be supplied to the input terminal IN1 of the current mirror circuit 4- Provided next is the explanation about operations performed by this reference current generation circuit in Fig.13, the reference current Iref is supplied from the voltage/current conversion circuit 6 to the input terminal IN1 of the compound current mirror circuit 4, the input current 12 is supplied from the output terminal OUT of the compound current: mirror circuit 5 to the input terminal IN2 of the compound current mirror circuit 4, the input current 13 is supplied from the output terminal OUT1 of the compound current mirror circuit 4 to the input term--Inal IN11 of the compound current mirror circuit 5, and the input current 14 is supplied from the output term-"nal OUT2 of the compcund current mirror circuit 4 to -,he input terminal!N'-,2 of the comzound currenz mirror circuit 5.

That is, input current 12, which is one of the two input currents Il and 12 of the compound current mirror circuit 4, is supplied from the output terminal OUT of the compound current mirror circuit 5, and the I 53 input currents 13 and 14 are supplied f rom the output terminals OUT1 and OUT2 of the compound current mirror circuit 4 - As a result, supplying only the reference voltage VREF1 from the voltage/current conversion circuit 6 allows the two-input compound current mirror circuits 4 and 5 to operate, and also allows the output terminals OUT3 through OUTN to output a plurality of output currents Iol through lo(n-2).

The above described embodiment refers to the case where the input current 12 from the compound current mirror circuit. 5 is supplied to the input term:Lnal IN2 of the compound current mirror circuit 4. However, the input current 12 from the compound current mirror circuit 5 may be supplied to the input terminal IN1 of the compound current mirror circuit 4.

Furthermore, N-channe! MOS transistors and Pchannel MOS transistors mav be used in the compound current mirror circuit 4 and 5 respectively. In this case, a P-channel MOS transiszcr replaces the Nchannel transistor M48 and a power supply voltage VD replaces the ground GND.

With this circuit, the two-input compound 54 current mirror circuits 4 and 5 are used and the input current 12 of the compound current mirror circuit 4 is generated by feedback from the compound current mirror circuit 5. Additionally, the reference current Iref is supplied from the voltage/current conversion circuit 3. to the input terminal IN1 of the compound current mirror circuit 4. As a result, a plurality of. output currents Iol through Io(n-2) can be output, dependant on the precisions of the compound current mirror circuits 4 and 5.

There will now be described a voltage/current conversion circuit embodying the present invention, which is intended to generate two equal reference currents from one reference voltage.

Fig.14 is a circuit diagram showing a Of", the voltage/current conversion circuit.

In this figure, OP3 and OP4 indicate operational amplifiers, M50 and M51 indicate N-channel MOS transistors, and Rl indicates a resistor- A drain of the N-channel MOS transistor M50 is connected to a first current output terminal, and a I gate of the N-channel MOS transistor M50 is connected to an output terminal of the operational amplifier OP3, and a source of the N-channel MOS transistor M50 is connected to a ground GND via the resistor Rl.

A drain of the N-channel MOS transistor M51 is connected to a second current output terminal. A gate of the N-channel MOS transistor M51 is connected to the output terminal of the operational amplifier OP3.

A source of the N-channel MOS transistor M51 is connected to an output terminal of the operational amplifier OP4.

A non-inverting input terminal of the operational amplifier OP3 is connected to an output terminal of the reference voltage VREF4, and an inverting input of the operational amplifier OP3 is connected to the source terminal of the N-channel MOS transistor M.K.

A non-inverting input of the operational amplifier OP4 is connected to an outnut terminal of a reference voltage VREF4, while an inverting input cf 7-.e 2C operational amplifier OP4 is connected to an terminal of the operational amplifier OP4_ That is, a first reference current Il is generated by a first reference current generation circuit including the operational amplifier OP3, the N-channel MOS transistor M50, and the resistor Rl, while a 56 second reference current 12 is generated by a second reference current generation circuit including the operational amplifier OP4 and the N-channel MOS transistor N151, which are configured as a voltage follower.

Provided next is the explanation abou-t operations performed by this. voltage/current conversion circuit, In Fig.14, if a gain of the operational amplifier OP3 is infinite, electric potentials of non-inverting and inverting inputs of the operational amplifier OP3 become equal. If the reference voltage VREF4 is supplied to. the non-inverting input of the operational amplifier OP3, an electrical potential of the source of the N-channel MOS transistor M50 (electric potential at node (1)) becomes equal to the reference voltage VREF4. Even if the gain of the operationa_ amplifier OP3 is not infinite but large, the error range is small.

Accordingly, the first reference current Il according to a value of the VREF4/Rl is applied to the drain of the N-channel MOS transistor M50.

Additionally, since the operational ampl-ifier OP4 is a voltage follower, electric potentials of a non- I 57 inverting input and an output of theoperational amplifier OP4 become equal- As a result, the electric potential of the source of the N-channel MOS transistor M51 (electric potential at node (2)) becomes equal to the reference voltage VREF4.

If a size of the N-channel MOS transistor M50 is equal to that of the Nchannel MOS transistor M51, a voltage between a gate and a source of the N-channel MOS transistor M50 and M51 is a value obtained by subtracting the reference voltage VREF4 from an output voltage VOUT of the operational amplifier OP3.

Accordingly, to the drain of the N-channel MOS transistor M51, a current becomes the same. as that applied to the drain of the N-channel MOS transistor M50, and the value of the first and the second reference currents Il and 12 become equal. - By making the size of the N-channel MOS transistor M50 different from that of the N-channel MCS transistor M51, the first and the second reference currents Il and 12 can be also obtained as being dependant on a ratio of the size of the N-channel MOS transistor M50 to the size of the N-channel MOS transistor M51.

In this voltage/current conversion circuit, 58 as described above, a plurality of reference currents Il and 12 can be obtained from the reference voltage VREF4.

If electric potentials of output terminalsare equalized, precision can be improved in comparison with a plurality of reference currents generated by a normal current mirror. P-channel MOS transistors may replace the N-channel MOS transistors M50 and M51. It is not significant if the ground GND has a different electric potential.

Another voltage/current is conversion circuit -embodying the present invention is intended to generate a plurality of reference currents by supplying two reference currents generated by the voltage/currenIt conversion circuit shown in Fig.14, to the current mirror circuit shown in Fig.7.

Fig.15 is a circuit diagram showing a structure of this voltage/current conversion circuit.

In this figure, a current mirror circuit 7is composed of P-channel MOS transistors M60 through M69, I I 59 and includes two input terminals IN1 and IN2, and "N" output terminals OUT1 through OUTN- The input terminal IN1 is connected to a drain of th.e P-channel:,,!'-)S zrans-istor M611 the inout terminal.

IN2 is connected to a drain of the P-channel MOS transistor M63, the out"out terminal OUT1 is connected to a drain of the P-channel MOS transistor M65, the output terminal OUT2 is connected to a drain of the Pchannel MOS transistor M67, and the output terminal OUTN is connected to a drain of the P-channel MOS transistor M69.

Source termInals of the P-channel OS transistors M60, M62, M64, M66, and M68 are connected to an output terminal of a voltage VD. Drain terminals of thd P- channel MOS transistors M60, M62, M64, M66, and M68 are connected to source terminals of the P-channel MOS transistors M61, M63, M65, M67, and M69 respectively.

A gate terminal of the P-channel MOS transistor M61 is connected to a drain terminal of the P-channel MOS transistor M61, and this transistor M61 serves as a voltage drop device.

Gate terminals of the P-channel MOS transistors M60, M62, M64, M66, and M68 are connected to the input terminal IN1 to configure a current mirror, and gate terminals of the P-channel MOS transistors M63, M65, M67, and M69 are connected to the input terminal IN2 to configure a current mirror A voltage/current conversion circuit 8 is composed o.-c' operationaI amplifiers OP5 and OP6, N-channel MOS transistors M70 and M71, and a resistor RREF3.

A source of' the N-channel MOS transistor M70 is connected to an output terminal of a voltage VREF6 via a resistor RREF3, and a gate of the N-channel MOS transistor M70 is connected to an output terminal of the operational amplifier OP5 to which a ref erence voltage VREF5 is. input as a non-Inverting input, and to which a source voltage of the N-channel MOS transistor M70 is input as an inverting input.

A source of the N-channel MOS transistor M71 is connected to an output terminal of the operational amplifier OP6 configuring a voltage follower, and a gate of the N-channel MOS transistor 71 is connected -to an output terminal of the operational amplifier OP5.

The input terminal INI of a current mirror circuit 7 is connected to a drain of the N-channel MOS transistor M70, while the input terminal IN2 of the current mirror circuit 7 is connected to a drain of the N-channel MOS transistor M71.

I 61 The operation of this circuit will now be described.

in Fig.15, by suppl-...r-ing a refrerence voltage VREF5 to a non-inverting input of the operational ampliffier OP5, a first reference current Il=VRE---5/RREF3 is applied to the drain of the N-channel MOS transistor M70, while a second reference current 12=VREF5/RREF3 is applied to the drain of the N-channel MOS transistor M71. Then, the first reference current Il is supplied to the input terminal IN1 of the current mirror circuit 7, while the second reference current 12 is supplied to the input terminal IN2 of the current mirror circuit 7.

The current mirror circuit 7 to which the first and the second reference currents Il and 12 are supplied, outputs a plurality of reference currents -Iol through IoN from output terminals OUT1 through OUTN by performing a current mirror operation.

The above described embodiment refers to the case where the input current Il from the voltage/current conversion circuit 8 is supplied to the input terminal IN1 of the current mirror circuit 7, and the input current 12 from the voltage/current conversion circuit 8 is supplied to the input terminal IN2 of the current t 62 mirror circuit 7. However, the input currents Il and 12 from the voltage/current conversion circuit 8 may be supplied to the input terminals IN2 and INI of the currentm_r_ro_r ircuir 7 respectively.

The above described embodiment also refers to the examole where --'-e current amplification circuit shown in Fig.3 is used as the current mirror circuit 7, is given- However, the current amplification circuit shown in Fig.8 or Fig.9 may be used.

Alternatively, N-channel MOS transistors may be used as the current mirror circuit 7. In this case, P-channel MOS transistors replace the N-channel MOS transistors M70 and M71.

As. described above, the f irst and the second reference currents Il- and 12 generated from one -reference voltage VREF5 are used as two input currents to the current mirror circuit 7, thereby obtaining a plurality of high precision reference currents Iol through IoN.

A further voltage/current I 63 conversion circuit embodying the present invention is intended to generate a plurality of reference currents by suoplying two, reference cu--rre.nts generated by the vo 1 tage /currentconversion circuit shown in Fig. 14 to the comcound current mirror circuit shown in Fig.3.

Fig.16 is a circuit diagram of the structure of this voltage/current conversion circuit.

In this figure, a compound current mirror circuit 9 is composed of P-chaxinel MOS transistors M80 through M88 and includes two input terminals IN1 and IN2, and "N" output terminals OUT1 through OUTN. A proportion of gate length to gate width of the P-channel MOS transistor M80 is one fourth of a proportion "W/L" of gate length to gate width of the P-channel MOS transistors M81 through MSS.

The input terminal INI is connected to a drain of the P-channel MOS transistor M80, while the input terminal IN2 is connected to a drain of the P-channel MOS transistor M82. The output terminal OUT1 is connected to a drain of the P-channel MOS transistor M84, while the output terminal OUT2 is connected to a drain of the P-channel MOS transistor M86. The output terminal OUTN is connected to a drain of the 64 P-channel MOS transistor m88.

Source terminals of the P-channel MOS transistors M80, M81, M83, M85, and M87 are connected to an output terminal of a voltage VREF9. Drain terminals o-;;' the P-channel MOS transistors M81, M83, M85, M87 are connected to source terminals of the P-channel MOS transistors M82, M84, M86, and M88 respectively.

A gate terminal of the P-channel MOS transistor M80 is connected to a drain terminal of the P-channel MOS transistor M80.

Gate terminals of the P-channel MOS transistors M80, M82, M84, M86j and M88 are connected to the input terminal IN1 to configure a current mirror, while gate terminals of the P-channel MOS transistors M81, M83, M85, and M87 are connected to the input te=lnal IN2 to configure a current mirror.

A voltage/current conversion circuit 10 is composed of operational amplifiers OP7 and OP8, - channel MOS transistors M89 and M90, and a resis7or RREF4.

A source of the N-channel MOS transistor M89 is connected to an output terminal of a voltage VREF8 via a resistor RREF4, and a gate of the N-channel MOS transistor M89 is connected to an output terminal of the operational amplifier OP7 to which a reference I e voltage VREF7 is-input as a non-inverting input, and -to which a source voltage of the N-channel mOS transistor M89 is input as an inverting input.

A source of the N-channel MOS transistor M90 is connected to an output terminal of the operational amplifier OP8 configuring a voltage follower, and a gate of the N-channel MOS transistor M90 is connected to an outpi4t terminal of the operational amplifier OP7.

The input terminal IN1 of -the compound current mirror circuit 9 is-connected to a drain of the Nchannel MOS transistor M89. The input terminal IN2 of the compound current mirror circuit 9 is connected to a drain of. the N-channel MOS transistor M90.

15.

The operation of this circuit will now be described.

In Fig.16, by supplying the reference voltage VREF7 to the non-inverting input of the operational amplifier OP7, the first reference current Il=VREF7/RREF4 is applied to the drain of the N channel MOS transistor M89, and the second reference current 12=VREF7/RREF4 is applied to the drain of the N-channel MOS transistor M90. Then, the first 66 reference current'Il is-supplied to the input terminal IN1 of the compound current mirror circuit 9, and the second reference current 12 is supplied to the input terminal IN2 of the compound current mirror circuit 9.

The compound current mirror circuit 9. to which the first and the second reference currents Il and 12 are supplied outputs a plurality of reference currents Iol through Iol! from output terminals OUT1 through OUTN.

The above described embodiment refers to the case where the input current Il from the voltage/current conversion circuit 10 is supplied to the Input terminal IN1 of the current mirror circuit 9, and the.input current 12 from the voltage/current conversion circuit 10 is supplied to the input terminal IN2 of the current mirror circuit 9. However, the input current Il from the voltage/current conversion circuit 10 may be supplied to the input terminal IN2 of the current mirror circuit 9, and the input current 12 from the voltage/current conversion circuit 10 may be supplied to the input terminal IN1 -of the current mirror circuit 9.

Alternatively, N-channel MOS transistors may be used in the current mirror circuit 9. In this case, P-channel MOS transistors replace the N-channel MOS 67 transistors M89 and M90.

With this voltage/current conversion circuit, the first and the second reference currents ii and 12 generated from one reference voltage VREF7 are used as two input currents to the compound current mirror ci rcuit 9, thereby obtaining the plurality of high precision reference currents Iol through IoN.

The above described embodiment of the present invention is not limited to this case. Field-effect transistors or bipolar transistors'. for example, may_ replace.:- the MOS transistors.

As described above.. with reference -to Fig. 5, since the drain of the first input- transistor is connected to the f irst current input terminal via the voltage drop device, the electric potential of the drain of the second output transistor can be lowered by a voltage drop produced by the voltage drop device,., thereby lowering an output voltage.

Furthermore, since the voltage drop produced by the voltage drop device is set to a value equal to or less than a threshold voltage of the f irst input transistor, an output voltage can be lowered by a voltage drop produced by the voltage drop dev-ice while leaving a precision of the output current unchanged.

68 In addition, adjusting a proportion of gate length to gate width of a transistor allows each transistor to operate in a saturation region, thereby obtaining a high precision output current.

In the meantime, a voltage drop can be set arbitrarily. Since a diode may be used as the voltage drop device as shown in Fig.9, a voltage drop can be set with high.precision.

Furthermore, as shown in Fig.10, one of current inputs -to the first current amplification circuit which requires two current inputs may be generated by using a..' second. current amplification circuit, and a current input to the second current amplification circuit may be generated by using the first current amplification circuit. - As a result, externally supplying only one input current allows a current amplification circuit which requires two current inputs, to output a plurality of output currents., Additionally, a current amplification circuit comprising: a first input transistor whose drain is connected to a first current input terminal via a voltage drop device, whose gate is connected to the first current input terminal, and whose source is connected to a common terminal; a second input transistor whose drain and gate are connected to a I 69 second current input terminal a third input transistor whose drain is connected to a source of the second input transistor, whose gate is connected to the first current input terminal, and whose source is connected to the common terminal; a first output transistor whose drain is connected to an output terminal, and whose gate is connected to the second current input terminal; and a second output transistor whose drain is connected to the source of the first output transistor, whose gate is connected to the - f irst current input terminal, and whose source is connected to the common terminal, is used as the first and the second current amplification circuits.

- Therefore, externally supplying only one input current allows a currentamplif ication circuit which requires two current inputs to output a plurality of high precision output currents at a low output voltage.

Furthermore, since a compound current mirrov circuit may be used as the f irst and the second current amplification circuits, externally supplying only one input current allows a current amplification circuit which requires two current inputs to output a plurality of high precision output currents at a low output voltage.

In the meantime, an output current from a voltage/current -conversion circuit to which a reference voltage is input, is used as an input current to the first current input terminal included in a current am-olification circuit as recited above, or to a compound current mirror circuit. Therefore, externally supplying only one reference voltage allows a current amplification circuit which requires two current inputs to externally output a plurality of high precision output currents at a low output voltage.

In addition, a P-channel field-effect transistor may be,' used -in the first current amplIfication circuit, and an N-channel field-effect transistor is used in the second current amplification circuit. As a result, externally supplying only one input current allows a current amplification circuit which requires two current inputs to output a plurality of output currents at-a low output voltage.

On the contrary, by using an N-channel field- effect transistor in the first current amplification circuit, and a P- channel field-effect transistor in the second current amplification circuit, externally supplying only one input -current allows a current amplification circuit which requires two current inputs to output a plurality of output currents at a I 71 low output voltage.

In the meantime, by inputting a result of comparison between a voltage of a source and a reference voltage to a gate of a f irst transistor, inputting the reference voltage to a source of a second transistor via a voltage follower, and inputting the result of the comparison to the gate of the second transistor, supplying only one reference voltage allows output of a plurality of high precision reference currents.

Furthermore, by supplying the first reference current: generated by inputting the result' of the comparison between the voltage of the source of the first transistor and the reference voltage, to the first current input terminal of the current amplification circuit as recited above, inputting the reference voltage to the source of the second transistor via a voltage follower, and supplying the second reference current generated by inputting the result of the comparison to the- gate of the second transistor, tothe second current input terminal of the current amplification circuit as recited above, supplying only one reference voltage allows output.of a plurality of high precision reference currents at a low voltage.

72 In addition, by supplying the first reference current generated by inputting the result of the comparison between the voltage of the source of the first transistor and the reference voltage, to the first current input terminal- of the compound current mirror circuit, inputting the reference voltage to the source of the second transistor via a- voltage follower, and supplying the second reference current generated by inputting the result of the comparison io to the gate of the second transistor, to the second current input terminal of the compound current mirror circuit. supplying. only one reference. voltage allows output of a plurali-ty of high precision reference currents.

i5 Furthermore, by connecting the source of the first transistor to a voltage input terminal via a resistance element, connecting its gate to an output terminal of the first operational amplifier to whicia a reference voltage is input as a non-inverting input and a voltage of the source is input as an inverting input, connecting a source of the second transistor to an output terminal of the second operational amplifier to which the reference voltage is input as a non- inverting input and an output voltage-is input as an inverting input, and connecting its gate to the I 73 output terminal 0 the first operational amplifier, supplying only one reference voltage allows output of a plurality of high precision reference currents.

In addizion, by supplying (N-1) input currents of the first reference current generation circuit which requires "N" -input currents, from (N-1) output currents ofthesecond reference current generation circuit which requires K(M>K) input currents, and supplying K input currents to the second reference current generation circuit from K output currents of the first reference current generation circuit, externally supplying only one Input current allows a current amplification circuit which requires a plurality of input currents to output a plurality of output currents.

74

Claims (6)

1. A reference current generation circuit, comprising:

a first reference current generation circuit for generating a first reference current by inputting a result of a comparison between a source potential of first transistor (M50) and a reference voltage, to gate of the first.transistor (M50); and a second reference current generation circuit for generating a second reference current by inputting the reference voltage to a source of a second transistor (M51) via a voltage follower (OP4), and inputting the result of the comparison to a gate of the second transistor (M51).

2. A current amplification circuit, comprising:

means for supplying a first reference current generated by inputting a result of a comparison between an electric potential of a source of a first transistor (M89) and a reference voltage to a gate of the first transistor (M89), to a first current input terminal of a compound current mirror circuit (9); and means for supplying a second reference current generated by inputting the reference voltage to a source of a second transistor (M90) via a voltage I follower (OP8), and inputting the result of the comparison to a gate of the second transistor (M90), to a second current input terminal of the compound current mirror circuit (9).

3. A voltage/current conversion circuit, comprising:

a first transistor (M50) whose source is connected to a voltage input terminal via a resistance element (R1), and whose gate is connected to an output terminal of a first operational amplifier (OP3) to which a reference voltage is input as a non-inverting input and a voltage of the source of the first transistor (M50) is input as an inverting input; and a second transistor (M51) whose source is connected to an output terminal of a second operational amplifier (OP4) to which the reference voltage is input as a non-inverting input, and an output voltage is input as an inverting input, and whose gate is 41 connected to the output terminal of the first operational amplifier (OP3).

4. A reference current generation circuit according to claim 1 and substantially as hereinbefore described with reference to any one of Figures 10 to 13 of the accompanying drawings.

76 S. A current amplification circuit according to claim 2 and substantially as hereinbefore described with reference to any one of Figures 5 to 16 of the accompanying drawings. 5 6. A voltage/current conversion circuit according to claim 3 and substantially as hereinbefore described with reference to any one of Figures 14, 15 or 16 of the accompanying drawings.

I.

I 71.

Amendments to the claims have been filed as follows 1. A reference current generation circuit, comprising:

a first reference current generation circuit for generating a first reference current by inputting a result of a comparison between a source potential of a first transistor (M50) and a reference voltage, to a gate of the first.transistor (M50); and a second reference current generation circuit for generating a second reference current by inputting the reference voltage to a source of a second transistor (M51) via a voltage follower (OP4), and inputting the result of the comparison to a gate of the second transistor (M51).

2. A current amplification circuit, comprising:

means for supplying a first reference current generated by inputting a result of a comparison between an electric potential of a source of a first transistor (M89) and a reference voltage to a gate of the first transistor (M89), to a first current input terminal of a compound current mirror circuit (9); and means for supplying a second reference current generated by inputting the reference voltage to a source of a second-transistor (M90) via a voltage I If- 78.

follower (OPS), and inputting the result of the comparison to a gate of the second transistor (M90), to a second current input terminal of the compound current mirror circuit (9) 3. A voltage/current conversion circuit, comprising:

a first transistor (M50) whose source is connected to a voltage input terminal via a resistance element (R1), and whose gate is connected to an output terminal of a first operational amplifier (OP3) to which a reference voltage is input as a non-inverting input and a voltage of the source of the first transistor (M50) is input as an inverting input; and a second transistor (M51) whose source is connected to an output terminal of a second operational amplifier (OP4) to which the reference voltage is input as a non-inverting input, and an output voltage is input as an inverting input, and whose gate is connected to the output terminal of the first operational amplifier (OP3).

4. A reference current generation circuit according to claim 1 and substantially as hereinbefore described with reference to any one of Figures 14 to 16 of the accompanying drawings.

I I I I I -79.

5. A current amplification circuit according to claim 2 and substantially as hereinbefore described with reference to any one of Figures 15 and 16 of the accompanying drawings. 5

6. A voltage/current conversion circuit according to claim 3 and substantially as hereinbefore described with reference to any one of Figures 14, 15 or 16 of the accompanying drawings.