GB2345405A

GB2345405A - Measuring the bit error rate of TDM telecommunications channels

Info

Publication number: GB2345405A
Application number: GB9828802A
Authority: GB
Inventors: Stephen Routliffe; George Jeffrey
Original assignee: Mitel Corp
Current assignee: Microsemi Semiconductor ULC
Priority date: 1998-12-30
Filing date: 1998-12-30
Publication date: 2000-07-05
Also published as: DE19962242C2; DE19962242A1; GB9828802D0; FR2788182A1; CA2293201A1

Abstract

A device 2 for measuring the bit error rate of a telecommunications channel is mounted on a peripheral PC card and inserted into a card slot of a personal computer 1. The device is responsive to external program commands from the PC. A pseudo random sequence generator 8 generates a pseudo random sequence and sends it through an output means 3 for connection to a time division multiplexed telecommunications link in response to program commands received from the PC. Comparison of the received and transmitted sequences may be performed using an XOR gate and the transmitted sequences may be received either at a second test device or at the originating device via loop back. The sequence may be generated using a predetermined generator polynomial, eg <F>X<SP>15</SP> + X<SP>14</SP> + X<SP>2</SP> + 1</F>.

Description

2345405 BIT ERROR RATE TESTER

This invention relates to the field of telecommunications, and more particularly to a device for measuring the reliability of a digital telecommunications channel by measuring the bit error rate.

Any telecommunications path is subject to errors, which can cause transmitted bits to become inverted. In order to monitor the performance of telecommunication networks, there is a need to monitor the rate at which bit errors occur. A device for carrying out this task is known as a BERT (Bit Error Rate Tester). A BERT can be connected a telecommunications channel and made to send a known sequence of I's and O's, which can be monitored by a receiving device at the far end for errors. BERTs are typically stand-alone devices, which offer limited flexibility to the user. Such devices are used on T 1, E I and ISDN lines.

In a time division multiplex environment, there is a need to test multiple channels on a random basis and control the amount of time each channel, or group of channels, is under test. In some cases BERTs can be controlled over serial or parallel cables, but such devices do not offer the necessary degree of flexibility for adequate testing, for example, TDM busses, such as a STbus (Standard Telecom Bus).

An object of the invention is to alleviate this problem.

According to the present invention there is provided a device for use in the measurement of the bit error rate of a telecommunications channel, comprising a connector for insertion into a personal computer PC card slot for establishing communication with a PC bus; a pseudo random sequence generator for generating a pseudo random sequence in response to commands from said PC; and an output means for connection to a time division multiplexed telecommunications link for sending on at least one selected telecommunications channel a pseudo random sequence in response to program commands from said PC.

The connector is preferably designed to plug into a standard ISA/EISA/PCI connector of an IBM compatible PC. The computer can control the BERT, the TDM bus, and other devices on the TDM bus, permitting automatic test suites to be run under the control of software running on the PC.

More than one device can be installed on the PC at the same time, in which case each device can be individually controlled by separate programs running, on the PC.

The BERT preferably produces a pseudo random sequence based on the generator polynomial X15 + X14 + X2 + 1, although other sequences can of course be employed.

This sequence can be sent on a channel or group of channels over a telecommunications link, for example, a TDM bus. The sequence is then compared on a bit by bit basis with an identical sequence generated at the far end, where bit errors are recorded in a counter.

The BERT is suitable for standard industry backplanes, such as BNfVIP/MVIP/SCSA.

Since the BERT controlled by software running on the PC, it can be used to test individual channels, test groups of randomly selected channels, walk through many channels, and control the amount of time each channel is tested.

The invention also provides a method of measuring the bit error rate of a telecommunications channel, comprising the steps of providing a test device for insertion into a personal computer card slot, generating a pseudo random sequence in response to extemal program commands received from the personal computer, sending said pseudo random sequence in response to program commands received from said personal computer on at least one selected telecommunications channel on a time division multiplexed telecommunications link, and comparing a bit sequence received over said at least one selected channel with a locally generating pseudo random sequence synchronized with the transmitted sequence to determine the bit error rate of said at least one channel.

The invention will now be described in more detail, by way of example only, with reference to the accompanying drawings, in which:- Figure I is a generic block diagram showing a BERT in accordance with the invention; Figure 2 is a block diagram of a BERT transmitter; and Figure 3 is a block diagram of a BERT receiver.

In Figure 1, a standard IBM compatible PC I has a plurality of ISA/EISA/PCI peripheral slots in a known manner to permit the insertion of peripheral cards.

BERT 2 is mounted on a card adapted to be inserted into one of the peripheral slots through a plug-in connector 9 in a conventional manner. The BERT 2 has an output port 3 1 for connection to a TDM bus 4, which may be a ST bus or a MVIPdEVMP/SCSA telecorn bus. The far end of the bus 4 is connected to device under test DUT 5, which is in 5 tum connected to network 6 with loop back 7.

The BERT 2 also a pseudo random sequence generator 8, which generates a sequence I based on the generator polynomial X15+X14+X2+ 1.

Under software control the BERT 2 can place the pseudo random pattern in any combination of channels on the bus 4. The receivinc, device 5 contains a pseudo random CP sequence generator, which is synchronised to the transmit side. The received bits are XORed on a bit by bit basis with a pattern generated locally by the device 5. Device 5 includes a counter which is incremented every time a received bit is corrupted.

Figure 2 is a more block diagram of the transmitter of the BERT 2. The transmitter consists of the pseudo-random generator (PRG) 8, which receives a stream of I's and performs a modulo 2 division using a predetermined generator polynomial, for example, X15 + X14 + X2 + 1. The remainder of the division is output as a serial stream of bits. When the START input is low the PRG 8 is loaded with all Is and all Is are sent out as a serial stream. When the START input is pulled high, the PRG 8 produces random values. The first bit transmitted after the START input is pulled high must be 0 in order to synchronise the receiver. The random stream of bits is sent to on e of the input streams of a Mitel MT90820 diorital cross point switch 10, which is used to map the pseudo random ID pattern into the channels of a N4V]EPdB4VIP/SCSA bus 11 to be tested. Both the switch 10 and the START input to PRG 9 are controlled by the computer 1.

The receiver portion of the BERT is shown in Figure 3. PRG 15 is identical to PRG 8 in the transmitter. When the START input 16 is pulled low, the PRG 15 is loaded with the first value of the pseudo random sequence, which is the sequence that is transmitted by the transmitter after the START input 12 is pulled high. When the START input 16 is Z pulled high, the PRG 15 will remain frozen until a zero bit is received. At this time the PRG 15 will start cycling through the pseudo random sequence, and it will become Z;- synchronized to the PRG 8 in the transmitter section of the BERT. Synchronization detector 20 detects when synchronization occurs.

The received bit stream is received at the crosspoint switch 10, which is common to the transmitter, and exclusive ORed with the bit stream coming from the receiver PRG 16 in 4-:

exclusive OR aate 18 with the bit stream from the receiver PRG 15. Counter 19 is 1 incremented each time the bits of the two streams do not match.

Like the transmitter, the receiver operates under the control of the computer 1, which implements the following program steps:

1. Pull START low 2. Set up channel mapping in digital switch 3. Pull START high 4. Wait for synchronization detection logic 20 to assert synch signal 5. Wait for measurement period 6. Read counter 7. Calculate bit error rate (BER) from experssion BER = counter value/ measurement period.

8. Goto step 5 The BERT 3 may be implemented using ASIC/FPGA/CPLD or discrete TTL parts. It can be plugged into ISA/EISA slots or PCI slots and test MVIP/11MVIP/SCA. It also permits H. 1 00/H. 100 operation and can be used for other tests, such as digital milliwatt, fixed tones, or distortion measurement. It can generally be used for the test of telecom components connected to a standard TDM bus, the test of telecom. lines using s BERT a each end of the line remotely controlled by modem, test of CBR (Constant Bit Rate services) over ATM components with one tester at each end, loop back at an ATM switch or loop back at an ATM bus. It can also be used for automated test applications and remotely initiated tests. A remote PC can be controlled by modem.

When test are performed under loopback conditions, only one BERT is required. However, separate BERTs can be employed if they are located at opposite ends of a transmission medium. In this case, it is possible to set up full duplex monitoring where the transmitter of the near end BERT sends to the receiver of the far end BERT and vice versa.

Claims

Claims:

1. A device for use in the measurement of the bit error rate of a telecommunications channel, comprising a connector for insertion into a personal computer PC card slot for establishing communication with a PC bus; a pseudo random sequence generator for generating a pseudo random sequence in response to commands from said PC; and an output means for connection to a time division multiplexed telecommunications link for sending on at least one selected telecommunications channel a pseudo random sequence in response to program commands from said PC.

2. A device as claimed in claim 1, wherein said pseudo random sequence generator generates the sequence X15 + X14 + X2 + 1.

3. A device as claimed in claim 1, wherein said output means is responsive to program commands from said PC to test randomly selected channels.

4. A device as claimed in claim 1, wherein said output means is responsive to program commands from said PC to test randomly selected groups of charmels.

5. A device as claimed in claim 1, wherein said output means is responsive to program commands from said PC to sequentially walk through channels.

6. A device as claimed in claim 1, wherein said output means is responsive to program commands from said PC to control the amount of time each channel is tested.

7. A device as claimed in any one of claims I to 6, wherein said output means is a crosspoint switched controlled by said PC.

8. A device as claimed in claim 1, further comprising a receiver for comparing a received bit sequence with a locally generated bit stream matching said transmitted pseudo random sequence.

9. A device as claimed in claim 8, wherein said receiver includes an exclusive OR gate for performing an exclusive OR operation on said received bit sequence and said transmitted pseudo random sequence.

10. A device as claimed i1h claim 8, further comprising a counter for counter the number of mismatches of said received bit sequence with said transmitted pseudo random sequence.

11. A method of measuring the bit error rate of a telecommunications channel, comprising the steps of providing a test device for insertion into a personal computer card slot, generating a pseudo random sequence in response to external program commands received from the personal computer, sending said pseudo random sequence in response to program commands received from said personal computer on at least one selected telecommunications channel on a time division multiplexed telecommunications Link, and comparing a bit sequence received over said at least one selected channel with a locally generating pseudo random sequence synchronized with the transmitted sequence to determine the bit error rate of said at least one channel.

12. A method as claimed in claim 11, wherein said pseudo random sequence generator generates the sequence X15 +X14 + X2 + 1.

13. A method as claimed in claim 11, wherein said channels are tested at random.

14. A device as claimed in claim 11, wherein said channels are tested at random in groups-

15. A method claimed in claim 11, wherein said receiver an exclusive OR operation is performed on said received bit sequence and said transmitted pseudo random sequence to determine the number of mismatches.

16. A device for use in the measurement of the bit error rate of a telecommunications channel, substantially as hereinbefore described with reference to the accompanying drawings.

17. A method of measuring the bit error rate of a telecommunications channel, substantially as hereinbefore described with reference to the accompanying drawings.