GB2343980A

GB2343980A - Spatial light modulator and display

Info

Publication number: GB2343980A
Application number: GB9825152A
Authority: GB
Inventors: Jonathan Harrold
Original assignee: Sharp Corp
Current assignee: Sharp Corp
Priority date: 1998-11-18
Filing date: 1998-11-18
Publication date: 2000-05-24
Also published as: GB9825152D0

Abstract

An active matrix spatial light modulator is provided, for instance, for use in time sequential or other fast displays. The modulator comprises rows and columns of light-modulating pixels 23. Image data are supplied on data electrodes 4 and scan signals are supplied in sequence on scan electrodes 5 so that the modulator is refreshed a row at a time. Each light-modulating pixel comprises a picture element 10 of variable light attenuation and a storage capacitor 14. A first transistor switch 12 is connected between the data electrode 4 and the storage capacitor 14 and actuated by a scan signal on the scan electrode 5. A second transistor 11 is connected between the capacitor 14 and the picture element 10 and is actuated by a transfer signal received from a transfer signal generator 28 via the data electrode 4 or the scan electrode 5. Alternatively, the transfer signal may be sent along a separate electrode (13, fig 17) and may include a blanking signal to a blanking signal detector (61, fig 17) connected to a third transistor.

Description

SPATIAL LIGHT MODULATOR AND DISPLAY The present invention relates to a spatial light modulator and to a display incorporating such a modulator. Such modulators and displays may be used in fast liquid crystal displays, for instance of the time sequential type capable of operating at sufficiently high refresh rates to avoid visible flicker with rapidly changing images. Such displays may be used in time sequential colour displays and autostereoscopic three dimensional (3D) displays.

Thin film transistor twisted nematic (TFT TN) displays are commonly used as high quality direct view liquid crystal displays for operating at video rates, such as 60 fields or 30 frames per second. Such displays can be relatively large, for instance with a diagonal panel size of 15 to 20 inches (approximately 38 to 51 centimetres). Although such displays are capable of being refreshed with image data at the rate of 60 fields or 30 frames per second, the liquid crystal material does not respond at this rate. For example, typical liquid crystal materials have a typical on switching time of 30 milliseconds and a typical optical relaxation or off switching time of 50 milliseconds.

The display therefore responds to the root mean square (RMS) value of the video signal.

For static images or images which change relatively slowly, the visual performance is satisfactory. However, the visual performance deteriorates for more rapidly changing images, for instance corresponding to relatively rapid movements within a scene.

Such performance is completely inadequate for time sequential displays in which there must be minimal crosstalk between consecutive images. Although it may be possible to improve the switching speeds of materials for use in TFT TN displays, it is unlikely in the foreseeable future that response times of standard TN materials with 90 twist will be sufficiently fast for such displays to be used in time sequential applications.

Time sequential displays display images in a time sequential or time multiplexed manner and require that consecutive images be displayed with no visible crosstalk i. e. the image or remnant of the image displayed in the preceding field or frame should not be visible when the current image is being displayed. Such displays are required for time sequential colour applications and for 3D stereoscopic and autostereoscopic applications. The requirements for a time sequential colour display will be described and essentially the same considerations apply to 3D displays.

In a time sequential colour display, the colour filters, which are required for non-time sequential colour displays, are omitted, thus resulting in a saving in cost. Also, the same spatial resolution as for a non-sequential display may be achieved with one third of the number of picture elements (pixels) so that display complexity may be reduced. However, it is necessary to display the red, green, and blue image components at a sufficiently high rate for the eye to integrate the images without visible flicker. A 60 Hz refresh rate is generally considered to achieve this so that, for the same flicker-free performance in a time sequential colour display, the red, green and blue images require a display refresh rate of 180 Hz (or more). Thus, within each interval of the order of 5 milliseconds, it is necessary to complete the addressing of the whole display, to allow for the response of the liquid crystal material to the last row of image data (in the usual type of display which is scanned or refreshed one row at a time), and to illuminate the display.

Addressing of the display may take a significant portion of the available time period.

For example, 2 milliseconds are required to address a 1000 line display having a line address time of 2 microseconds. Using a liquid crystal effect which can respond in about 2 milliseconds, only ( (5-2)-2) = 1 millisecond of the time period is available for illumination. The fluorescent tubes which are generally used for display illumination have a finite start time and the tube phosphor has a decay time so that full illumination is only available for a portion of the available time interval. Although"fast"phosphors are available, they are generally of poorer efficiency than standard phosphors so that display power consomption has to increase in order tc maintain a desired brightness.

EP 0 660 297 discloses a time sequential display using a crystalline silicon backplate.

The display comprises the usual row and column matrix of pixels and Figure 1 of the accompanying drawings illustrates the circuit of each pixel. The liquid crystal element is illustrated by its capacitance CP and is effectively connected between ground (typically a front plate electrode) and the drain of a TFT field effect transistor 1, whose source is connected to a supply line 2. The gate of the transistor 1 is connected to the drain of another TFT field effect transistor 3 and to one terminal of a storage capacitor CS, whose other terminal is grounded. The source of the transistor 3 is connected to a data line 4, which is common to the pixels of the column, whereas the gate is connected to a scan line 5, which is common to the pixels of the row.

This display is refreshed in the conventional way one row at a time. Analogue data signals for the row to be refreshed are supplied on the data lines 4 and the scan line 5 connected to that row of pixels receives a scan signal for enabling the transistors 3. The storage capacitors CS are of smaller capacitance than the capacitance of the liquid crystal cells CP and so can be charged relatively rapidly, for example in comparison with other known arrangements in which the storage capacitor is in parallel with and of much greater capacitance than the capacitance of the liquid crystal cell. The transistors 1 act as source-follower buffers and charge the pixel capacitance CP from the supply line 2. The pixels therefore begin to switch as soon as the transistors 3 are enabled by the scan signal.

This arrangement allows the pixels to be refreshed relatively rapidly because of the relatively small storage capacitors CS, which reduce the RC load on the data lines. In fact, rapid addressing is necessary in order to make available a larger portion of the field or frame refresh time interval for displaying the image. The relatively high speed addressing therefore requires the use of crystalline silicon transistors 1 and 3 (which limit the sizes of display to less than that of a silicon wafer) but illumination must be terminated so as to avoid crosstalk between consecutive images as soon as the refresh cycle begins again. Further, in addition to the data and scan lines or electrodes 4 and 5, each pixel has to be connected to a supply line or electrode 2 and therefore requires three connections. Also, the threshold voltage of the transistors 1 suffers from substantial variations from pixel to pixel because of tolerances in manufacture. Thus, a given data signal may lead to different optical responses of the pixels as the threshold voltage varies from pixel to pixel. This would be particularly significant if the transistor were made of polysilicon in order to provide displays which were larger than silicon wafers.

US 5 225 823 discloses a field sequential liquid crystal display comprising a matrix of pixels, the circuit of one of which is illustrated in Figure 2 of the accompanying drawings. Each pixel comprises two changeover switches 6 and 7 whose implementation is not disclosed. The switches are controlled by signals on the scan electrode 5. The switch 6 is connected to the data electrode 4 which also supplies power at the appropriate time. In the position illustrated in Figure 2, the switch 6 connects the electrode 4 to the switch 7 whereas, in the alternative position, the switch 6 connects the electrode 4 to a supply terminal of an amplifier 8.

In the position shown in Figure 2, the switch 7 connects the storage capacitor CS to the switch 6 whereas, in the alternative position, the switch 7 connects the storage capacitor CS to the input of the amplifier 8. The output of the amplifier 8 is connected to the liquid crystal cell CP.

When the pixel is being refreshed, the switches 6 and 7 connect the electrode 4 to the storage capacitor CS which is thus charged in accordance with the data signal on the electrode 4. The switches 6 and 7 then disconnect the storage capacitor CS from the electrode 4 until refreshing of the storage capacitors CS of all of the pixels has been completed. Signals on all of the scan electrodes 5 then cause the switch 6 to connect to the supply input of the amplifier 8 to the electrode 4 and the switch 7 to connect the capacitor to the input of the amplifier 8. Power is therefore supplied to the amplifiers 8 of all of the pixels substantially simultaneously so that the charges on the pixel capacitors CP are updated"in parallel". The refresh cycle then starts again. Thus, while the storage capacitors CS of the pixels are being refreshed with the next field or frame of image data, the liquid crystal elements are intended to continue to display the image data from the preceding field or frame. During this period, the display may be illuminated by a suitable light source. The light source is extinguished during the "power phase"when the pixel capacitors CP are being updated and is illuminated again once the liquid crystal cells have responded. Thus, the display may be illuminated during a substantial portion of each frame refresh time interval whereas the pixels may be addressed at a slower rate than for the display illustrated in Figure 1 of the accompanying drawings. Also, the arrangement shown in Figure 2 appears to avoid the need for a third power supply connection to each pixel.

Power must be supplied to the amplifiers 8 via the data electrodes 4 during a separate power phase, which must last at least as long as the maximum response time of the liquid crystal material of the display. This extends the frame refresh time. Also, because all of the pixels are updated at the same time, there is a relatively very large instantaneous current supply requirement in order to supply the energy for establishing the desired charges on the pixel capacitances CP, which are much larger than the storage capacitors CS, and this must be met by the addressing arrangement. Although it is possible to divide the power phase into a number of sub-phases, during each of which a group of lines is updated, so as to distribute the current drain, this further increases the frame refresh time.

Although the arrangement shown in Figure 2 of the accompanying drawings does not appear to require a third connection to each pixel, the implementation of the amplifier 8 is not disclosed. The detailed implementation of the amplifier 8 is important because: it is required to maintain the voltage across the pixel when the supply input is disconnected by the switch 6; it must prevent a leakage path to ground which would discharge the pixel; and it must have a design which does not transfer variations in threshold voltage to the pixel.

In order to prevent degradation of the liquid crystal material of displays, it is common practice for the polarity of the voltage across the pixel capacitance to be inverted in alternate fields or frames. The previously described items of prior art do not disclose techniques for achieving this.

As far as it may be understood from US 5 225 823, the arrangement of Figure 2 seems primarily intended for use with ferroelectric liquid crystal (FLC) effects. FLC has both a binary (i. e. off/on with no intermediate grey level) effect and an unpowered storage effect. Extra considerations to circuit design apply when there is no intrinsic storage liquid crystal effect and an analog effect is required.

JP 8095526 discloses another arrangement for achieving"parallel"loading of a liquid crystal display. Figure 3 of the accompanying drawings illustrates the circuit arrangement of each pixel. The optically active area of the pixel is determined by an electrode 10 which is connected to the drain of an n type TFT field effect transistor 11. The source of the transistor 11 is connected to the drain of a similar n channel transistor 12 whose drain is connected to the data electrode 4. The gate of the transistor 12 is connected to the scan electrode 5 whereas the gate of the transistor 11 is connected to a transfer signal electrode 13 which is common to all of the pixels. A storage capacitor 14 is connected between ground and the connection between the source of the transistor 11 and the drain of the transistor 12.

During addressing of the pixels, the"load"transistors 11 are switched off by the voltage on the electrode 13. The pixels are addressed a row at a time by scan signals on the electrodes 5 so that the data signals charge the pixel storage capacitors 14. When the addressing cycle has finished, a transfer signal is supplied to the electrode 13 so that the load transistors 11 of all of the pixels are switched on and the pixel capacitance is charged from the storage capacitor 14 via the transistor 11. The transistors 11 are then switched off and the next addressing cycle begins.

This arrangement avoids the instantaneous current supply requirement of the arrangement shown in Figure 2 and does not suffer from pixel consistency problems caused by variations in transistor threshold voltages as in the arrangement of Figure 1.

However, each pixel requires three connections. The electrode 13 connected to each pixel requires extra crossovers which can result in pixel aperture reduction and a reduction in manufacturing yield.

According to a first aspect of the invention, there is provided an active matrix spatial light modulator comprising: a plurality of rows and columns of light modulating arrangements; a data signal generator connected to a plurality of data electrodes, each of which is connected to the arrangements of a respective column; a scan signal generator connected to a plurality of scan electrodes, each of which is connected to the arrangements of a respective row; and a transfer signal generator, each of the arrangements comprising a picture element of variable light attenuation, a capacitor, a first transistor switch connected between the capacitor and the data electrode to which the arrangement is connected and arranged to be actuated by a scan signal on the scan electrode to which the arrangement is connected, and a second transistor switch connected between the capacitor and the picture element and arranged to be activated by a transfer signal received from the transfer signal generator via the data electrode or the scan electrode to which the arrangement is connected.

The terms"column"and"row"as used herein are not intended to be limited to vertically extending columns and horizontally extending rows. Instead, the term"row" refers to each group of picture elements, which may extend in a vertical or horizontal line with respect to the normal orientation of the modulator or may be spatially arranged in any desired way and which receive the same scan signal. Similarly, the term "column"refers to a group of pixels which are connected to receive the same data signal and which may be arranged as a vertically or horizontally extending line of pixels or in any other spatial arrangement.

Each of the first and second transistor switches may comprise a thin film transistor.

Each of the first and second transistor switches may comprise a field effect transistor and the source-drain paths of the first and second transistor switches of each arrangement may be connected in series between the data electrode to which the arrangement is connected and the picture element.

The gate of the first transistor switch of each arrangement may be connected to the scan electrode which is connected to the arrangement.

The gate of the second transistor switch of each arrangement may be connected via a transfer signal detector to the scan electrode or the data electrode which is connected to the arrangement.

The transfer signal detector may comprise a voltage shifting circuit.

The second transistor switch may be of opposite conduction type to the first transistor switch of each arrangement and may have a gate connected to the scan electrode or the data electrode which is connected to the arrangement.

The second transistor switch may be of opposite conduction type to the first transistor switch of each arrangement.

According to a second aspect of the invention, there is provided an active matrix spatial light modulator comprising: a plurality of rows and columns of light modulating arrangements; a data signal generator connected to a plurality of data electrodes, each of which is connected to the arrangements of a respective column; a scan signal generator connected to a plurality of scan electrodes, each of which is connected to the arrangements of a respective row; and a transfer signal generator, each of the arrangements comprising a picture element of variable light attenuation, a capacitor, a first transistor switch connected between the capacitor and the data electrode to which the arrangement is connected and arranged to be actuated by a scan signal on the scan electrode to which the arrangement is connected, a second transistor switch connected between the capacitor and the picture element and arranged to be actuated by a transfer signal on a transfer signal electrode connected to the transfer signal generator, and a third transistor switch connected across the picture element and arranged to blank the picture element in response to a blanking signal on the transfer signal electrode.

The transfer signal electrode may be common to all of the arrangements.

Each of the first, second and third transistor switches may comprise a thin film transistor.

Each of the first, second and third transistor switches may a comprise a field effect transistor, the source-drain path of the first and second transistors of each arrangement may be connected in series between the data electrode to which the arrangement is connected and the picture element, and the source-drain path of the third transistor switch may be connected across the picture element in each arrangement.

The gate of the first transistor switch of each arrangement may be connected to the scan electrode which is connected to the arrangement and the gate of the second transistor switch of each arrangement may be connected to the transfer signal electrode.

The gate of the third transistor switch of each arrangement may be connected to the transfer signal electrode via a blanking signal detector.

The second and third transistor switches maybe of opposite conduction type and the gate of the third transistor switch may be connected to the transfer signal electrode.

The transfer signal generator may be arranged to supply a transfer signal to each of the arrangements after each frame of image data has been scanned into the capacitors.

The transfer signal generator may be arranged to supply the transfer signal substantially simultaneously to all of the arrangements.

The modulator may comprise a blanking signal generator for supplying the blanking signal before each transfer signal.

The modulator may comprise a blanking signal generator for supplying the blanking signal after each transfer signal.

The blanking signal generator may be arranged to supply the blanking signals simultaneously to all of me arrangements.

The picture elements may be capacitive.

The picture elements may comprise liquid crystal picture elements.

The picture elements may comprise surface mode nematic liquid crystal picture elements, such as pi-cells, Frederiks cells, or super twisted surface mode cells.

The picture elements may comprise smectic liquid crystal elements, such as thresholdless antiferroelectric liquid crystal picture elements.

The picture elements may be reflective or transmissive.

According to a third aspect of the invention, there is provided a time sequential display comprising a modulator in accordance with the first or second aspect of the invention and a light source.

The display may comprise a controller for illuminating the light source after each transfer signal and for extinguishing the light source before each next transfer signal.

The controller may be arranged to illuminate the light source with a delay after each transfer signal greater than or equal to the maximum time for the picture elements to respond to a change of image data.

The light source may be arranged to supply a repeating sequence of different colours.

The display may be of three dimensional type.

The light source may be arranged to supply light in different directions in different time periods.

It is thus possible to provide a spatial light modulator and display of the"parallel updating"type in which each field or frame can be displayed for a prolonged part of the refresh cycle. It is not necessary to use fast and more expensive addressing techniques and circuitry because the time available for illumination is not limited by the addressing speed. Also, because there is no"power phase", peak current requirements are reduced compared, for instance, with arrangements of the type shown in Figure 2 of the accompanying drawings. For instance, the peak current can be reduced by a factor of at least 200 and typically by a factor of 1000. The charge required by, for instance, liquid crystal pixels can be provided over an extended addressing period so that no special requirements need be placed on the addressing circuitry.

It is also possible to provide a spatial light modulator and display in which the configuration of signal paths through the transistors is such that variations in threshold voltage among the transistors and changes in threshold voltage with time do not substantially affect the performance of the modulator or display. Such variations and changes are a particular problem with thin film transistors and lead to undesirable or unacceptable degradation of performance, for example in arrangements of the type shown in Figure 1. In the case of modulators or displays where an analog liquid crystal effect is used to achieve grey scale capability and the difference between pixel voltages for addressing adjacent grey levels may be as little as lOmV, it is particularly important to avoid such variations and changes as these would be readily visible on the display.

It is further possible to provide an arrangement which allows bipolar data voltages to be applied to the pixels so as to achieve DC balance. This is generally necessary to avoid degradation of liquid crystal materials caused be a DC imbalance with time across liquid crystal pixels and may be achieved, for example, by periodically inverting the polarity of pixel addressing voltages.

In the first aspect, the transfer signal is supplied via the data or scan electrodes so that no extra connection is required at each pixel. The data and scan electrodes may therefore be conventional and there is no need to provide further electrodes with the requirements for crossovers and the consequent reduction in manufacturing yield and possibly aperture ratio.

In the second aspect, although an additional connection is required at each pixel, the functionality of the modulator can be improved by providing blanking of the display before or after refreshing.

Compact pixel circuitry can be provided and this allows high aperture transmissive panels to be made. Thus, although crystalline silicon backplates and reflective panels may be made, this is not necessary.

It is thus possible to provide fast spatial light modulators and displays which may operate in the time sequential mode. For instance, displays capable of operating at refresh rates suitable for colour sequential and 3D autostereoscopic applications can be provided.

The invention will be further described, by way of example, with reference to the accompanying drawings, in which: Figure 1 is a circuit diagram of a known pixel addressing arrangement; Figure 2 is a circuit diagram of another known pixel addressing arrangement; Figure 3 is a circuit diagram of a further known pixel addressing arrangement; Figure 4 is a block diagram of a colour sequential display constituting an embodiment of the invention; Figure 5 is a timing diagram illustrating operation of the display of Figure 4; Figure 6 is a cross-sectional diagram of an SLM of the display of Figure 4; Figures 7 and 8 are circuit diagrams of first and second addressing arrangements, respectively, for pixels of the display of Figure 4; Figure 9 is a graph of drain current against source-gate voltage for transistors for use in the arrangement of Figure 8; Figures 10 to 18 are circuit diagrams of third to eleventh addressing arrangements, respectively, for pixels of the display of Figure 4; Figure 19 is a diagrammatic plan view of a 3D display constituting an embodiment of theinvention; Figure 20 is a diagrammatic plan view of another 3D display constituting an embodiment of the invention; Figures 21a and 21b are diagrammatic plan views of micropolariser 3D displays constituting embodiments of the invention; Figure 22 is a diagram illustrating a switchable directional backlight for use in the displays of Figures 19 to 21; Figure 23 is a diagrammatic plan view of a shutter-glasses 3D display constituting an embodiment of the invention; and Figure 24 is a schematic diagram of another colour sequential display constituting an embodiment of the invention; Like reference numerals refer to like parts throughout the drawings.

Figure 4 shows a direct view transmissive display of the time-sequential type. The display comprises red, green and blue backlights 20 to 22 and a liquid crystal spatial light modulator of the surface mode nematic type. The spatial light modulator comprises data (column) electrodes 4 and scan (row) electrodes 5 connected to an array of pixels such as 23. Each column of pixels is connected to the same data electrode 4 whereas each row of pixels is connected to the same scan electrode 5.

The data electrodes 4 are connected to a column driver 24 which constitutes a data signal generator. The driver 24 has inputs for receiving, in serial format, image data to be displayed. The driver 24 also has a timing input connected to a system controller (incorporating a timing generator) 25 for receiving clock signals for controlling operation of the driver 24.

The scan electrodes 5 are connected to a multiplexer and row driver 26, which receives timing signals from the system controller 25. The multiplexer and row driver 26 has a first input connected to a scan/address controller 27 and a second input connected to a transfer/load controller 28, which optionally includes a blanking controller for embodiments in which a blanking function is provided. The controllers 27 and 28 receive timing and control signals from the system controller 25.

The backlights 20 to 22 are controlled by a backlight controller timer 29. The timer 29 receives timing and control signals from the system controller 25 and control signals from the controller 28.

Operation of the display shown in Figure 4 as a colour sequential display is illustrated by the graph and control signals shown in Figure 5. The display displays green, blue and red field or frame image data in a repeating sequence at a sufficiently fast repetition rate for the individual colour component images to be integrated by an observer. The vertical axis of the graph represents the number of the line of pixels currently being addressed whereas the horizontal axis represents time. During a first time interval from to to tl, the N lines of the display are addressed and refreshed a line or row at a time.

This is illustrated in Figure 5 as a ramp waveform but in practice each line is discretely refreshed. The first time interval is of NTg seconds, where Tg is the time required to address each individual row of pixels.

During this interval, the multiplexer and row driver 26 supplies the scan/address signals from the controller 27 to the scan electrodes 5. In particular, a scan signal is supplied to each of the electrodes 5 in turn and in synchronism with the row of pixel image data being supplied to the data electrodes 4 by the column driver 24. At the end of this interval, the system controller 25 causes the controller 28 to supply a transfer signal Ts which is in turn supplied by the multiplexer and driver 26 to all of the scan electrodes 5 simultaneously. As an alternative, several transfer signals may be supplied in sequence to groups of scan electrodes. The transfer signal Ts has a sufficient duration to ensure that the image data supplied to the pixels during the addressing interval are transferred so as to be displayed by the pixels 23.

The transfer signal Ts ceases at time t2, after which addressing of the next data phase, in this case blue, may begin. After a time interval Trw corresponding to the electro-optic material response time of the display, the pixels are displaying the green data.

Accordingly, at time t3, the backlight controller timer 29 illuminates the green backlight 21 so as to make the green image visible to an observer. The green backlight remains illuminated until or (so as to allow for the turn-off response time of the backlight, for example resulting from the phosphor decay time) immediately before time t4 corresponding to completion of addressing of the pixels with the blue image data. The green backlight is then extinguished and the next transfer signal Ts is supplied to the scan electrodes 5 so as to transfer the blue image data for display by the pixels 23. At time ts, the transfer signal ceases and the pixels are addressed with the red image data.

At time t6 when all of the pixels have had time to respond to the transferred blue data, the timer 29 illuminates the blue backlight 22 so as to display the blue image data.

In Figure 5, the timing of the illumination signal is illustrated. However, the timing may be adjusted to take account of different switch-on and switch-off characteristics of the illumination sources which are actually used. For example, the timing may be slightly different for the different colours so as to account for different response times of red, green and blue phosphors used in fluorescent lamps. It is also possible for the illumination to encroach into at least part of the liquid crystal response time Trw without substantial loss of contrast performance.

This process is repeated for the red image data so as to complete the display of a colour image. The frame cycle time F is thus given by 3 (NTg+Ts) and is preferably of the order of 20 milliseconds or less so as to prevent an observer perceiving flicker.

Figure 6 illustrates diagrammatically the structure of the spatial light modulator. A substrate 31 typically comprises glass but may alternatively comprise fused silica, quartz, a plastics material or silicon. An optional barrier layer 32 is formed on the substrate. A layer 33 is formed on the barrier layer 32 and contains addressing electrodes and circuitry, such as thin film transistors as described hereinafter, together with optional passivation and planarisation layers. A layer 34 is formed on the layer 33 and contains pixel pad electrodes in the form of transparent conductors, for instance made of indium tin oxide (ITO). Alternatively, for reflective displays, the conductor material may be reflective and may, for example, comprise aluminium. Such an aluminium reflector may have a polarisation preserving partially diffusing structure on its surface, for example as used in HR-TFT displays available from Sharp K. K. An alignment layer 35 is formed on the layer 34 for providing the desired alignment at one surface of a layer of liquid crystal 36. For liquid crystal modes which do not require alignment, the layer 35 maybe omitted.

A transparent substrate 37 (comprising glass, fused silica, quartz or a plastics material) carries an electrode layer 38 and an optional alignment layer 39. The layers adjacent the liquid crystal 36 are spaced apart and edge sealing is provided so as to confine the liquid crystal 36 to form a display cell. Optional polarisers 40 and 41 are formed on the exterior surfaces of the substrates 31 and 37 in accordance with the requirements of the mode of operation of the display. In reflective embodiments where the substrate 31 carries a reflector, the polariser 41 is not required. In such embodiments, at least one internal waveplate, such as a quarter waveplate, may optionally be provided between the polariser and the reflector.

The alignments layers 35 and 39, when present, are arranged to suit the electro-optic liquid crystal mode of the display and may, for instance, be arranged to produce planar alignment with defined pre-tilt, homeotropic alignment or a patterned alignment. The liquid crystal 36 may be a nematic or smectic material but is preferably a surface mode nematic material such as a pi-cell, a Frederiks cell or a super twisted surface mode cell, for example as disclosed in British Patent Applications Nos. 9712378.0 and 9811579. 3 and in European Patent Application No. 98304669.9. As an alternative, antiferroelectric liquid crystal or thresholdless antiferroelectric liquid crystal materials may be used as disclosed in GB 2 324 899 and EP 0 875 881. The liquid crystal may also use a thin and/or reduced twist angle twisted nematic effect or other liquid crystal effect with a response time of less than 5 milliseconds and preferably less than 2 milliseconds. Reducing the twist angle generally reduces the light throughput efficiency.

The structure and manufacture of the liquid crystal cell may be conventional and will not therefore be described further.

Figure 7 illustrates the addressing circuitry of a typical pixel 23 of the display shown in Figure 4. The addressing circuitry comprises transistors 11 and 12, a storage capacitor 14 and an electrode 10 as illustrated in Figure 3 and as described hereinbefore. The addressing circuitry differs from that illustrated in Figure 3 in that the gate of the transistor 11 is connected to a transfer signal detector 45 whose input is connected to the scan line 5 to which the gate of the transistor 12 is connected. The electrode 13 of Figure 3 is therefore omitted and, as described hereinbefore, transfer signals are supplied to the pixels 23 via the scan electrodes 5. The transfer signal detector 45 may make use of signal magnitude, polarity, pulse width or a combination thereof to perform discrimination between transfer and scan signals.

This addressing arrangement at each pixel 23 thus avoids the need for a third connection to the pixel. Such a third connection, for example as shown in Figure 3, requires space and may therefore reduce the maximum optical aperture of the pixels. Also, crossovers must be provided where such a third connection crosses over the other electrodes and the crossing electrodes must be insulated from each other. This complicates the manufacture of such devices and, because of failures occurring in the insulation, reduces the manufacturing yield of devices requiring third connections to the pixels. The circuitry illustrated in Figure 7 avoids these problems but requires a transfer signal detector 45 at each pixel 23. Such a detector may be provided in several ways and need not compromise the aperture or yield of the display as compared with the arrangement shown in Figure 3.

Figure 8 illustrates a specific form of the circuitry shown in Figure 7. The transistor 12 is of nMOS type whereas the transistor 11 is of pMOS type, so that the transistor and the detector 45 are embodied as the opposite conduction type of the transistor 11.

The polarity of the scan signals supplied to the electrodes 5 is such as to cause the transistor 12 to conduct so as to charge the storage capacitor 14 from the data electrode 4. However, the transistor 11 does not respond to the scan signal and remains switched off so as to isolate the pixel capacitance from the storage capacitor 14. When the storage capacitors 14 of all of the pixels 23 of the display have been refreshed, the transfer signal is supplied to all of the scan electrodes simultaneously. The polarity of the transfer signal is such as to switch on the transistors 11 whereas the transistors 12 remain switched off. Thus, the charges stored on the storage capacitors 14 of all of the pixels are simultaneously shared with the pixel capacitances formed by the pixel pad electrodes in the layers 34 and 38 and the intervening dielectric formed by the layers 35, 36 and 39. The storage capacitors may have a substantially higher capacitance than the pixel capacitors so that the voltage Vp appearing across the pixel capacitance is substantially equal to V51 (1+Cp/Cs), where Vs is the voltage across the storage capacitor 14, Cp is the pixel capacitance and Cs is the capacitance of the storage capacitor 14.

This expression is an approximation because the pixel capacitance Cp is a function of the pixel voltage and therefore varies during charge transfer. However, this can be corrected as part of the calibration of the pixel transmittance with voltage, generally referred to as"gamma correction".

Alternatively, the capacitance of the storage capacitor 14 may be of the same order as or even less than that of the pixel capacitance. In this case, a higher data signal voltage may be used so as to provide the desired charge on the pixel capacitance.

Thus, the transfer signal detection is implemented by the pMOS enhancement transistor 11. In normal operation, neither the positive going pulses nor the off level at the gate of the transistor 12 are sufficiently negative to turn the transistor 11 into conduction. The transfer signal is a very negative pulse applied to the scan electrode 5 which keeps the transistor 12 off and turns the transistor 11 into conduction. For the optimum operating range, the threshold value of the transistor 11 should be numerically large. This is contrary to the typical design requirement of a standard pMOS transistor where the threshold voltage has to be numerically minimised.

Figure 9 illustrates the performance of transistors which, in this case, are poly-silicon TFT's. The leakage of the pMOS transistor 11 is typically somewhat lower than that of the nMOS transistor 12 (not illustrated). This is important because the positive gate pulse for the transistor 12 must not cause substantial leakage in the transistor 11. This high voltage only exists for 1/N of the frame time. The leakage of the nMOS transistor 12 from the (higher magnitude) transfer pulse of the transistor 11 is not significant because it exists simultaneously with the turn on pulse to the transistor 11 for transferring the charge on the storage capacitor 14 to the pixel capacitance.

In operation, a scan pulse on the scan electrode 5 causes the signal on the data electrode 4 to be transferred via the transistor 12 to the storage capacitor 14. This transistor accurately transfers the data voltage Vdata provided some reasonable drain current can still flow (in the saturation region). The drain current ID in a field effect transistor may be approximated by: ID = k (VGs-Vr) 2 saturation region

linear region ID = k exp (VGs-VT)"sub-threshold"region where VGS is the gate-source voltage, VT is the threshold voltage and k is a constant dependent on the dimensions and mobility of the transistor and the oxide capacitance.

Thus, ID will remain reasonable for charging the pixel from the storage capacitance if VGS-VT > O, i. e. if the data voltage is applied to the source is such that: Vc > Vd+VT When Vdata is negative (in order to DC balance the liquid crystal), then a positive gate voltage still causes transfer of the data voltage as above, but now the gate voltage VG must be sufficiently negative to give an"off condition". Thus, in the sub-threshold regime, to have a reasonably negative exponential, VGS should be a small amount a less than VT where ~9 : VGS < VT1 - α #VG < VT1 - α + Vs #VG < VT1 - α - | Vdata| To keep the pMOS transistor 11 off when Vdaia is a maximum positive: VGS > VT2 + a = > VG > VT2 + a + V, #VG > VT2 + α + |Vdata| VT2 + + |Vdata| < VG < VT1 -α- |Vdata| Therefore for VG to have a non-zero range: VT1-VT2 > 2( |Vdata|+α) As VT2 is negative, the sum of the moduli of the threshold voltages needs to be greater than the total data voltage swing. Therefore a strong incentive exists to have a lowvoltage operating liquid crystal material (e. g. +/-3.5V or below). This is illustrated in Figure 9 graphically.

Figure 10 illustrates another type of pixel circuitry in which the pixel capacitance is shown at CP and the transfer signal detector comprises the combination of the opposite conductivity transistor 11 and a voltage source 48 connected between the gate of the transistor 11 and the scan electrode 5. The voltage source 48 provides a shift in the voltage at the gate of the transistor 11 compared with the voltage at the scan electrode 5 so as to maintain the transistor 11 switched off during the negative part of the gate signal supplied to the transistor 12. This also increases the magnitude of the negative voltage which must be applied to cause the transistor 11 to switch on. Such an arrangement allows a reduction in the magnitude of the threshold voltage of the transistor 11.

Figure 11 illustrates a specific form of the voltage shifting circuit 48. In particular, diodes 49 and 50 are connected in series between the gate of the transistor 11 and the scan electrode 5. The connection between the gate of the transistor 11 and the diode 49 is connected via a resistor 51 to a bias voltage source 52 shown schematically as a battery. The bias voltage may be positive or zero and may be provided by a connection to the ground connection of the storage capacitor 14 or by filtering or averaging the voltage on the data electrode 4. As there is no effective circuit current path into the gate of the transistor 11, the resistor 51 and the source 52 provide sufficient current flow for the diodes 49,50 to establish a potential drop. The resistor 51 may have a large value.

The arrangement shown in Figure 12 differs from the shown in Figure 11 in that the diodes 49 and 50 are replaced by a transistor 53 connected as a source-drain diode. Any number of such transistors may be connected in series to provide the desired voltage shift and Figure 13 illustrates an arrangement in which two transistors 53 and 54 are connected in series.

Figure 14 illustrates an arrangement which differs from that shown in Figure 8 in that the types of the transistors 11 and 12 are exchanged so that the transistor 11 is an nMOS type and the transistor 12 is a pMOS type. In this arrangement, the average voltage on the scan electrode 5 is more positive than in the arrangement of Figure 8 and this may be used as a source of the bias voltage for arrangements of the type shown in Figures 11 to 13.

Figure 15 illustrates an arrangement in which the input of the transfer signal detector 45 is connected to the data electrode 4 and the transfer signals are supplied via the data electrodes to the pixel 23. The detector 45 may discriminate between the data and transfer signals on the basis of magnitude, polarity, pulse width or a combination thereof. Figure 16 illustrates an arrangement in which the detector 45 is embodied by the opposite conduction type of the transistor 11 compared with the transistor 12 and as described hereinbefore with reference to Figure 8.

Figure 17 illustrates an arrangement in which the transistors 11 of the pixels 23 are connected to a separate common transfer signal electrode 13 in the same way as the known arrangement illustrated in Figure 3. However, the arrangement shown in Figure 17 differs from the known arrangement in that a discharge transistor 60 is provided with its source-drain path connected across the electrodes of the liquid crystal pixel. The gate of the transistor 60 is connected to the electrode 13 via a blanking signal detector 61. With such an arrangement, the controller 28 supplies the transfer signal and a blanking signal to all of the pixels 23 via the common electrode 13.

Operation of the this type of display differs from that described hereinbefore in that the pixel capacitance is discharged by the transistor 60 in response to the blanking signal detected by the detector 61 so that the whole display is blanked before the charges on the storage capacitors 14 are transferred via the transistors 11 in response to the common transfer signal to the pixel capacitance. Such blanking before updating the image may provide faster acquisition of the new pixel values with some electro-optic effects. It is also possible to blank the display a relatively short time after the pixels 23 have displayed a new image. Such a mode of operation more closely simulates the time update behaviour of a cathode ray tube phosphor and may give improved appearance for fast-moving objects in a sequence of images.

As illustrated in Figure 18, the transfer signal detector 61 may be provided by the transistors 11 and 60 being of opposite conduction types. This is similar to the arrangement illustrated in Figure 8 and will not therefore be described further. Also, the blanking signal detector 61 may be embodied in the same way as the transfer signal detector as illustrated in Figures 10 to 13. Also, the conductivity types of the transistors 11 and 60 may be reversed, as may the conductivity type of the transistor 12.

Figure 19 illustrates an autostereoscopic display using a spatial light modulator (SLM) 65 as described hereinbefore. The SLM 65 cooperates with a switchable directional backlight 66 so as to permit the simultaneous viewing of several different views, indicated as V1 to V7 in the drawing, by observers such as 67a and 67b. The SLM 65 is controlled in synchronism with the backlight 66 such that each of the views is only visible in a restricted region of space. Thus, the SLM 65 displays image data for the view V1 when the backlight 66 illuminates the SLM 65 so that the image is visible in the tapered region of space indicated at 68. The backlight 66 is then extinguished and the SLM 65 is refreshed with image data for the view V2. When the image has been transferred to the pixels of the SLM 65, the backlight 66 is again illuminated so as to direct light into the region 69. This process is repeated for each of the views in sequence sufficiently rapidly for flicker to be substantially invisible to an observer.

The views V1 to V7 of an object or scene are reproduced in the directions from which they were recorded during image capture or generated by a computer graphics system.

Accordingly, the observer 67 sees the views Vl and V2 with the right and left eyes, respectively, in the way he would have seen the object or scene itself. As the observer moves laterally with respect to the display, the views which are visible to the left and right eyes change so as to maintain the 3D appearance and to provide a look-around facility.

Figure 20 illustrates another autostereoscopic 3D display of a type similar to that disclosed in EP 0 576 106 but using the SLM 65 and the switchable directional backlight 66 as shown in Figure 19. This display is capable of supplying 3D images to several independent observers such as 67a, 67b and 67c at the same time. An observer tracking system (not shown) for determining the positions of the observers 67a, 67b, 67c controls the SLM 65 and the backlight 66 so as to form viewing windows such as 70 to 75 which independently track each of the observers. The views displayed by the SLM 65 are synchronised with the operation of the switchable directional backlight 66 so that each observer perceives a 3D image. Although the left and right eye views may be the same for each observer, the SLM 65 is capable of being refreshed sufficiently quickly for different observers to see different 3D views. For example, this may be used to provide a look-around facility in the same way as the display shown in Figure 19. However, the display illustrated in Figure 20 does not need to generate and display views in locations where no observer is present. Both colour and view information or either or part thereof may be multiplexed to each observer in a time sequential manner with any remaining information for each view being produced by spatial multiplexing.

With this arrangement and multiple viewers, it is preferable to avoid lobe generation.

Figure 21 a illustrates a stereoscopic 3D display of the micropolariser type, for example as disclosed in EP 0 721 132. The display comprises an SLM 65 and a backlight 66 of the type illustrated in Figures 19 and 20. However, the SLM 65 comprises an output micropolariser 76 comprising two sets of interlaced regions or elements providing orthogonal output polarisations. The pixels of the SLM 65 display pairs of stereoscopic 3D images in a spatially multiplexed way such that light from the pixels displaying the left eye image pass through polarising elements 76a whereas light from pixels displaying the right eye image pass through polarising elements 76b. The elements 76a and 76b may be linear polarisers or circular polarisers but provide orthogonal output polarisations.

In order to view the stereoscopic images correctly, the observers are provided with polarising glasses comprising a left eye polariser such as 77 and a right eye polariser 78.

The polariser 77 transmits light from the elements 76a and blocks light from the elements 76b of the micropolariser 76 whereas the polariser 78 transmits light from the elements 76b but blocks light from the elements 76a. The left and right eyes of each observer therefore see only the left and right eye images, respectively, displayed by the SLM 65.

The display shown in Figure 21a may be operated in substantially the same way as that shown in Figure 20, namely to provide independent viewing information for each of the observers 67a, 67b and 67c. However, whereas the individual eye views for the observers are provided time-sequentially by the display of Figure 20, the left and right eye views for each observer are provided simultaneously by spatial multiplexing in the display of Figure 21 a. The pairs of images for the individual observers are provided time-sequentially in the display of Figure 21a. Thus, by utilising the spatial resolution of the SLM 65 in the display of Figure 21a, the addressing rate requirement of the SLM 65 may be reduced.

The display shown in Figure 21b is of the same general type as that shown in Figure 2 la but differs in that the micropolariser 76 which is external to the SLM 65 in Figure 21a is replaced by an equivalent arrangement which is internal to the SLM 65 of Figure 21b.

This arrangement comprises an internal polariser 76c and a waveplate array 76d. The internal polariser 76c acts as an ouput linear polariser whereas the waveplate array 76d acts as a patterned polarisation rotator. In particular, the array 76d comprises two sets of alternating regions such that the polarisation of light emerging from the regions of one set is substantially orthogonal to the polarisation of light emerging from the regions of the other set. As in the display of Figure 21 a, the polariser 77 transmits light from one set of regions and blocks light from the other set of regions whereas the polariser 78 transmits light from the other set of regions and blocks light from the one set of regions.

Figure 22 illustrates diagrammatically a compact directional backlight which may be used as the backlight 66 in the displays shown in Figures 19 to 21. The backlight 66 may be of the type disclosed in GB 2 317 710 and EP 0 833 183 and/or EP 0 656 555.

The upper part of the drawing illustrates a 3D mode of operation. The backlight comprises a plurality of imaging elements in the form of a lenticular screen 87 cooperating with a light source in the form of a plurality of parallel strip emitting regions. The lateral positions of the strip emitting regions are controllable relative to the lenticular screen 87 so as to control the output direction of the backlight 66. For example, the strip emitting regions may be defined by a plurality of moveable slits cooperating with a compact extended rear light source. The slits may be provided by a spatial light modulator of the liquid crystal type so as to provide a switchable directional backlight without moving parts.

A 2D mode of the backlight is illustrated at 66a in Figure 22. In this mode, a nondirectional or diffused backlight is required and this may be achieved by removing or disabling the strip light sources. Where these are provided by a liquid crystal SLM, the SLM may be controlled so as to be transparent to permit the transmission of light across the whole of its area.

Figure 23 shows a 3D stereoscopic display of the"shutter glasses"type. The display comprises an SLM 65 provided with a non-directional backlight (not shown). Each observer is provided with a pair of shutter glasses comprising left and right eye shutters such as 80 and 79, respectively. The SLM 65 displays the views for each eye of each observer time sequentially and the shutters 79 and 80 are opened in synchronism with the display by the SLM 65 of the view intended for the corresponding eye of the respective observer. By correct phasing of the display and the shutters of each independent observer, such an arrangement allows independent observers to see different views, for instance so as to provide a look-around facility. However, the display may be operated so that all of the observers see the same information, in which case the operation of the left and right eye shutters of the observer glasses are synchronised and the SLM 65 provides single left and right views in a time-sequential manner.

In the case of colour sequential displays, the multi-colour backlight may be of the filter wheel type as illustrated diagrammatically in Figure 24. A light source 81 providing light of more than one colour band, preferably white light, is provided with a system 82 for collimation, optional harmonisation and/or polarisation conversion. Light passes through a colour filter wheel 83 which typically comprises radial sections of different colour filter bands. The wheel 83 is rotated by a suitable system 86 and is appropriately synchronised with the image display. A spatial light modulator of the type described hereinbefore is shown at 84 and a projection optical system is shown schematically at 85.

Claims

CLAIMS : 1. An active matrix spatial light modulator comprising: a plurality of rows and columns of light modulating arrangements; a data signal generator connected to a plurality of data electrodes, each of which is connected to the arrangements of a respective column; a scan signal generator connected to a plurality of scan electrodes, each of which is connected to the arrangements of a respective row; and a transfer signal generator, each of the arrangements comprising a picture element of variable light attenuation, a capacitor, a first transistor switch connected between the capacitor and the data electrode to which the arrangement is connected and arranged to be actuated by a scan signal on the scan electrode to which the arrangement is connected, and a second transistor switch connected between the capacitor and the picture element and arranged to be actuated by a transfer signal received from the transfer signal generator via the data electrode or the scan electrode to which the arrangement is connected.
2. A modulator as claimed in claim 1, in which each of the first and second transistor switches comprises a thin film transistor.
3. A modulator as claimed in claim 1 or 2, in which each of the first and second transistor switches comprises a field effect transistor and the source-drain paths of the first and second transistor switches of each arrangement are connected in series between the data electrode to which the arrangement is connected and the picture element.
4. A modulator as claimed in claim 3, in which the gate of the first transistor switch of each arrangement is connected to the scan electrode which is connected to the arrangement.
5. A modulator as claimed in claim 4, in which the gate of the second transistor switch of each arrangement is connected via a transfer signal detector to the scan electrode or the data electrode which is connected to the arrangement.
6. A modulator as claimed in claim 5, in which the transfer signal detector comprises a voltage shifting circuit.
7. A modulator as claimed in claim 4, in which the second transistor switch is of opposite conduction type to the first transistor switch of each arrangement and has a gate connected to the scan electrode or the data electrode which is connected to the arrangement.
8. A modulator as claimed in claim 5 or 6, in which the second transistor switch is of opposite conduction type to the first transistor switch of each arrangement.
9. An active matrix spatial light modulator comprising: a plurality of rows and columns of light modulating arrangements; a data signal generator connected to a plurality of data electrodes, each of which is connected to the arrangements of a respective column ; a scan signal generator connected to a plurality of scan electrodes, each of which is connected to the arrangements of a respective row; and a transfer signal generator, each of the arrangements comprising a picture element of variable light attenuation, a capacitor, a first transistor switch connected between the capacitor and the data electrode to which the arrangement is connected and arranged to be actuated by a scan signal on the scan electrode to which the arrangement is connected, a second transistor switch connected between the capacitor and the picture element and arranged to be actuated by a transfer signal on a transfer signal electrode connected to the transfer signal generator, and a third transistor switch connected across the picture element and arranged to blank the picture element in response to a blanking signal on the transfer signal electrode.
10. A modulator as claimed in claim 9, in which the transfer signal electrode is common to all of the arrangements.
11. A modulator as claimed in claim 9 or 10, in which each of the first, second and third transistor switches comprises a thin film transistor.
12. A modulator as claimed in any one of claims 9 to 11, in which each of the first, second and third transistor switches comprises a field effect transistor, the source-drain paths of the first and second transistors of each arrangement are connected in series between the data electrode to which the arrangement is connected and the picture element, and the source-drain path of the third transistor switch is connected across the picture element in each arrangement.
13. A modulator as claimed in claim 12, in which the gate of the first transistor switch of each arrangement is connected to the scan electrode which is connected to the arrangement and the gate of the second transistor switch of each arrangement is connected to the transfer signal electrode.
14. A modulator as claimed in claim 13, in which the gate of the third transistor switch of each arrangement is connected to the transfer signal electrode via a blanking signal detector.
15. A modulator as claimed in claim 13, in which the second and third transistor switches are of opposite conduction type and the gate of the third transistor switch is connected to the transfer signal electrode.
16. A modulator as claimed in any one of the preceding claims, in which the transfer signal generator is arranged to supply a transfer signal to each of the arrangements after each frame of image data has been scanned into the capacitors.
17. A modulator as claimed in claim 16, in which the transfer signal generator is arranged to supply the transfer signal substantially simultaneously to all of the arrangements.
18. A modulator as claimed in claim 16 or 17 when dependent on any one of claims 9 to 15, comprising a blanking signal generator for supplying the blanking signal before each transfer signal.
19. a modulator as claimed in claim 16 or 17 when dependent on any one of claims 9 to 15, comprising a blanking signal generator for supplying the blanking signal after each transfer signal.
20. A modulator as claimed in claim 18 or 19, in which the blanking signal generator is arranged to supply the blanking signal simultaneously to all of the arrangements.
21. A modulator as claimed in any one of the proceeding claims, in which the picture elements are capacitive.
22. A modulator as claimed in any one of the proceeding claims, in which the picture elements comprise liquid crystal picture elements.
23. A modulator as claimed in claim 22, in which the picture elements comprise surface mode nematic liquid crystal picture elements.
24. A modulator as claimed in claim 23, in which the picture elements comprise picells.
25. A modulator as claimed in claim 23, in which the picture elements comprise Frederiks cells.
26. A modulator as claimed in claim 23, in which the picture elements comprise super twisted surface mode cells.
27. A modulator as claimed in claim 22, in which the picture elements comprise smectic liquid crystal picture elements.
28. a modulator as claimed in claim 27, in which the picture elements comprise thresholdless antiferroelectric liquid crystal picture elements.
29. A modulator as claimed in any one of the proceeding claims, in which the picture elements are reflective.
30. A modulator as claimed in any one of claims 1 to 28, in which the picture elements are transmissive.
31. A time sequential display comprising a modulator as claimed in any one of the preceding claims and a light source.
32. A display as claimed in claim 31, comprising a controller for illuminating the light source after each transfer signal and for extinguishing the light source before each next transfer signal.
33. A display as claimed in claim 32, in which the controller is arranged to illuminate the light source with a delay after each transfer signal greater than or equal to the maximum time for the picture elements to respond to a change of image data.
34. A display as claimed in claim 32 or 33 of colour sequential type, in which the light source is arranged to supply a repeating sequence of different colours.
35. A display as claimed in any one of claims 32 to 34 of three dimensional type.
36. A display as claimed in claim 35, in which the light source is arranged to supply light in different directions in different time periods.