GB2342824A - Signal flow control for a unidirectional differential data link - Google Patents

Abstract

A data communication device includes a data latch (3) which can receive and temporarily store digital data in the form of a parallel multi-bit data signal; a serialiser (4) which is operative to convert a data signal in the latch into serial form; a differential line driver (5) which transmits data as a time varying difference voltage between two transmission lines; and means (14,15) for sensing when the voltage between said two lines (6,7) is outside a predetermined range. The lines may be bridged adjacent the line driver by an impedance (11) substantially greater than an impedance presented to the line driver by said transmission lines. A receiver (2) may include a differential input amplifier (9), of which the input is connected to said two transmission lines, and across the said input a branch (12,13) which can be switched between a low impedance state and a high impedance state. The output signal on line 16 is used to initiate corrective measures, such as re-transmission of a current word stored in latch (3) or re-synchronisation of the data to be transmitted. Transistor switch (13) is opened e.g. by congestion or by loss of synchronisation.

Description

SIGNAL FLOW CONTROL FOR A UNIDIRECTIONAL DIFFERENTIAL DATA LINK This invention relates to the control of signal flow from one digital data communication device to another and is particularly concerned with an improved technique for implementing'flow control'in data communication networks so as to prevent, at least temporarily, the flow of data over the link and to enable, if desired, various forms of signalling which may be associated with that flow control.

Background to the Invention It is customary to transmit data in, for example, data communication networks, from one device to another at a high rate over a serial unidirectional link. In order to transfer data over such a link, it is customary to read data words, i. e. multi-bit digital signals into a temporary store, herein termed'latch', and to convert the multi-bit signals successively fed to the latch into serial form by means of a serialiser which may be operated in known manner. The serial data is applied to a buffer amplifier which is preferably constituted by a differential line driver, which is coupled to twin transmission paths which at a receiving device are coupled to the differential inputs of an input buffer constituted by any suitable form of differential amplifier. Thereafter the serial data may be converted to parallel format and may be processed or directed according to the requirements of the transmission system.

For a variety of reasons, for example congestion at a receiving device or loss of synchronisation, it is necessary from time to time to institute some form of flow control, namely the temporary cessation of data flow. Additionally or alternatively it may be necessary to provide a signal indicating loss of synchronisation. For example, in our earlier British patent applications numbers 9806748.1 and 9806747. 3 filed 30 March 1998 we describe various schemes for transmitting data serially on each of a plurality of parallel lines and for achieving, in a manner not directly relevant to the present invention, synchronisation of the data thereby transmitted. Loss of mutual synchronisation at the receiver of data transmitted over those multiplicity of lines may be an occasion for signalling back to the transmitter flow control.

In a system wherein a link between communication devices is bidirectional, conditions at the receiver justifying flow control may be signalled from the receiver to the transmitter. However, it is common for such schemes to require substantial buffer space at the receiver and possibly programming time by a central processing unit in order to provide the signal commanding flow control.

The object of the present invention is to provide an expedient form of signalling to institute flow control or to indicate loss of synchronisation particularly for unidirectional low voltage differential data links.

Summarv of the Invention The basis of the present invention is the use of a differential line driver at the transmitter to provide an output which is substantially independent of load impedance, the monitoring of voltage across the differential output by means of a differential amplifier and indicating if the differential line voltage is outside a predetermined range and in particular exceeds some predetermined value. The indication may be employed to cause re-transmission of a current word stored in the latch, or to institute other actions such as re-synchronisation of the data to be transmitted and so on. The paths to which the line driver is connected may be bridged by a shunt impedance of substantially higher value than that of the said paths and any normal termination of them.

At the receiving end of the link, there may be a differential input amplifier across the input to which is disposed a branch which is very much lower in impedance than the said shunt impedance and which can be put into a high impedance state, for example by means of a transistor switch, so that the output buffer works into an output impedance substantially higher than the impedance it sees when the transmission paths are normally terminated. The consequent increase in the voltage between the two transmission paths can be sensed by the differential amplifier of the transmitter and compared with the relevant threshold to develop the output flow control signal as desired.

It is possible under normal circumstances to reduce buffer sizes at the receiver and the scheme can be implemented without requiring any additional connection from the destination device or chip back to the transmitter or source chip.

Brief Description of the Drain ; s Figure 1 is an explanatory diagram illustrating a generally known form of unidirectional data link ; and Figure 2 illustrates an embodiment of the invention applied to such a data link.

Detailed Description Figure 1 illustrates a known form of unidirectional data link between a transmitter, for example a source chip 1, and a receiver, for example constituted by a destination chip 2. Data may be transmitted over the link at rates typically well in excess of one megabit per second, such as approximately one gigabit per second.

Typically, the source 1 has a FIFO (first-in, first-out) buffer which may hold a multiplicity of data words in parallel form. Words may be read out from that buffer at a desired rate and according to some desired scheme successively into a latch 3 constituting a store wherein each word is temporarily held while the data therein is converted into a serial data stream by means of a serialiser 4. Such serialisers are well known. The serial data output from the serialiser is coupled to the input of an output buffer amplifier 5 constituted by a differential line driver which provides a differential voltage between two output lines 6 and 7. The lines are customarily terminated at the receiving end by a termination resistor 8, which may be selected so that the impedance looking forwards into the link (shown by arrow A) from the output buffer corresponds to the termination impedance At the destination 2, the twin lines may be coupled to a differential amplifier 9 which may convert the differential input into a'single-ended'output (10) for conversion, as desired, into whatever form the destination chip or devices connected thereto may need.

Figure 2 illustrates a modification according to the invention.

In the system shown in Figure 2, an impedance preferably in the form of a high value resistor 11 is disposed across the lines 6 and 7. At the destination, there is a switchable branch comprising a resistor 12 and a transistor switch 13. Preferably the impedance (and normally the resistive impedance Ra) ouf impedance 11 is very much greater than RB, that of impedance 12 and preferably the impedance of the branch 12,13 corresponds to the ordinary termination impedance that would be used in the system shown in Figure 1.

Provided that the line driver produces an output current, lid,, which is substantially independent of the output impedance, the voltage across the lines 6 and 7 will be substantially increased when the transistor switch opens such that the output buffer 5'sees'the high impedance RA rather than the much lower impedance looking into the link when it is terminated with the resistor 12.

The voltage across lines 6 and 7 is coupled to a differential amplifier 14 of which the output is connected to one input of a comparator 15 which compares that output with a threshold.

Should the comparator detect an over-voltage, as determined by the aforesaid threshold, it may produce an output signal on a line 16. This output signal may be used to command the retransmission of a current word or to initiate some other action. For example, the transistor switch 13 at the destination may be opened by a variety of circumstances, such as congestion or loss of synchronisation between a multiplicity of channels, and accordingly the signal on line 16 may be used to initiate a corresponding variety of corrective measures.

The over-voltage may be detected indirectly. For example, the analog voltage detected by the amplifier may be decoded, whereupon it will yield a digital word (such as all 1's) that will differ from the word applied to the input of the amplifier 5. A comparison of the two words will provide the required indication. Furthermore, the means for modifying the impedance at the receiving end of the link may take other forms, such as means for circuiting the lines.

Claims (4)

1. CLAIMS 1 A data communication device which includes : a data latch which can receive and temporarily store digital data in the form of a parallel multibit data signal ; a serialiser which is operative to convert a data signal in the latch into serial form; a transmitting stage which transmits data as a time varying difference voltage between two transmission lines, the stage being constituted by a line driver providing an output current substantially independent of the load impedance; and means for sensing when the voltage between said two lines is outside a predetermined range.
2. 2. A data communication device according to claim 1 wherein said means for sensing includes a differential amplifier of which the input is connected to said two transmission lines.
3. 3. A data communication device according to claim 1 or claim 2 wherein said lines are bridged adjacent the line driver by an impedance substantially greater than an impedance presented to the line driver by said transmission lines.
4. 4. A data communication system comprising a device according to any of claims 1 to 3 and further comprising a receiver including a differential input amplifier, of which the input is connected to said two transmission lines, and across the said input a branch which can be switched between a low impedance state and a high impedance state.