KR950012320B1 - Image interface unit of atm adaptation layer for constant bitrate image service - Google Patents

Abstract

The device comprises a video connecting unit for connecting an image signal; a first pre-input/pre-output unit for storing the image information in connection with the video connecting unit; a second pre-input unit for storing ATM adaptation layer-service data unit transmitted from the first pre-input/pre-output unit and a dividing and recoupling header, transmitting ATM layer adaptation layer-protocol data unit to the ATM layer, or dividing the ATM layer adaptation layer-protocol data unit into the header and the ATM adaptation layer-service data unit; a buffer controlling unit for monitoring the storage state in connection with the first and second pre-input unit and controlling the pre-output unit; a first counting unit for counting a count driving signal outputted from the buffer controlling unit; a division and recouple header generating unit for receiving the count signal and transmitting the dividing and recoupling header to the second pre-input unit; a division and recouple header detecting unit for receiving the output of the first counting unit and detecting the dividing and recoupling header among data transmitted from the division and recouple header generating unit and the second pre-input unit; and an image data compensating unit for compensating a damage data by checking an output order number of the division and recouple header detecting unit and transmitting the compensated data to the second pre-input unit.

Description

Video access device of asynchronous delivery mode adaptation layer for accommodating fixed bit rate video service

1 is a block diagram according to the present invention.

2 is a block diagram of a video codec connection circuit.

3 is a block diagram of transmission and reception of a first FIFO.

4 is a block diagram of transmission and reception of a second FIFO.

5 is a block diagram of a buffer control circuit.

6 is a block diagram of a separation and recombination header generation circuit.

7 is a block diagram of a detach and recombine header detection circuit.

8 is a block diagram of an image data compensation circuit.

9 is a block diagram of a counter circuit.

* Explanation of symbols for main parts of the drawings

1: Video codec connection circuit 2: First FIFO

3: second FIFO 4: buffer control circuit

5: counter circuit 6: disconnect and recombination header generating circuit

7 separation and recombination header detection circuit 8 image data compensation circuit

The present invention provides a fixed bit rate video service in an ATM network among asynchronous transfer mode (hereinafter referred to as 'ATM') service according to the International Telegraph and Telephone Advisory Committee (CCITT) recommendation of the broadband information transmission mode. A video service access device in an ATM adaptation layer.

In broadband broadband telecommunications network, the user's data is first transformed from ATM adaptation layer to deliver 53-byte ATM cell in packet form needed by ATM network to provide fixed bit rate video service. There is a need for a video access device that transforms into an ATM adaptation layer-protocol unit. That is, the fixed bit rate video data transmitted from the video codec should be reconstructed into the data format for the fixed bit rate video service recommended by CCITT.

Accordingly, the present invention provides a 4-bit sequence number field generated by a 47-byte ATM adaptation layer-service data unit and an ATM adaptation layer in which digital signal level 3 (DS3) image information transmitted from a video codec of a fixed bit rate is transmitted. A 4-bit sequence protection field for protection is transmitted in conjunction with the separation and reassembly header, and when received, the pure video data transmitted from the video codec and the ATM adaptation layer are separated by restoring the ATM-protocol unit in order by referring to this sequence number. And an asynchronous transmission mode adaptation layer video access device for accommodating a fixed bit rate video service to transmit and receive user information of a fixed bit rate video codec by sequentially connecting or disconnecting a recombination header.

The present invention devised to achieve the above object comprises: video codec connection means for connecting a video signal from a video codec; First-in first-out means connected with the video codec connection means to store image information and to indicate a storage state; ATM Adaptation Layer-Protocol Data Unit (AAL) by storing an ATM Adaptation Layer-Service Data Unit (AAL-SDU) and a Separation and Reassembly (SAR) header connected to the first-in, first-out, and transmitting from the first-in, first-out, means. PDUs) and send them to the ATM layer, or separate ATM adaptation layer-protocol data units (AAL-PDUs) sent from the ATM layer into separate and recombination headers and ATM adaptation layer-service data units (AAL-S). Second first-in first-out means for transmitting; Buffer control means connected to the first and second first-in first-out means to monitor a storage state and to control the first-in first-out means; First counting means for receiving a counter driving signal output from the buffer control means and outputting a counter output; Separation and recombination header generating means connected to said first counting means for receiving a counter output and generating a separation and recombination header and transmitting it to said second first-in first-out means; Separation and recombination header detection means for receiving a counter output of the first counting means and detecting a separation and recombination header among data transmitted to the separation and recombination header generating means and the second first-in first-out means; And image data compensation means connected to the first counting means to check the output sequence number of the separation and recombination header detection means to compensate for the lost data and to transmit it to the second first-in first-out means.

Hereinafter, with reference to the accompanying drawings will be described an embodiment according to the present invention;

1 is a block diagram according to the present invention, which includes a video codec (1), a first FIFO (2), a buffer control circuit (4), a counter circuit (5), a separation and recombination header generating circuit (6), and a separation and recombination header. It consists of a generation circuit 7 and an image data compensation circuit 8.

The video connection device includes a video codec connection circuit 1 for connecting an image signal from a video codec, a first FIFO 2 connected to the video codec connection circuit 1 to store image information and to inform a storage state thereof, ATM adaptation layer-protocol data unit (ALL-) stored in the ATM adaptation layer-service data unit (AAL-SDU) and the separation and reassembly (SAR) header connected to the first FIFO 2 and transmitted from the first FIFO 2 PDUs (PDUs) to be sent to the ATM layer or to separate and reassemble the ATM Adaptation Layer-Protocol Data Units (AAL-PDUs) sent from the ATM Layer and separate the ATM Adaptation Layer-Service Data Units (AAL-SDUs). A counter output from the buffer circuit 4 and a buffer control circuit 4 connected to a second FIFO 3, the first and second FIFOs 2 and 3 to monitor a storage state and to control the FIFO; With drive signal A counter circuit 5 for outputting a counter output, a split and recombination header generating circuit 5 connected to the counter circuit 5 for receiving a counter output, generating a separate and recombined header, and transmitting the generated output to the second FIFO 3; A separation and recombination header detection circuit (7) for receiving a counter output of the counter circuit (5) and detecting a separation and recombination header among data transmitted to the separation and recombination header generation circuit (6) and the second FIFO (3). And an image data compensation circuit (8) connected to the counter circuit (5) for checking the output sequence number of the separation and recombination header detection circuit (7) to compensate for the lost data and to transmit it to the second FIFO (3). Equipped.

2 is a block diagram of a video codec connection circuit.

The signal transmitted from the video codec is transmitted as a line-coded signal (Bi-Ploar with three Zero substitution (B3ZS) hereinafter) and non-zero return (Non Return to Zero: NRZ) data. Branch signals are to be accepted. First, the B3ZS signal attenuates the reflection of the signal transmitted through the B3ZS impedance matching circuit 9 to be transmitted to the B3ZS converter 10 and detects the threshold of the B3ZS signal transmitted to the bipolar to transmit + and-data to the transmission clock. In the case of a video codec converted into NRZ data and transmitted to the input / output driver 11, the NRZ signal transmitted from the video codec is signal-matched through the impedance matching circuit 12 and then clocked together with a clock. The data is transmitted to the input / output driver 13 and then transmitted to the first FIFO 2.

3 and 4 are block diagrams of transmission and reception of the first FIFO 2 and the second FIFO 3, respectively.

The transmission / reception block diagram of the first FIFO 2 is divided into a first transmission buffer 14 and a first reception buffer 15.

The NRZ data and the digital signal level 3 clock transmitted from the video codec connection circuit 1 are transmitted to the serial data input terminal and the serial clock input terminal of the first transmission buffer 14 at the time of transmission, and are serially / parallel converted and stored. The signal indicating the data storage state of the buffer is transmitted to the buffer control circuit 4, the signal for driving the first transmission buffer 14 is supplied from the buffer control circuit 4, and the first transmission buffer 14 Since the signal for informing the operator of underflow, underflow, and steady state is transmitted to the buffer control circuit 4, the first transmission buffer 14 is transferred according to the clock output from the counter circuit 5 without losing the stored data. By driving, a 47-octet ATM adaptation layer-service data unit is transmitted from the parallel data output terminal to the parallel data input terminal of the second FIFO 3.

The clock is provided from the second receiving buffer 17 of the second terminal 3 to the parallel data input terminal of the first receiving buffer 15 and received from the counter circuit 5 at the time of reception. Since it is connected to the parallel clock input terminal of the first receiving buffer 15, parallel / serial conversion is stored in the first receiving buffer 15, and the overflow, underflow, normal state, etc. of the first receiving buffer 15 are shown. By transmitting a signal indicating the buffer state of the buffer to the buffer control circuit (4) to protect the data loss stored in the first receiving buffer 15, the clock output from the counter circuit (5) is a series of the first receiving buffer 15 It is transmitted to the video codec connection circuit 1 via the serial data output terminal simultaneously with the input to the clock terminal.

The transmission / reception block diagram of the second FIFO 3 is divided into a second transmission buffer 16 and a second reception buffer 17. The ATM adaptation layer-service data unit (AAL-SDU) output from the first transmission buffer 14 of the first FIFO 2 and the separation and reassembly headers supplied from the separation and reassembly header generation circuit 6 may include a counter circuit ( 5 is input to the parallel data input and the parallel clock input terminal of the second transmission buffer 16 together with the clock provided in 5), and the clock of the counter circuit 5 is connected to the parallel clock output terminal of the second transmission buffer 16. And transmits an ATM adaptation layer-protocol data unit (AAL-PDU) from the parallel data output terminal to the buffer control circuit 4 informing of the buffer storage state such as buffer overflow, underflow, and steady state. The ATM adaptation layer-protocol data unit (AAL-PDU) stored in the transmission buffer 16 is transmitted without loss to the ATM layer, and upon reception, the ATM adaptation layer-protocol data unit (AAL-PDU) transmitted from the ATM layer is transferred to the ATM layer. Supply from Tier After being stored through the parallel data input and the parallel clock input terminal of the second receiving buffer 17 together with the clock, the clock of the counter circuit 5 is sequentially input to the parallel clock output terminal. To the detection circuit 7, an ATM adaptation layer-service data unit (AAL-SDU) is input to the parallel data input terminal of the first receiving buffer 15, and the buffer overflows, underflows, and steady state buffers. Since the signal informing the magnetic field state is transmitted to the buffer control circuit 4, the buffer input / output is controlled through the drive / control signal terminal.

5 is a block diagram of the buffer control circuit 4.

The buffer control circuit 4 is composed of a buffer state input and decoding circuit 18, a flip-flop circuit 19, and a flip-flop control circuit 20.

A buffer state output signal is input to the buffer state input and decoding circuit 18 according to respective states from the first and second transmit / receive buffers 14 to 17, so that the decoded signal is a D flip of the flip-flop circuit 19. D flip-flop is input to each clock terminal and D flip-flop D terminal is kept at a logic value '1' so that the D flip at the moment when a decoded signal corresponding to the input / receive buffers 14 to 17 is input to the clock terminal. The Q terminal of the flop outputs a logic value '1' and transmits it to the flip-flop control circuit 20, and provides buffer control signals such as output driving and switching of the buffer to each transmit / receive buffer 14 to 17. When the storage state of each transmit / receive buffer 14 to 17 is transmittable, the counter driving signal is supplied to the counter circuit 5, and after the output of the Q terminal of the flip-flop circuit 19, the flip-flop clear signal is supplied. Input to the clear terminal of the flip-flop circuit 19, and D Clear the output of the flip-flop circuit.

6 is a block diagram of a separation and recombination header generating circuit, wherein the recognition bit generating circuit 21, the sequence number generating circuit 22, the sequence number protecting bit generating circuit 23, and the parity bit generating circuit 24 are shown. And the corresponding eight foot flip-flop 25.

The separation and reassembly header provided by the ATM adaptation layer is composed of 4 bits of the sequence number field and 8 bits of 4 bits of the sequence number protection field.

The recognition bit generation circuit 21 determines the presence or absence of information input from the wrong portion, and is divided into logical values '0' and '1', and the sequence number generation circuit 22 is provided by the first transmission buffer 14. A sequence number of logical values '000' to '111' is assigned to each of the ATM adaptive layer-service data units (ALL-SDUs) of bytes, and the sequence number protection bit generation circuit 23 protects the data of the sequence number field. 3 bits, which is composed of a separate and recombination header together with one bit of the parity bit provided by the parity bit generating circuit 24 and is passed to the 8-bit flip-flop 25, and the output of the counter circuit 5 The second transmission buffer 16 is transmitted according to the clock.

7 is a block diagram of a separation and recombination header detection circuit, and is composed of a corresponding 8-bit flip-flop 26, a parity bit check circuit 27, an error correction circuit 28, and an error detection circuit 29. have.

The protocol operation in the detach and recombine header detection circuit 7 is as follows. First, the default mode is the error correction mode, which operates in the normal state in which headers with no errors are input. When an error occurs in the header, the error correction function is performed for 1-bit errors. Will change to and operate.

The separation and recombination headers transmitted from the second reception buffer 17 are transferred to the corresponding 8-bit flip-flop 26 according to the clock provided from the counter circuit 5, and the parity bit check circuit 27 is previously transmitted. The separation and reassembly headers are transmitted together with the first and second driving signals to the error correction circuit 28 and the error detection circuit 29, respectively, to indicate an abnormal state of the separation and reassembly headers with the sequence number bits and the sequence number protection bit fields. In case of 1-bit error, correct it and switch the input to the error correction circuit with the first control signal and the first exchange signal, and for the multi-bit error, the corresponding ATM adaptive layer-service EDLXK unit (AAL-SDU) is discarded and sent to the image data compensation circuit 8 to compensate for this, and the next separation and recombination header is sent from the parity bit check circuit 27 to the error detection circuit according to the second drive signal. Received by (29), continues in case of an error, and after receiving the normal separation and reassembly header, drives the error correction circuit 28 together with the second exchange signal and the second control signal, and performs normal separation and reassembly header check. Transfer to the second receiving buffer 17.

The seventh will be described in detail as follows.

In the parity bit check circuit 27, after checking the even parity of the header, the header input to the error correction circuit 28 is inputted as a first control signal, and the input to the error detection circuit 29 is controlled by the second control. Input by signal. Here, the first or second control signal is a signal for inputting a header to each circuit according to the received mode, and the operations of the error correction circuit 28 and the error detection circuit 29 are controlled by the first and second drive signals. It is transferred. The first and second drive signals output from the parity bit check circuit 27 signal the presence or absence of an error of the header to be output, thereby controlling the operations of the error correction circuit 28 and the error detection circuit 29. For example, in the normal case, when the header output from the parity bit check circuit 27 is normal due to the first control signal of the error correction circuit 28, the first drive signal advances the operation of the error correction circuit 28. The operation of the error detection circuit 29 is stopped by the first drive signal and the second drive signal having the inversion function. On the contrary, when the header error occurs, the error correction circuit 28 is driven to correct the error for the 1-bit error, and the second header is inverted from the first drive signal from the next header through the first exchange signal. The error detection circuit 29 is operated by the drive signal.

A no bit, 1 bit, and multi bit error detection process for a split and recombination (SAR) header is as follows.

The current AAL1 protocol corrects errors for one-bit errors and sends them, but discards headers and payloads for errors more than two bits. Therefore, in the error correction circuit 28, the normal header is directly transmitted to the first reception buffer 15. However, when an error occurs, the error correction circuit 28 corrects it and transmits it to the first reception buffer 15. . In the case of a multi-bit error, the header and payload are discarded, and then the operation is switched to the error detection circuit 29 via the first exchange signal. After checking the received header, the error detection circuit 29 discards the header for subsequent errors (1 bit, multi-bit) and stores the header and payload only when the normal header is received. And the mode is switched to the error correction circuit 28 by the second exchange signal to receive the next header.

The error correction circuit 28 and the error detection circuit 29 each have a check function for header errors. The error correction circuit 28 has 1-bit correction capability for and handles received header errors, but discards headers with multi-bit errors. The error detection circuit 29 judges only whether there is an error in the received header, transmits only the normal header to the second receiving buffer without an error, and discards the header according to the protocol when there is an error.

Therefore, in order to compensate for the loss of data existing by the discarded PDU between the sequence number of the normal PDU and the sequence number of the next PDU, only the normal header is transmitted to the image data compensation circuit.

The image data compensation method is as follows.

The separation and recombination (SAR) header detection circuit 7 receives the separation and recombination header and payload from the second receiving buffer to determine whether there is an error for the separation and recombination header. Here, the image data compensation circuit 8 is delivered with normal separation and recombination headers sequentially input. Referring to the operation, since the sequence numbers of the normal separation and recombination headers always have a difference of '001' from the next one, the image data compensation circuit 8 receives as many compensation SDUs as having a difference of more than binary '1' from the first. Function to provide to the receive buffer. For example, when the sequence number value of the first header input to the image data compensation circuit 8 is '000' and the next input value is '001', the sequence of AAL-PDUs is normal and thus the image data compensation circuit 8 ) Does not work, but if the first input value is '000' and the next input value is '010', the difference between them is 2, so one AAL-PDU is lost in the middle. 8) generates a compensation SDU to compensate for this and transmits it to the first receiving buffer.

FIG. 8 is a block diagram of the image data compensation circuit, and is composed of the 8-bit flip-flop 30, the first counter 31, the counter control circuit 32, and the image data compensation buffer 33. As shown in FIG.

The clock terminal of the 8-bit flip-flop 30 receives a signal for compensating for lost image data from the output of the error detection circuit 29 and outputs a logic value '1', which is a counter driving signal, through the Q terminal. The first counter 31 receives the driving signal and supplies 47 compensation buffer driving clocks for driving the image data compensation buffer 33, and receives the image data compensation buffer 33. Is compensated for the lost data through the output terminal and provided to the first receiving buffer 15, and at the same time the 47 th clock provided from the first counter 31 is supplied to the counter control circuit 32, the counter control circuit ( 32 supplies a counter control signal to the clear terminal of the first counter 31 and the output control terminal of the image data compensation buffer 33 to control the output of the first counter 31 and the image data compensation buffer 33. .

9 is a block diagram of the counter circuit 5, and is composed of a second counter circuit 34, a decoding circuit 35, and a clock output control circuit 36. As shown in FIG.

The second counter circuit 34, which receives the clock divided by the network, supplies a counter output signal for supplying 48 clocks to the decoding circuit 35, and the decoding circuit 35 provides a separation and recombination header and an ATM adaptation layer. Provides decoding information for supplying the clock to transmit the service data unit (AAL-SDU). The clock output circuit 36 provided with the decoding information drives the separation and recombination header generation circuit 6 as the first clock, and clears the separation and recombination header generation circuit 6 as the second to 48th clocks. At the same time, it is supplied to the parallel clock terminal of the first transmission buffer 14 to transfer the ATM adaptation layer-service data unit (AAL-SDU) to the second transmission buffer 16, and the clock output control circuit 36 is cleared again. 48 clocks are sequentially supplied, and another 48 clocks are sequentially supplied through the clock output control circuit 36 to be provided to the separation and reassembly header generation circuit 6 and the second transmission buffer 16 to provide ATM. Clear the clock output control circuit 37 by storing the adaptation layer-protocol data unit (AAL-PDU).

Therefore, the present invention converts the signal (B3ZS) transmitted by line coding in the video codec into an NRZ signal by impedance matching at the connection terminal of the video codec, or immediately matches the NRZ signal of the video codec by outputting the NRZ. It is connected to a codec and converted to 8-bit parallel in a serial connection of a buffer that stores only pure video data. A buffer to store 8-bit parallel image data information and a buffer to store a separation and reassembly header for assigning sequence numbers to packetized image information. Connect ATM Adaptation Layer-Service Data Units (AAL-SDUs) and transmit them as ATM Adaptation Layer-Protocol Data Units (AAL-PDUs) to the ATM Adaptation Layer. A video codec that stores the ATM Adaptive Layer-Service Data Unit (AAL-SDU) in a buffer, transmits it to the video codec, and restores the video signal. A fixed bit rate video service can be provided.

That is, the ATM layer is formed by connecting a 1-byte separation and reassembly header and 47-byte ATM adaptation layer-service data unit (AAL-SDU) to receive the image information provided from the fixed bit rate video codec in the ATM network. The ATM adaptation layer-protocol data unit (AAL-PDU) for transmitting to the ATM is generated and transmitted to the ATM layer, which can be used for video communication in an ATM network.

Claims (8)

Video codec connection means (1) for connecting a video signal from the video codec; First-in first-out means (2) connected to said video codec access means (1) for storing image information and for indicating a storage state; ATM Adaptation Layer by storing a Separation and Recombination (SAR) header with an ATM Adaptation Layer-Service Data Unit (AAL-SDU) connected to the first-in, first-out means (2) and transmitted from the first-in, first-out means (2). Create and transmit Protocol Data Units (AAL-PDUs) to the ATM layer, or separate and recombine ATM Adaptation Layer-Protocol Data Units (AAL-PDUs) sent from the ATM layer headers and ATM Adaptation Layer-Service Data Units (AAL-PDUs). Second first-in, first-out means (3) for separating and transmitting in SDUs; A buffer control means (4) connected to said first and second first-in first-out means (2,3) for monitoring storage conditions and controlling said first-in first-out means (2,3); First counting means (5) for receiving a counter drive signal output from said buffer control means (4) and producing a counter output; Separation and recombination header generating means (6) connected to said first counting means (5) for receiving a counter output, generating a separation and recombination header, and transmitting it to said second first-in first-out means (3); A separation and recombination header that receives a counter output of the first counting means 5 and detects a separation and recombination header among data transmitted to the separation and recombination header generating means 6 and the second first-in first-out means 3. Detection means 7; And image data compensation connected to the first counting means 5 to check the output sequence number of the separation and recombination header detection means 7 to compensate for the lost data and to transmit it to the second first-in, first-out means 3. And a means (8). 2. The video codec connection means (1) according to claim 1, further comprising: B3ZS conversion means (10) for inputting a line coded signal (B3ZS) through an impedance matching circuit (9); A first input / output driver (11) connected to the B3ZS conversion means (10); Impedance matching means 12 for impedance matching a non-zero return (NRZ) signal and a clock divided in the network; And a second input / output driver 13 connected to the impedance matching means 12 to receive a matched signal, wherein the first and second input / output drivers 13 may include the first first-in first-out means ( 2) an image connecting device, characterized in that connected to. The video connection apparatus according to claim 1, wherein the first and second first-in, first-out means (2, 3) comprise first and second transmission / reception buffers 14 to 17 so that transmission and reception can be performed together. . 2. The apparatus according to claim 1, wherein said buffer control means (4) comprises: buffer state input and decoding means (18) for receiving a buffer state from said first and second first-in first-out means (2,3); A flip-flop circuit (19) connected to said buffer status input and decoding means (18) for outputting a signal for driving a corresponding buffer; And flip-flop control means (20) connected to said flip-flop circuit (19) for outputting a buffer control signal and a counter drive signal. 2. The separation and recombination header generating means (6) according to claim 1, further comprising: a sequence number protection field (A) comprising a recognition bit generation circuit (21) and a sequence number generation circuit (22); A sequence number protection field B comprising a sequence number protection bit generation circuit 23 and a parity bit generation circuit 24; A flip-flop 25 connected to the sequence number field A and the sequence number field B and receiving an output from the first counting means 5, the flip-flop 25 being the second; An image connecting device, characterized in that connected to the first-in first-out means (3). 2. The apparatus according to claim 1, wherein said separation and recombination header detection means (6) comprises: a flip-flop (26) for receiving and storing a signal from said second first-in first-out means (3); Parity bit checking means (27) connected to the flip-flop (26) to check parity bits; Error correction means (28) for receiving a first drive signal from the parity bit check means (27) and outputting a first control signal; And error detection means 29 for receiving a second drive signal from the parity bit check means 27 and outputting a second control signal, wherein the error correction means 28 and the error detection means 29 Outputting first and second exchange signals, respectively, and are connected to said first-in first-out means (3) and video data compensation means (8). The image data compensating means (8) according to claim 1, further comprising: a flip-flop (30) driven by an input from the error detecting means (29); Second counting means (31) connected to the flip-flop (30); Counter control means (32) coupled to the flip-flop (30) and sending an output to the second counting means (31) and the flip-flop (30); An image data compensation buffer 33 which receives a compensation buffer driving clock from the second counting means 31, is controlled by the counter control means 32, and outputs to the first first-in first-out means 2; And a video connection device. 2. The apparatus of claim 1, wherein the first counter means (5) comprises: second counting means (34) for receiving a clock divided by a network; Decoding means 935 for decoding the output of said second counting means; And a clock output control means 36 which receives a clock divided by a network, receives decoding information of the decoding means 35 and sends a counter circuit clear signal to the second counting means 34. Connecting device.