GB2342226A - Growing a deuterium containing insulation layer - Google Patents
Growing a deuterium containing insulation layer Download PDFInfo
- Publication number
- GB2342226A GB2342226A GB9922758A GB9922758A GB2342226A GB 2342226 A GB2342226 A GB 2342226A GB 9922758 A GB9922758 A GB 9922758A GB 9922758 A GB9922758 A GB 9922758A GB 2342226 A GB2342226 A GB 2342226A
- Authority
- GB
- United Kingdom
- Prior art keywords
- insulation film
- semiconductor device
- furnace
- forming
- deuterium
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Withdrawn
Links
- 238000009413 insulation Methods 0.000 title claims abstract description 84
- YZCKVEUIGOORGS-OUBTZVSYSA-N Deuterium Chemical compound [2H] YZCKVEUIGOORGS-OUBTZVSYSA-N 0.000 title claims abstract description 34
- 229910052805 deuterium Inorganic materials 0.000 title claims abstract description 31
- XLYOFNOQVPJJNP-ZSJDYOACSA-N Heavy water Chemical compound [2H]O[2H] XLYOFNOQVPJJNP-ZSJDYOACSA-N 0.000 claims abstract description 34
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims abstract description 30
- 229910052710 silicon Inorganic materials 0.000 claims abstract description 30
- 239000010703 silicon Substances 0.000 claims abstract description 30
- MWUXSHHQAYIFBG-UHFFFAOYSA-N Nitric oxide Chemical compound O=[N] MWUXSHHQAYIFBG-UHFFFAOYSA-N 0.000 claims abstract 3
- 238000000034 method Methods 0.000 claims description 35
- 239000004065 semiconductor Substances 0.000 claims description 28
- 230000001590 oxidative effect Effects 0.000 claims description 23
- 238000004140 cleaning Methods 0.000 claims description 6
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 abstract description 11
- 239000007789 gas Substances 0.000 abstract description 10
- 229910052760 oxygen Inorganic materials 0.000 abstract description 8
- 239000001301 oxygen Substances 0.000 abstract description 8
- 230000015556 catabolic process Effects 0.000 abstract description 2
- MGWGWNFMUOTEHG-UHFFFAOYSA-N 4-(3,5-dimethylphenyl)-1,3-thiazol-2-amine Chemical compound CC1=CC(C)=CC(C=2N=C(N)SC=2)=C1 MGWGWNFMUOTEHG-UHFFFAOYSA-N 0.000 abstract 1
- 230000015572 biosynthetic process Effects 0.000 abstract 1
- JCXJVPUVTGWSNB-UHFFFAOYSA-N nitrogen dioxide Inorganic materials O=[N]=O JCXJVPUVTGWSNB-UHFFFAOYSA-N 0.000 abstract 1
- 239000000758 substrate Substances 0.000 abstract 1
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N silicon dioxide Inorganic materials O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 9
- 229910052681 coesite Inorganic materials 0.000 description 8
- 229910052906 cristobalite Inorganic materials 0.000 description 8
- 229910052682 stishovite Inorganic materials 0.000 description 8
- 229910052905 tridymite Inorganic materials 0.000 description 8
- 230000010354 integration Effects 0.000 description 4
- 238000004519 manufacturing process Methods 0.000 description 3
- 229910052581 Si3N4 Inorganic materials 0.000 description 2
- 238000000137 annealing Methods 0.000 description 2
- 239000003990 capacitor Substances 0.000 description 2
- 229910052739 hydrogen Inorganic materials 0.000 description 2
- 239000001257 hydrogen Substances 0.000 description 2
- 238000002161 passivation Methods 0.000 description 2
- 241001391944 Commicarpus scandens Species 0.000 description 1
- UFHFLCQGNIYNRP-UHFFFAOYSA-N Hydrogen Chemical compound [H][H] UFHFLCQGNIYNRP-UHFFFAOYSA-N 0.000 description 1
- 229910052782 aluminium Inorganic materials 0.000 description 1
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 1
- 230000003247 decreasing effect Effects 0.000 description 1
- 238000000151 deposition Methods 0.000 description 1
- 230000005684 electric field Effects 0.000 description 1
- 150000002431 hydrogen Chemical class 0.000 description 1
- 238000002844 melting Methods 0.000 description 1
- 230000008018 melting Effects 0.000 description 1
- 229910052751 metal Inorganic materials 0.000 description 1
- 239000002184 metal Substances 0.000 description 1
- 229910044991 metal oxide Inorganic materials 0.000 description 1
- 150000004706 metal oxides Chemical class 0.000 description 1
- 239000000377 silicon dioxide Substances 0.000 description 1
- 235000012239 silicon dioxide Nutrition 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02107—Forming insulating materials on a substrate
- H01L21/02225—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer
- H01L21/02227—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a process other than a deposition process
- H01L21/0223—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a process other than a deposition process formation by oxidation, e.g. oxidation of the substrate
- H01L21/02233—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a process other than a deposition process formation by oxidation, e.g. oxidation of the substrate of the semiconductor substrate or a semiconductor layer
- H01L21/02236—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a process other than a deposition process formation by oxidation, e.g. oxidation of the substrate of the semiconductor substrate or a semiconductor layer group IV semiconductor
- H01L21/02238—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a process other than a deposition process formation by oxidation, e.g. oxidation of the substrate of the semiconductor substrate or a semiconductor layer group IV semiconductor silicon in uncombined form, i.e. pure silicon
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02107—Forming insulating materials on a substrate
- H01L21/02109—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates
- H01L21/02112—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer
- H01L21/02123—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon
- H01L21/02164—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon the material being a silicon oxide, e.g. SiO2
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02107—Forming insulating materials on a substrate
- H01L21/02225—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer
- H01L21/02227—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a process other than a deposition process
- H01L21/02255—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a process other than a deposition process formation by thermal treatment
Landscapes
- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Formation Of Insulating Films (AREA)
- Insulated Gate Type Field-Effect Transistor (AREA)
Abstract
An oxide or oxynitride layer is grown on a silicon substrate in a deuterium containing atmosphere in a furnace. The insulation layer may be grown in a deuterium oxide atmosphere. The layer may have a multilayer structure with a conventional insulating layer either overlying or underlying the deuterium oxide/oxynitride layer. The atmosphere in the furnace may be purely deuterium oxide or have a conventional oxidising gas component (ie oxygen, nitrogen monoxide or nitrogen dioxide). The leakage and breakdown characteristics of the insulation film are improved due to the formation of strong silicon-deuterium bonds.
Description
2342226 l\l[ETHOD OF FORMING AN INSXJLATION F11LM IN A SEMICONDUCTOR
DEVICE
FIELD OF THE INVENTION
1. Field of the Invention
71he present invention relates to a method of forming an insulation film that is an essential process in manufacturing a Metal Oxide Semiconductor (MOS), which can be applicable to all the Ultra Large Scale Integration (ULSI) to which MOS is applied.
2. Description of the Prior Art
In a conventional technology, to form an insulation Elm such as a gate oxide, a S'02 insulation film is formed on a silicon wafer by annealing the silicon wafer at high temperature in the ambient of oxygen, hydrogen or steam. The Si02 insulation film is contained a large amount of hydrogen, whereby Si-H bonds are created in SiO2 insulation film.
As the degree of integration of the semiconductor device is increased, the thickness of the insulation film is scaled less than 50A. As the thickness of the insulation film becomes scaled, the Si-H bonds easy to break by an electrical stress. Thus, it may cause a problem in which an electrical and reliability characteristics of the insulation film such as a lowered WDB (time-independent 1 dielectric breakdown) characteristics and an increased SILC (Stress induced leakage current), etc.
In order to obtain a higher integration of the semiconductor device, it is required that the insulation film must be very thin and uniform while keeping a good reliability characteristics. However, as explained above, the conventional technology has a limitation.
According to a paper called Results of Improved Device Reliability Using Deuterium (D2) on'IEEE Electron Device Letter, Vol. 18, No. 3, March p. 81-83, 199T, it is said that, in a final step after manufacturing of the device, an annealing C> process is performed under the ambient of deuterium (D2) so that any silicon dangling bonds that are not combined with oxides existing at a Si/si02 interface have the strong bond force of Si-D instead of conventional SPH bond, thereby the electrical and reliability characteristics of the insulation film becomes relatively good even though a high electrical field is applied to it during operation of the device. However, in case of depositing a Si3N4 layer VAth a passivation layer, this method has a problem that it does not greatly improve the device characteristics since a Si-D bond is difficult to Gonn at Si/Si02 interface due to difficulty of difflusion of deuterium (Q) throm-fli the Si3N4 layer. Also, this method has a problem that it could not add a stiff'icicnt amount of deuterium (D2) to the interface because the temperature during the diermal process could not be set higher than the melting point of aluminum used as a metal wire.
2 S LTAINIARY OF TBE E-N3NTIO It is therefore an object of the present invention to provide a method of forming an insulation film in a semiconductor device, capable of solving the above problems by improve the electrical and reliability characteristics of the device by which an insulation film is directly grown in the ambient of deuterium oxide (D20)or deuterium (D2) so that deuterium can be easily added to aSi/Si02 interface.
BRIEF DESCRIPTION OF TBE DRAWING
The above object, and other features and advantages of the present invention will become more apparent by describing the preferred embodiment thereof with reference to the accompanying drawing, in which:
Fig. 1 shows a graph for illustrating the phenomenon in which electrons are trapped into an insulation film in a MOS capacitor.
DETAILED DESCRIPTION OF PREFERRED EMBODIMENT
During the process of manufacturing a semiconductor device, a method of forming an insulation film such as a gate oxide is essential. As the integration of the semiconductor device becomes higher, the thickness of the insulation film is scaled less than 50A and the electrical reliability characteristics has to be also improved.
To improve the electrical reliability characteristics of the insulation film, the method performs an oxidizing process using deuterium oxide (D20) or deuterium(D2) to so that deuterium can be easily added to theSi/S'02 interface. In other words, the present invention makes a Si-D bond be formed at the Si/Si02 interface during the process of forming the insulation film.
Meanwhile, as in the following Example 2 and 3, the oxidizing temperature of the first and second steps can be controlled to a proper range. In other words, the oxidizing temperature of the first and second steps is proceeded simultaneously or differently, so that the thickness of the insulation and the containing amount of deuterium can be controlled independently.
A preferred embodiment of the present invention will be explained below in detail by reference to the accompanying drawing.
<Example l>
After cleaning a silicon wafer on which an insulation film will be fonned, the silicon wafer is loaded into a furnace which is heated to at the temperature of 650 through 750 C. Then, deuterium oxygen (D20) is supplied into it at the temperature of 750 through 1,050 C to fonii aii insulation film on the silicon wafer, thus completing a semicondtictor de- .,,,ice.
In the above Example 1, deutenum oxide i, supplied at the flow rate of 3 through 10 SLM (standard liter per minute).
4 <Example 2>
As in Example 1, after the silicon wafer is loaded into the furnace, at a first Step 02 is supplied into it at the flow rate of 3 through 10 SLM to grow a first insulation film having the thickness of 30 through 50A on the silicon wafer, and at a second step deuterium oxide is supplied into it at the flow rate of 3 through 10 SLM to grow a second insulation film having the thickness of 10 through 3 OA on the first insulation firm, thus completing an insulation film according to the present invention, wherein02being an oxidizing gas and deuterium oxide (D20) are used respectively at the temperature of 750 through 1,050 C In the above Example 2, NO or N02 may be used instead of 02 used in the first step, and also the fast and second step may be changed in order.
<Example 3>
As in Example 1, after the silicon wafer is loaded into the furnace, at a first step deuterium oxygen is supplied into it at the flow rate of 3 through 10 SLM at the temperature of 750 through 950 'C to grow a first insulation film having the thickness of 30 through 50A on the silicon wafer, and at a second step NO or N02 is supplied into it at the flow rate of 3 SLM through 10 at the temperature of 95 0 through 1,050 C to grow a second insulation film having the thickness of 10 through 30A on the first insulation firm, thus completing an insulation film C> according to the present invention, wherein NO or NO, being oxidizing gases and Z deuterium oxygen (D20) are used respectively.
In the above Example 3, 0-, being an oxidizing gas may be used instead of No or N02 used in the second step, and also the first and second step may be changed in order. Also, deuterium oxygen may be used in the second step and NO or N02 may be used in the first step, without varying the temperature.
<Example 4>
As in Example 1, after the silicon wafer is loaded into the furnace, NO or N02 being oxidizing gases and deuterium oxygen (D20) are used simultaneously at the temperature of 750 through 1,050 'C and the combined gases are supplied into it at the flow rate of 3 through 1 OSLM, thus forming an insulation film on the silicon wafer. At this time, the combined ratio of NO or N02 to deuterium oxygen is 1: 0. 1 through 10.
In the above Example 4, 02 being an oxidizing gas may be used instead of No or N02.
<Example 5>
As in Example 1, after the silicon wafer is loaded into the furnace, 02being an oxidizing gas and deuterium (D2) are used si ii i t 11 tmeously at the temperature of 750 through 1,050 'C and the combined gases are upplied into it at the flow rate of 3 through 10SLM, thus forming aii insulation filin on the silicon wafer. At this time, the combined ratioOf 02to deuterium (D,,) Is 1: 0.5 through 2.
In the above Example 5, 02 being an oxidiz-iiig gas may be used instead of C> -A x i 6 No or N02.
With the above examples, deuterium is added at the Si/Si02 interface to form a Si-D bond. Further, the fi=ace to which these examples may be applied include both a tube-type furnace and a rapid then-nal furnace.
<Test Example> Fig. 1 shows the phenomenon AVc; resulting from trapped electrons into C) respective insulation films of a MOS capacitor in which an insulation film of 17nm is grown by using deuterium oxide (D20) and H20 at the temperature of 900 'C. In Fig. 1, AVG represents a gate voltage shift under constant current, which was 10 MA/CM2 in this test example. As can be seen from Fig. 1, comparing the insulation film grown under the ambient of conventional H20 and the insulation film which is groAm under the ambient of D20. the amount of trapped electrons is dr-amatically decreased in the insulation film grown under the ambient of D20 than that under the ambient of H.,O. Therefore, it can be seen that the device reliability is high in the insulation film grown under the ambient of D20 than that under the ambient of H20.
As described above, the present invention can improve the electrical reliability characteristics of a device by growing an insulation film under the ambient of deuterium oxide or deuterium so that a sufficient amount of deuterium 7 can be added to aSi/Si02 interface. Therefore, the insulation film accordina to W the present invention has not only a good electrical reliability, but also can easily add deuterium into the Si/Si02 interface regardless a passivation layer of by controlling the amount of deuterium existing at the insulation film.
While the present invention has been described and illustrated herein with reference to the preferred embodiment thereof, it ',XAII be understood by those skilled in the art that various changes in form and details may be made therein without departing from the spirit and scope of the invention.
8
Claims (23)
1 A method of fom-iing an insulation film in a semiconductor device, comprising the steps of. cleaning a silicon wafer and then loading the silicon wafer into a furnace; and growing an insulation film on the silicon wafer by supplying a deuterium oxide into said furnace.
2. The method of fom-iing an insulation film in a semiconductor device as claimed in Claim 1, wherein said loading temperature is 650 through 750 C and the growth temperature of said insulation film is 750 through 1,050 'C.
3. The method of forming an insulation film in a semiconductor device as claimed in Claim 1, wherein said deuterium oxide is supplied into said furnace at the flow rate of 3 through 1 OSLM.
4. A method of fom-iing an insulation film in a semiconductor device, comprising the steps of. cleaning a silicon wafer and then loading said silicon wafer into a furnace; growing a first insulation film on said silicon wafer by supplying an oxidizing gas into said furnace; and growing a second insulation film on said first insulation film by supplying 9 deuterium oxide into said furnace, thereby forn-ting an insulation film contained deuterium.
5. The method of forming an insulation film in a semiconductor device as claimed in Claim 4, wherein said oxidizing gas is at least one of 0, NO and N02.
C> -
6. The method of forming an insulation film in a semiconductor device as claimed in Claim 4, wherein the growth temperature of said first and second insulation film is 750 through 1,050 C.
7. The method of forn-fing an insulation fih-n in a semiconductor device as claimed in Claim 4, wherein the growth temperature of said first insulation fLIm is 750 through 950 C, and the growth temperature of said second insulation film is 950 through 1,050 'C.
8. The method of forming an insulation film in a semiconductor device as claimed in Claim 4, wherein said oxidizing gas and said deuterium oxide is C_ respectively supplied into the furnace at the flow n tie of 3 through 1 OSLM.
9. A method of forming an insiiIation ftirn M a semiconductor device, comprising the steps of. cleaning a silicon wafer and then loading s t 1 (.1 silicon wafer into a flirnace; to growing a first insulation film on said silicon wafer by supplying deuterium into said furnace; and growing a second insulation film on said first insulation film by supplying an oxidizing gas into said furnace, thereby forming an insulation film contained deuterium.
10. The method of forming an insulation film in a semiconductor device as claimed in Claim 9, wherein said oxidizing gas is at least one Of 02, NO and N02.
11. The method of forming an insulation film in a sen-ticonductor device as claimed in Claim 9, wherein the growth temperature of said first and second insulation film is 750 through 1,050 C.
12. The method of forming an insulation film in a sen-Liconductor device as claimed in Claim 9, wherein the growth temperature of said first insulation film is 750 through 950 'C, and the growth temperature of said second insulation film is 950 through 1,050 C.
13. The method of forming an insulation filni in a semiconductor device as claimed in Claim 9, wherein said oxidizing gas and said deuterium oxide is C> respectively supplied into the fi=ace at the flow rate of -3) through 1 OSLM.
11
14. A method of fom-fing an insulation film in a semiconductor device, comprising the steps of.
cleaning a silicon wafer and then loading said silicon wafer into a furnace; gTowing an insulation film on said silicon wafer by supplying an oxidizing gas and deuterium oxide into said furnace.
15. The method of fonning an insulation film in a semiconductor device as claimed in Claim 14, wherein said loading temperature is 650 and 750 'C, and the growth temperature of said insulation film is 750 through 1,050 'C.
16. The method of forming an insulation film in a semiconductor device as claimed in Claim 14, wherein said oxidizing gas and said deuterium oxide is respectively supplied into the furnace at the flow rate of 3 through 1 OSLM.
17. The method of forming an insulation film in a semiconductor device as claimed in Claim 14, wherein said oxidizing gas is at least oneOf 02, NO andN02.
18. The method of forming an insulation Illin in a semiconductor device as claimed in Claim 9, in case of using NO or No.,x., oxidizing gas, the combined ratio ofNO or N02to deuterium ox c n s 1. 0, 1 t 11 rough 10.
19. A method of fom-iing an insulation Iffin in a semiconductor device, 12 comprising the steps of. cleaning a silicon wafer and then loading said silicon wafer into a furnace; growing an insulation film on said silicon wafer by supplying an oxidizing gas and deuterium into said furnace.
20. The method of forming an insulation film in a semiconductor device as claimed in Claim 19, wherein said loading temperature is 650 and 750 'C, and the growth temperature of said insulation film is 750 through 1,050 'C.
21. The method of forming an insulation film in a semiconductor device as claimed in Claim 19, wherein said oxidizing gas and said deuterium oxide is respectively supplied into the furnace at the flow rate of 3 through 1 OSLM.
22. The method of forming an insulation film in a semiconductor device as claimed in Claim 19, wherein said oxidizing gas is at least one Of 025 NO and N02.
23. The method of forming an insulation film in a semiconductor device as claimed in Claim 19, in case of using 02 as said oxidizing gas, the combined ratio Of 02 to deuterium is 1 A5 through 2.
13
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| KR1019980040260A KR20000021246A (en) | 1998-09-28 | 1998-09-28 | Method for forming insulating film for semiconductor device using deuterium oxide or deuterium |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| GB9922758D0 GB9922758D0 (en) | 1999-11-24 |
| GB2342226A true GB2342226A (en) | 2000-04-05 |
Family
ID=19552160
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| GB9922758A Withdrawn GB2342226A (en) | 1998-09-28 | 1999-09-27 | Growing a deuterium containing insulation layer |
Country Status (4)
| Country | Link |
|---|---|
| JP (1) | JP2000150508A (en) |
| KR (1) | KR20000021246A (en) |
| GB (1) | GB2342226A (en) |
| TW (1) | TW419745B (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN107154354A (en) * | 2016-03-03 | 2017-09-12 | 上海新昇半导体科技有限公司 | Wafer heat-treating methods |
Families Citing this family (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR100474190B1 (en) * | 2000-12-19 | 2005-03-08 | 주식회사 하이닉스반도체 | Method of thermal process in a semiconductor device |
| KR100500698B1 (en) * | 2002-11-20 | 2005-07-12 | 광주과학기술원 | Dangling bond decrease Method for forming high-permitivity gate dielectric |
| JP4999265B2 (en) * | 2004-08-27 | 2012-08-15 | 大陽日酸株式会社 | Method for manufacturing gate insulating film |
| US7253020B2 (en) | 2005-01-04 | 2007-08-07 | Omnivision Technologies, Inc | Deuterium alloy process for image sensors |
Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| WO1997026676A1 (en) * | 1996-01-16 | 1997-07-24 | The Board Of Trustees Of The University Of Illinois | Semiconductor devices, and methods for same |
| WO1997045864A1 (en) * | 1996-05-31 | 1997-12-04 | Lam Research Corporation | Improved method of polycrystalline silicon hydrogenation |
| JPH1012609A (en) * | 1996-06-21 | 1998-01-16 | Toshiba Corp | Semiconductor device and its manufacture |
| JPH10200115A (en) * | 1996-12-27 | 1998-07-31 | Matsushita Electric Ind Co Ltd | Thin film transistor and method for manufacturing the same |
-
1998
- 1998-09-28 KR KR1019980040260A patent/KR20000021246A/en not_active Application Discontinuation
-
1999
- 1999-09-27 TW TW088116484A patent/TW419745B/en not_active IP Right Cessation
- 1999-09-27 GB GB9922758A patent/GB2342226A/en not_active Withdrawn
- 1999-09-28 JP JP11273630A patent/JP2000150508A/en active Pending
Patent Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| WO1997026676A1 (en) * | 1996-01-16 | 1997-07-24 | The Board Of Trustees Of The University Of Illinois | Semiconductor devices, and methods for same |
| WO1997045864A1 (en) * | 1996-05-31 | 1997-12-04 | Lam Research Corporation | Improved method of polycrystalline silicon hydrogenation |
| JPH1012609A (en) * | 1996-06-21 | 1998-01-16 | Toshiba Corp | Semiconductor device and its manufacture |
| JPH10200115A (en) * | 1996-12-27 | 1998-07-31 | Matsushita Electric Ind Co Ltd | Thin film transistor and method for manufacturing the same |
Non-Patent Citations (2)
| Title |
|---|
| WPI Abstract Accession No1998-136470 & JP 10 012 609 A * |
| WPI Abstract Accession No1998-473291 & JP 10 200 115 A * |
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN107154354A (en) * | 2016-03-03 | 2017-09-12 | 上海新昇半导体科技有限公司 | Wafer heat-treating methods |
| CN107154354B (en) * | 2016-03-03 | 2020-12-11 | 上海新昇半导体科技有限公司 | Method for heat treatment of wafer |
| DE102016114940B4 (en) | 2016-03-03 | 2023-04-27 | Zing Semiconductor Corporation | Thermal processing method for a wafer |
Also Published As
| Publication number | Publication date |
|---|---|
| TW419745B (en) | 2001-01-21 |
| JP2000150508A (en) | 2000-05-30 |
| GB9922758D0 (en) | 1999-11-24 |
| KR20000021246A (en) | 2000-04-25 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| US6294819B1 (en) | CVD Ta2O5/oxynitride stacked gate insulator with TiN gate electrode for sub-quarter micron MOSFET | |
| US5068124A (en) | Method for depositing high quality silicon dioxide by pecvd | |
| US6136654A (en) | Method of forming thin silicon nitride or silicon oxynitride gate dielectrics | |
| KR100880309B1 (en) | Method for manufacturing a semiconductor device | |
| US20070169696A1 (en) | Two-step post nitridation annealing for lower eot plasma nitrided gate dielectrics | |
| US8227356B2 (en) | Method of forming semiconductor device and semiconductor device | |
| US7851383B2 (en) | Method and system for forming a controllable gate oxide | |
| KR20080047322A (en) | Improved manufacturing method for two-step post nitridation annealing of plasma nitrided gate dielectric | |
| US6689646B1 (en) | Plasma method for fabricating oxide thin films | |
| US20050245019A1 (en) | High quality thin dielectric layer and method of making same | |
| US6025281A (en) | Passivation of oxide-compound semiconductor interfaces | |
| US6740941B2 (en) | Semiconductor device including a gate insulating film made of high-dielectric-constant material | |
| US7192887B2 (en) | Semiconductor device with nitrogen in oxide film on semiconductor substrate and method of manufacturing the same | |
| GB2342226A (en) | Growing a deuterium containing insulation layer | |
| JP4224044B2 (en) | Manufacturing method of semiconductor device | |
| JPH08255905A (en) | Fabrication of semiconductor device | |
| WO2009119148A1 (en) | Film forming method and semiconductor device manufacturing method | |
| JPH07221092A (en) | Manufacture of semiconductor device | |
| US20060138501A1 (en) | Semi-conductor dielectric component with a praseodymium oxide dielectric | |
| JP3444815B2 (en) | High breakdown voltage semiconductor device and method of manufacturing the same | |
| US5908321A (en) | Semiconductor structure with stable pre-reacted particle and method for making | |
| KR950002178B1 (en) | Delta doping method by mocvd of gaas epitaxial layer | |
| KR100398621B1 (en) | Method for manufacturing gate oxide layer of semiconductor device | |
| US6544907B1 (en) | Method of forming a high quality gate oxide layer having a uniform thickness | |
| CN100550321C (en) | Manufacture method with semiconductor device of nitration case and oxide layer |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| WAP | Application withdrawn, taken to be withdrawn or refused ** after publication under section 16(1) |