GB2341773A - Host interfacing method and apparatus in a data communication system - Google Patents

Host interfacing method and apparatus in a data communication system Download PDF

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Publication number
GB2341773A
GB2341773A GB9827010A GB9827010A GB2341773A GB 2341773 A GB2341773 A GB 2341773A GB 9827010 A GB9827010 A GB 9827010A GB 9827010 A GB9827010 A GB 9827010A GB 2341773 A GB2341773 A GB 2341773A
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Prior art keywords
data
packets
idma
memory
host
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GB9827010A
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GB9827010D0 (en
Inventor
Deog-Nyoun Kim
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WiniaDaewoo Co Ltd
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Daewoo Electronics Co Ltd
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Publication of GB9827010D0 publication Critical patent/GB9827010D0/en
Publication of GB2341773A publication Critical patent/GB2341773A/en
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    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L12/00—Data switching networks
    • H04L12/28—Data switching networks characterised by path configuration, e.g. LAN [Local Area Networks] or WAN [Wide Area Networks]
    • H04L12/40—Bus networks
    • H04L12/40006—Architecture of a communication node
    • H04L12/40032—Details regarding a bus interface enhancer
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/14—Handling requests for interconnection or transfer
    • G06F13/20—Handling requests for interconnection or transfer for access to input/output bus
    • G06F13/28—Handling requests for interconnection or transfer for access to input/output bus using burst mode transfer, e.g. direct memory access DMA, cycle steal
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L12/00—Data switching networks
    • H04L12/28—Data switching networks characterised by path configuration, e.g. LAN [Local Area Networks] or WAN [Wide Area Networks]
    • H04L12/2801—Broadband local area networks
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L12/00—Data switching networks
    • H04L12/28—Data switching networks characterised by path configuration, e.g. LAN [Local Area Networks] or WAN [Wide Area Networks]
    • H04L12/2854—Wide area networks, e.g. public data networks
    • H04L12/2856—Access arrangements, e.g. Internet access
    • H04L12/2858—Access network architectures

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  • Engineering & Computer Science (AREA)
  • Computer Networks & Wireless Communication (AREA)
  • Signal Processing (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Communication Control (AREA)
  • Bus Control (AREA)

Abstract

A peripheral component 380 is interfaced to a system bus 320 through a peripheral component interface (PCI) bridge. Data packets are transferred between the system memory 360 and peripheral component 380 through the PCI bridge using an independent direct memory access (IDMA) technique. An IDMA register in the PCI bridge 370 is first set according to a predetermined rule when a command signal is received from the system CPU 350. A control signal is then read from the host memory 381 of the peripheral component indicating an empty address in the host memory. An IDMA register in the PCI bridge is set based on header information in data packets and an IDMA channel is obtained between the PCI bridge and the CPU. Data packets are then retrieved from the system memory and sent to the host memory via the PCI bridge. Transmitting data packets from the host memory to system memory is the reverse sequence.

Description

2341773 HOST INTERFACING METHOD AND APPARATUS FOR USE IN A DATA
COMMUNICATION SYSTEM The present invention relates to a data communication system; and, more particularly, to a host interfacing method and apparatus for use in a data communication system.
As the so-called information highway is being developed, a wide communication channel which interconnects households and businesses provides many services to those who are connected thereto. These services may include banking at home, instant access to large databases and real time interaction with virtual communities of people with similar interests.
These days, an interactive communication system such as a computer communication system or a video on demand (VOD) system requires a transmission medium that can support a high speed data communication with a great deal of transmission data.
Since, however, the available transmission media are practically limited, an efficient host interfacing apparatus is essential to realize a high speed data communication under the limited data transmission capability of a corresponding transmission medium.
Fig. 1 provides a block diagram for illustrating a conventional host interfacing apparatus 20 for use in a data communication system 10.
The data communication system 10, e.g., a cable modem system, comprises a termination system (TS) 105, a transmitting/receiving data processing (TRDP) channel 100, a system bus 160, the host interfacing apparatus 20, an ethernet bus 200 and peripheral components (PCs) 201, 203 and 205. The host interfacing apparatus 20 includes a central processing unit (CPU) 170, a random access memory 180 and an ethernet connection circuit 190. The ethernet connection circuit 190 has an ethernet controller 191, a transceiver 193 and a connector 195.
In the data communication system 10, in case that data packets are transmitted from one of the PCs 201, 203 and 205 to the TS 105, e.g., a cable modem termination system (CMTS), the host interfacing apparatus 20 Performs a host interfacing to transmit the data-packets therebetween.
The TRDP channel 100 receives the data-packets via a line L21 carried on the system bus 160 via the host interfacing apparatus 20 from one of the PCs 201, 203 and 205 through the ethernet bus 200. Thereafter, the TRDP channel 100 transmits the data-packets to the TS 105 via a line L11, e.g., a coaxial cable or a twisted conductor wire, after processing the data packets by employing a conventional TRDP technique.
In the data communication system 10, in case that data packets are transmitted from the TS 105 to one of the PCs 201, 203 and 205, the TRDP channel 100 receives the data-packets from the TS 105 via the line L11 to transmit them to the host interfacing apparatus 20 through the system bus 160 after processing the data-packets by employing a conventional TRDP technique therein.
Then, the host interfacing apparatus 20 performs a host interfacing to send the data-packets to one of the PCs 201, 203 and 205 by way of the ethernet bus 200.
Fig. 2 represents a detailed block diagram of the TRDP channel 100 illustrated in Fig. 1. The TRDP channel 100 includes a diplexer 110, a data receiving circuit 120, a data transmitting circuit 130, a medium access controller (MAC) 140 and an encrypt ion/decrypt ion (E/D) circuit 150. The data is receiving circuit 120 has a tuner 121, an analog to digital (A/D) converter 123 and a demodulator 125. The data transmitting circuit 130 has a low pass filter (LPF) 131, a digital to analog (D/A) converter 133 and a modulator 135.
Referring to Figs. 1-2, the structure /f unction of the conventional host interfacing apparatus 20 and a host interfacing method therefor will now be described in detail.
First, the case that data-packets are transmitted from one of the PCs, e.g., personal computers, 201, 203 and 205 to the TS 105 will be described.
For the sake of illustration, if a user of the PC 201 sends data-packets to the TS 105, the PC 201 first loads up the data-packets on the ethernet bus 200 in response to a data sending command signal issued by a corresponding key operation of the user. The ethernet controller 191 receives the data packets from the ethernet bus 200 through the transceiver 193 and the connector 195.
Then, the ethernet controller 191 regards the PC 201 as a master and the other PC as a slave by using a conventional master/slave discrimination technique if there are no data packets currently loaded up by another PC, i.e., if there is no collision between data-packets, thereby outputting the data-packets on the system bus 160.
On the other hand, the ethernet controller 191 regards the PC 201 as a slave and the other PC as a master by using the conventional master/slave discrimination technique to thereby return a waiting command signal to the PC 201 if there are data-packets currently loaded up by another PC, e.g., the PC 203, i.e., if there is collision between data-packets.
The CPU 170 stores the data-packets outputted on the system bus 160 in the RAM 180 on a packet -by-packet basis; and retrieves the data-packets from the RAM 180 to the MAC 140 in the TRDP channel 100 via a line L21 through the system bus 160 in case that a data sending request signal is issued by the MAC 14 0.
The MAC 140 encrypts the data-packets through the E/D circuit 150 to send the encrypted data-packets to the modulator 135 through a line L15. The modulator 135 modulates the encrypted data-packets to thereby provide the modulated data-packets to the D/A converter 133. The D/A converter 133 converts the modulated data-packets into an analog signal to supply same to the LPF 131.
The LPF 131 performs filtering on the analog signal to reduce or eliminate noises therein, thereby feeding the filtered analog signal to the diplexer 110 through a line L13.
The diplexer 110 provides the filtered analog signal to the TS 105 via the line L11.
Next, the case that data-packets are transmitted from the termination system 105 to one of the PCs 201, 203 and 205 is described.
First, the diplexer 110 receives an analog signal, e.g., a radio frequency (RF) broadcasting signal, from the TS 105 via the line L11 and then provides the received analog signal to the tuner 121 through a line L12. The tuner 121 performs tuning on the received analog signal to thereby provide the tuned signal to the A/D converter 123. It should be noted that if the analog signal is not a broadcasting signal, the tuner 121 is not needed.
The A/D converter 123 converts the tuned analog signal into a digital signal and then supplies same to the demodulator 125. The demodulator 125 demodulates the digital signal to thereby supply the demodulated signal as data packets to the MAC 140 via a line L14.
The MAC 140 checks an identification signal (IS) of the data-packets and then decrypts the data-packets through the E/D circuit 150 if the IS of the demodulated signal is equal to a preset IS stored therein; and in turn outputs the decrypted data-packets on the system bus 160 through the line L2 1.
Thereafter, the CPU 170 controls the RAM 180 to store the data-packets from the system bus 160 on a packet -by- packet basis. The CPU 170, if a data reception request signal is fed thereto from the ethernet controller 191, retrieves the data- packets from the RAM 180 and then loads up same on the system bus 160.
Then, the ethernet controller 191 receives the datapackets to provide same to the transceiver 193. The transceiver 193 outputs the data-packets on the ethernet bus 200 by way of the connector 195. Finally, the data-packets are transmitted to a corresponding PC, e.g., one of the PCs 201, 203 and 205.
Since, however, the conventional host interfacing apparatus and method utilizes a direct memory access (DMA) technique employing a master/slave discrimination technique, the conventional host interfacing apparatus and method may entail a transmission speed decrease in case that a plurality of PCs are connected to the host interfacing apparatus.
Further, since the conventional host interfacing apparatus employs an ethernet bus to connect a plurality of PCs, it is necessary for each PC to be equipped with a local area network (LAN) card therein, thereby increasing the manufacturing cost thereof.
Embodiments of the present invention may provide a host interfacing method and apparatus provided with a PCI bridge and an independent direct memory access (IDMA) technique, thereby enhancing the data transmission efficiency as well as decreasing the manufacturing cost thereof.
In accordance with one aspect of the present invention, there is provided a host interfacing method for use in a data communication system provided with a system bus, a system memory for storing data-packets therein, a peripheral component interface (PCI) bridge having a plurality of independent direct memory access (IDMA) registers and a peripheral component (PC) having a driver and a host memory, the method comprising the steps of: (a) setting an IDMA register in the PCI bridge in accordance with a predetermined setting rule in case that a data-packet receiving command signal is fed to the PCI bridge; (b) reading a control signal from the host memory, wherein the control signal informs an address of an empty space in the host memory; (c) checking, based on the control signal, whether an empty space exists or not in the host memory to thereby read header information of the data-packets in case that the empty space exists; (d) setting, based on the header information, the IDMA register in the PCI bridge in accordance with a predetermined setting rule; (e) obtaining an IDMA channel for the data-packets; (f) retrieving the data-packets from the system memory; (g) sending the data-packets to the PCI bridge; and (h) transmitting the data- packets to the host memory.
In accordance with another aspect of the present invention, there is also provided a host interfacing apparatus for use in a data communication system including a system bus and a peripheral component (PC) having a driver and a host memory, the host interfacing apparatus comprising: a central processing unit (CPU), coupled to the system bus, for performing a control on the system; a system memory coupled to the system bus, for storing data-packets accessed through the system bus; and a peripheral component interconnect (PCI) bridge, coupled to the system bus, for performing an interfacing on the data- packets accessed between the system bus and the PC by using an independent direct memory access (IDMA) technique, the PCI bridge being connected to the driver and the host memory in the PC.
The above and other objects and features of the present invention will become apparent from the following description of preferred embodiments given with reference to the accompanying drawings, in which:
8 Fig. 1 provides a block diagram for illustrating a conventional host interfacing apparatus for use in a data communication system; Fig. 2 represents a detailed block diagram of the transmitting/receiving data processing channel illustrated in Fig. 1; Fig. 3 shows a block diagram for showing a host interfacing apparatus for use in a data communication system in accordance with a preferred embodiment of the present invention; Fig. 4 depicts a detailed block diagram of the peripheral component interconnect (PCI) bridge shown in Fig. 3; and Figs. 5 and 6 set forth flow charts for illustrating host interfacing methods in accordance with preferred embodiments of the present invention.
Preferred embodiments in accordance with the present invention will now be described in detail with reference to Figs. 3 to 6.
Fig. 3 shows a block diagram for showing a host interfacing apparatus 40 for use in a data communication system 30 in accordance with a preferred embodiment of the present invention.
The data communication system 30 comprises a termination system (TS) 305, a transmitting/receiving data processing (TRDP) channel 310, a system bus 320, the host interfacing apparatus 40 and a peripheral component (PC) 380.
The host interfacing apparatus 40 includes a central processing unit (CPU) 350, a system memory 360 and a peripheral component interconnect (PCI) bridge 370. The PC 380 includes a host memory 381 and a driver 383.
The CPU 350, coupled to the system bus 320 via a line L301, performs a control on the data communication system 30. The system memory 360, coupled to the system bus 320 via a line L401, stores data-packets accessed through the system bus 320 under the control of the CPU 350.
The PCI bridge 370, coupled to the system bus 320 via a line L501, performs an interfacing to transmit data-packets between the system bus 320 and the PC 380 by using an independent direct memory access (IDMA) technique, wherein the PCI bridge 370 is connected to the host memory 381 and the driver 383 via lines L601 and L701, respectively.
In the data communication system 30, in case that datapackets are transmitted from the PC 380 to the TS 305, e.g., a cable modem termination system (CMTS), the host interfacing apparatus 40 performs a host interfacing to transmit the datapackets therebetween. The TRDP channel 310 receives the datapackets via a line L201 carried on the system bus 320 by way of the host interfacing apparatus 40 from the PC 380.
Thereafter, the TRDP channel 310 transmits the data-packets to the TS 305 via a line L101, e.g., made of a coaxial cable, after processing the data-packets by employing a conventional TRDP technique.
On the other hand, in case that data-packets are transmitted from the TS 305 to the PC 380, the TRDP channel 310 receives the data-packets from the TS 305 via the line L101 to transmit the data-packets to the host interfacing apparatus 40 through the system bus 320 after processing the data-packets by employing the conventional TRDP technique therein. The host interfacing apparatus 40 performs a host interfacing to send the data-packets to the PC 380.
Referring to Fig. 4, there is depicted a detailed block diagram of the PCI bridge 370 shown in Fig. 3. The PCI bridge 370 has a system bus interface 371, a first buffer memory 373, a second buffer memory 375, a PC interface 377 and an IDMA control circuit 379.
The IDMA control circuit 379 contains a plurality of IDMA registers (not shown) therein, wherein the IDMA control circuit 379 controls the system bus interface 371 and the PC interface 377; and the IDMA registers are set under the control of a control logic (not shown) included in the IDMA control circuit 379 and/or the control of the CPU 350. it should be noted that the IDMA registers are classified into three groups: address registers; size registers; and control & status registers.
Figs. 5 and 6 set forth flow charts for illustrating host interfacing methods in accordance with preferred embodiments of the present invention. From now on, referring to Figs. 3 to 6, the host interfacing methods and the structure/ f unction of the host interfacing apparatus 40 in accordance with preferred embodiments of the present invention will be described in detail. For the sake of simplicity, the description therefor is focused on the data communication between the system bus 320 and the PC 380 intermediated through the host interfacing apparatus 40.
Fig. 5 sets forth a flow chart for illustrating a host interfacing process or method in accordance with a preferred embodiment of the present invention in case that data-packets are transmitted from the TRDP channel 310 to the PC 380 through the system bus 320. In this case, the host interfacing apparatus 40 receives the data-packets from the TRDP channel 310 through the system bus 320 and then stores the data-packets in the system memory 360.
The host interfacing process is initiated when the CPU 350 issues a data-packet receiving command signal to send it to the PCI bridge 370 through the system bus 320.
Referring to Fig. 5, at step 411, an IDMA register in the PCI bridge 370 is set in accordance with a predetermined setting rule when the data-packet receiving command signal is fed to the PCI bridge 370. Then the process goes to step 412.
At step 412, a control signal is read from the host memory 381, e.g., by the CPU 350, wherein the control signal informs an address of an empty space in the host memory 381.
The process flows to step 413.
It should be noted that in accordance with a preferred embodiment of the present invention, at step 411, the IDMA register is set under the control of the CPU 350 by using a source address having the control signal from the host memory; a destination address for the control signal; and a value for the number of bytes relating a size of the control signal.
At step 413, based on the control signal, it is checked, e.g., by the CPU 350 whether or not an empty space exists in the host memory 381. The process flows to step 414 if there exists an empty space in the host memory 381; and if otherwise, the process is ended. It should be noted that the IDMA control circuit 379 in the PCI bridge 370 sends the control signal via the system bus 320 to the CPU 350 by way of the system bus interface 371, thereby allowing the CPU 350 check whether an empty space exists or not in the host memory 381 by using the control signal.
At step 414, header information of the data-packets stored in the system memory 360 is read, e.g., by the CPU 350 and then the process goes to step 415. At step 415, based on the header information, the IDMA register within the IDMA control circuit 379 in the PCI bridge 370 is set in accordance with a predetermined setting rule, e.g., under the control of the CPU 350.
It should be noted that in accordance with a preferred embodiment of the present invention, at step 415, the IDMA register within the IDMA control circuit 379 is set by using a value for a length of the data-packets.
Then, at step 416, an IDMA channel for the data-packets is obtained, e.g., by the CPU 350. In other words, the IDMA channel for the data-packets is formed between the CPU 350 and the PCI bridge 370. It should be noted that in accordance with the present invention, the CPU 350 is a CPU, e.g., MC68360, MPC860 or MPC850 supplied by Motorola Co., having IDMA channel support function.
Thereafter, at step 417, the data-packets are retrieved from the system memory 360, e.g., under the control of the CPU 350 and then the process goes to step 418. At step 418, the data-packets are sent to the PCI bridge 370, e.g., under the control of the CPU 350 and then the process flows to step 419.
1.5 At step 419, the data-packets are transmitted to the host memory 381 in the PC 380, e.g., a personal computer and then, the process is ended.
It should be noted that at steps 418 and 419, the datapackets interfaced by the system bus interface 371 are stored in the f irst buf f er memory 373, e.g., as a f irst-in/f irst-out (FIFO) memory, and then transmitted to the host memory 381 through the PC interface 377.
It should be also noted that in the Steps 411 and 415, the IDMA register is set on a packet-by-packet basis; and in case that the data-packet receiving command signal is fed to the PCI bridge 370, the driver 383 prepares an empty space in the host memory 381 to store the data-packets therein.
Fig. 6 sets forth a flow chart for illustrating a host interfacing process or method in accordance with a preferred embodiment of the present invention in case that data-packets are transmitted from the PC 380 to the TRDP channel 310 through the system bus 320. In this case, an interrupt is issued by the driver 383 in case that a data-packet sending command signal generated by a corresponding key operation of the user is fed to the driver 383.
The host interfacing process is initiated when the driver 383 issues to send the interrupt to the CPU 350 via the system bus 320 by way of the PCI bridge 370. At step 510, the CPU 350 searches whether an interrupt issued from the driver 383 exists or not. If there exists the interrupt, the process goes to step 511; and if otherwise, the process is ended.
At step 511, an IDMA register within the IDMA control circuit 379 in the PCI bridge 370 is set in accordance with a predetermined setting rule and then the process goes to step 512. At step 512, a control signal is read from the host memory 381, e.g., by the PCI bridge 370, wherein the control signal informs an address of a space storing data-packets in the host memory 381. And then process flows to step 513.
It should be noted that in accordance with a preferred embodiment of the present invention, at step 511, the IDMA register is set by using a source address having the control signal from the host memory 381; a destination address for the control signal; and a value for the number of bytes relating a size of the control signal.
At step 513, based on the control signal, the IDMA register within the IDMA control circuit 379 in the PCI bridge 370 is set in accordance with a predetermined setting rule and then the process goes to step 514.
It should be noted that in accordance with a preferred embodiment of the present invention, at step 513, the IDMA register in the IDMA control circuit 379 is set by using a value for a length of the data-packets. It should be also noted that in the steps 511 and 513, the IDMA register is set on a packet-by-packet basis.
At step 514, the data-packets are read from the host memory 381. Then, at step 515, the data-packets are stored, e.g., within the second buffer memory 375, e.g., as FIFO memory in the PCI bridge 370. The process flows to step 516 thereafter. It should be noted that the data-packets are interfaced by the PC interface 377 between the host memory 381 and the second buffer memory 375.
At step 516 an IDMA channel for the data-packets are obtained, e.g., by the CPU 350. In other words, the IDMA channel for the data-packets is formed between the CPU 350 and the PCI bridge 370. Thereafter, at step 517, the data-packets are retrieved from the second buffer memory 375, e.g., under the control of the CPU 350. And then at step 518, the retrieved data-packets are transmitted to the system memory 360, e.g., under the control of the CPU 350. Then, the process is ended. In detail, at steps 517 and 518, the data- packets stored in the second buffer memory 375 are retrieved therefrom and then loaded up on the system bus 320 through the system bus interface 371.
Further, the CPU 350 controls the system memory 360 to store the datapackets loaded up on the system bus 320. Thereafter, the CPU 350, if a data sending request signal is fed thereto from the TRDP channel 310, retrieves the data- packets from the system memory 360 to transmit same to the TRDP channel 310 through the system bus 320.
While the present invention has been described with respect to certain preferred embodiments only, other modifications and variations may be made without departing from the scope of the present invention as set forth in the following claims.
17 -

Claims (17)

Claims
1. A host interfacing method for use in a data communication system provided with a system bus, a system memory for storing data-packets therein, a peripheral component interface (PCI) bridge having a plurality of independent direct memory access (IDMA) registers and a peripheral component (PC) having a driver and a host memory, the method comprising the steps of:
(a) setting an IDMA register in the PCI bridge in accordance with a predetermined setting rule in case that a data-packet receiving command signal is fed to the PCI bridge; (b) reading a control signal from the host memory, wherein the control signal informs an address of an empty space in the host memory; is (c) checking, based on the control signal, whether an empty space exists or not in the host memory to thereby read header information of the data-packets in case that the empty space exists; (d) setting, based on the header information, the IDMA register in the PCI bridge in accordance with a predetermined setting rule; (e) obtaining an IDMA channel for the data-packets; (f) retrieving the data-packets from the system memory; (g) sending the data-packets to the PCI bridge; and (h) transmitting the data-packets to the host memory.
2. The method according to claim 1, wherein in said step (a), the IDMA register is set by using a source address having the control signal from the host memory; a destination address for the control signal; and a value for the number of bytes relating a size of the control signal.
3. The method according to claim 1 or 2, wherein in said step (d), the IDMA register is set by using a value for a length of the data-packets.
4. The method according to claim 3, wherein in said steps (a) and (d), the IDMA register is set on a packet -by-packet basis.
5. The method according to claim 4, wherein in case that the data-packet receiving command signal is fed to the PCI bridge, the driver prepares an empty space in the host memory to store the data-packets therein.
6. A host interfacing method to transmit a data packet for use in a data communication system provided with a system bus, a system memory, a peripheral component interface (PCI) bridge having a plurality of independent direct memory access (IDMA) registers and a peripheral component (PC) having a driver and a host memory storing data-packets therein, the method comprising the steps of:
(a) searching whether an interrupt issued from the driver exists or not; (b) setting an IDMA register in the PCI bridge in accordance with a predetermined setting rule in case that there exists the interrupt; (c) reading a control signal from the host memory, wherein the control signal informs an address of a space storing data-packets in the host memory; (d) setting, based on the control signal, the IDMA register in the PCI bridge in accordance with a predetermined setting rule; (e) reading the data-packets stored in the host memory; (f) storing the data-packets in the PCI bridge; (g) obtaining an IDMA channel for the data-packets; (h) retrieving the data-packets from the PCI bridge and then transmitting the data-packets to the system memory.
7. The method according to claim 6, wherein in said step (b), the IDMA register is set by using a source address having the control signal from the host memory; a destination address for the control signal; and a value for the number of bytes relating a size of the control signal.
8. The method according to claim 6 or 7, wherein in said step (d), the IDMA register is set by using a value for a length of the data- packets.
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9. The method according to claim 8, wherein in said steps (b) and (d), the IDMA register is set on a packet -by-packet basis.
10. The method according to any of claims 6 to 9, wherein said interrupt is issued by the driver in case that a data-packet sending command signal generated by a corresponding key operation of a user is fed to the driver.
11. A host interfacing apparatus for use in a data communication system provided with a system -bus and a peripheral component (PC) having a driver and a host memory, the host interfacing apparatus comprising:
a central processing unit (CPU), coupled to the system bus, for performing a control on the system; a system memory coupled to the system bus, for storing data-packets accessed through the system bus; and a peripheral component interconnect (PCI) bridge, coupled to the system bus, for performing an interfacing to transfer the data-packets accessed between the system bus and the PC by using an independent direct memory access (IDMA) technique, the PCI bridge being connected to the driver and the host memory in the PC.
12. The apparatus according to claim 11, wherein the PCI bridge includes:
a system bus interface for performing interface between the system bus and the PCI bridge; a PC interface for interfacing between the PCI bridge and the PC; a first buffer memory for storing data-packets fed thereto from the PC through the PC interface; a second buffer memory for storing the data-packets fed thereto from the system bus through the system bus interface; and an IDMA control circuit to control the system bus interface and the PC interface, wherein the IDMA control circuit has a plurality of IDMA registers being classified into three groups: address registers; size registers; and control & status registers, each of the IDMA registers being set under the control of the CPU.
13. The apparatus according to claim 11 or 12, wherein the PC is a personal computer.
14. The apparatus according to any of claims 11 to 13, wherein the CPU has an IDMA channel support function.
15. The apparatus according to any of claims 11 to 14, wherein the first buffer memory and the second buffer memory are first-in/first-out (FIFO) memory's respectively.
16. A host interfacing apparatus constructed and arranged substantially as herein described with reference to or as shown in Figs. 3 and 4 of the accompanying drawings.
17. A host interfacing method constructed and arranged substantially as herein described with reference to or as shown in Figs. 5 and 6 of the accompanying drawings.
23
GB9827010A 1998-09-16 1998-12-08 Host interfacing method and apparatus in a data communication system Withdrawn GB2341773A (en)

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Application Number Priority Date Filing Date Title
KR1019980038272A KR100297840B1 (en) 1998-09-16 1998-09-16 Host interface method of cable modem

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GB9827010D0 GB9827010D0 (en) 1999-02-03
GB2341773A true GB2341773A (en) 2000-03-22

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GB9827010A Withdrawn GB2341773A (en) 1998-09-16 1998-12-08 Host interfacing method and apparatus in a data communication system

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GB (1) GB2341773A (en)

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