GB2341271A

GB2341271A - Method of fabricating capacitor

Info

Publication number: GB2341271A
Application number: GB9819061A
Authority: GB
Inventors: Gary Hong
Original assignee: United Semiconductor Corp
Current assignee: United Semiconductor Corp
Priority date: 1998-09-01
Filing date: 1998-09-01
Publication date: 2000-03-08
Anticipated expiration: 2018-09-01
Also published as: GB9819061D0; GB2341271B

Abstract

In a method of fabricating a capacitor for a DRAM, a bottom electrode is formed from a doped polysilicon layer 38a deposited on an insulation layer 36 and extending through a via hole to contact a source/drain region 34a of a MOS transistor. The polysilicon layer 38a is covered with a layer of silicon nitride 39b, and the two layers 38a,39b are patterned together using a photoresist mask 40a. Part of the mask is then removed by a plasma process, and a peripheral region of the underlying silicon nitride is etched away. The remainder of the mask is removed and a silicon oxide layer (41) is deposited on the exposed side and top regions of the polysilicon layer. The remaining silicon nitride is then etched away by phosphoric acid and the polysilicon layer is etched using the oxide layer (41) as a mask to form a cylindrical crown-shaped bottom electrode 38b. This is then covered with an HSG-Si layer 42, a dielectric layer 43 such as ONO and a further conductive layer forming an upper electrode 44. This method allows a reduction in the thickness of the cylindrical wall of the bottom electrode.

Description

1 2341271 IMETHOD OF FABRICATING CAPACITOR

BACKGROUND OF THE INVENTION 5 Field of the Invention

The invention relates to a method of fabricating a capacitor in an integrated to a method of fabricating a capacitor n a d-,n c circuit (IC), and more particularl- i ami random access memory (DRAM).

1 C Description of the Related Art

Figure I shows a single memory cell comprising a transfer transistor T and a capacitor C of a DRA.M The source of the transfer transistor T is coupled with a corresponding bit line BL. The drain of the transfer transistor T is coupled with a storing electrode 10 of the capacitor C, and the gate of the transfer transistor T is coupled with a corresponding word line WL. An opposed electrode 12 to the storing electrode 10 is coupled with a constant voltage supply, and a dielectric layer 14 is formed between the storing electrode 10 and the opposed electrode 12.

To increase the storing capacitance in the capacitor, apart from using material with a high dielectric constant for the dielectric layer, or controlling the deposition thickness and quality for the dielectric layer, by increasing the surface area of the storing electrode. a higher capacitance can be also obtained. However, as the dimension of memory becomes smaller, to fabricate a storing electrode with a larger surface area on the smaller substrate becomes a serious problem.

2 In a single chip, to increase data storage, the storing density of a memory I in an IC is increased. The high density of a memory provides a storing structure with a higher inte-ration. Normally. the density of an IC device is increased by means of reducinQ the dimensions of.viring lines. transistor gates. or device isolation re!zions.

The reduction of the dimension of devices and structures is accordin2 to the desl(2n rule of semiconductor fabrication.

To increase the surface area of a bottom electrode. that is. a storin2 electrode. an uneven surface structure, for example, a cro,,vri structure. a cylinder structure. a fin structure. a tree-like structure. or a cavity structure, is adapted to provides a larger 1C surface area. On the surface of above structures, an hemispherical grain (HSG) is further formed to increase the surface area. With the formation of the HSG str-ucture.

the capacitance gain is up to I.S.

In the conventional technique of fabricating a crown structure bottom electrode as shown in Figure 2, a poly-silicon laver 25 is patterned by using photo litho graphy to Ir form a bottom electrode on a semiconductor substrate -10. The substrate 20 further comprises a word line 2 1 of an metal-oxide-semiconductor (.140S), a bit line 221, a drain reLyion ")3, and an insulation laver 24. Being restricted by the photo- source, 1 -1 1 resolution of the desian rule, during exposure, the width u of the top branch of the C - crown structure can not be reduced unlimitedly, the capacity of increasing the surface area is therefore limited.

SUMMARY OF THE INVENTION

It is therefore an object of the invention to provide a method of fabricating a 3 crown structure capacitor by self-align process. The restriction of design rule and photo-resolution is overcome, and the misalignment during exposure is improved.

To achieve these objects and advantages, and in accordance with the purpose of the invention. as embodied and broadly described herein. the invention is directed 9 towards a method of fabricating a capacitor. On a semiconductor substrate having a metal -oxide-semiconductor. which comprising a source/drain region coupled with a bit line. form thereon. a first insulation layer is formed to cover the transistor and the substrate. The first insulation layer is patterned to form a via hole which penetrates through the first insulation layer, so that a source/drain region of the transistor is exposed. A poly-silicon layer is formed on the first insulation layer and fills the via hole. A silicon nitride laver is formed on the poly-silicon laver. A photo-resist laver is formed and patterned on the silicon nitride layer to define the silicon nitride layer and the poly-silicon layer, so that a cylinder structure comprising the silicon nitnde layer, the poly-silicon layer including the poly-silicon within the via hole is formed. A part of the photo-resist layer is removed to define the silicon nitride layer, so that a rim of a top surface and a side wall of the poly-silicon layer are exposed. A silicon oxide layer is formed on the exposed poly-silicon layer. By removing the silicon nitride layer, the poly-silicon layer which is not covered by the silicon oxide laver is exposed. The exposed poly-sillcon laver is removed by using the silicon oxide laver as a mask, until a crown structure is formed. The silicon oxide layer is removed. An hemispherical grain silicon layer is formed on the poly-silicon layer. A dielectric layer is formed on the hemispherical grain silicon laver, and a second conductive laver is formed on the dielectric layer.

4 It is to be understood that both the foregoing general description and the following detailed description are exemplary and explanatory only and are not restrictive of the invention as claimed.

BRIEF DESCRIPTION OF THE DP_kWTNGS

Figure I is a circuit diagram of a conventional DRA.M, Figure 2 is a cross sectional of a bottom electrode of a conventional DRA-M capacitor. and Figure 3A to Figure 31 are cross sectional views of the process for fabricating a ic" capacitor in a DRAM in a preferred embodiment according to the invention.

DESCRIPTIONTOF THE PREFERRED ENIBODEMENTS

In Figure 3A, a device isolation structure 3 1, for example, a field oxide laver with a thickness of about 3000_!-N formed by local oxidation (LOCOS), or a shallow trench, is formed on a silicon substrate 30. Usin2 thermal oxidation process, a gate ide la, 1 -1 oxi -er 32 is formed on the substrate 3 30. A doped pol-, -silicon laver is forn ed, for example, by chemical vapour deposition (CVD), and patterned to form a gate 33 (or word line) on the gate oxide layer 32. A source/drain region 34a, 34b is formed in the substrate 30. By a conventional technique, a poly-silicon layer is formed and patterned as a bit line 35 to couple with one of the source/drain region 34a, 34b. The word line 33 and the bit line 35 are separated by an insulation layer.

Referring Fig. 3B, a planar insulation layer 36 is formed, for example, by CVD to cover the word line 33) and the bit line 35. The planar insulation layer 36 is, for example, a borophosphosilicate glass (BPSG) formed by atmospheric pressure CVD (APCVD) or plasma enhanced CVD (PECVD). After deposition, the insulation layer is planarized by reflow or chemical-mechanical polishing (CN/IP). The process of I planarization is advantageous to the subsequent deposition and photo llthograph processes. For example. a more accurate pattern of the via or other structures is obtained during exposure. Using photolithography, a via hole 37 is formed to penetrate through the insulation layer 36, so that the source/drain region 34a is exposed within the via hole 37.

Referring to Fig. 33C. a first poly-silicon layer 38 is formed on the insulation layer 36 and fills the via hole 37. The first poly-silicon layer 38 is doped and has a thickness of about 1000A to 10000A. A blanket silicon nitride layer 39 having a thickness of about 50A to 1000A is formed on the first poly-silicon layer 38. On the silicon nitride layer 39. a photo-resist layer 40 is formed and patterned. Using the photo-resist layer 40 as a mask, the silicon nitride layer _339 and the first poly-silicon layer 40 are defined, for example, by dry etch, to form a cylinder structure comprising a silicon nitrnide laver 339a and a first poly-silicon layer 38a as shown in Figure 3)D. The cylinder structure further comprises the first poly-silicon laver filled in the via hole 37.

A part of the photo-resist layer 40 is removed, for example, by isotropic plasma process in an oxygen environment to transform a part of the photo-resist laver 40 to ash.

The remaining photo-resist layer 40a is in a form as shown in Figure 3E. Using the remaining photo-resist layer 40a as a mask to define the silicon nitride layer 39a. A part of the silicon nitride layer 39a, that is, the part which is not covered by the photo resist layer 40a. is removed, for example, by dry etch. Thus, a rim on the top surface 6 and a side wall of the first poly-silicon layer -338a are exposed, as shown in Figure 3F. On the other hand, only the central top surface of the first poly-silicon layer 38a is covered by the remaining silicon nitride layer 39b. The photo-resist layer 40a is then removed.

Referring to Fig. 3G. a silicon oxide laver 41 with a thickness of about 100A to '000A is formed by thermal oxidising the surface of the exposed first polv-silicon laver 39a.

The remaining silicon nitride layer 39b is removed. for example, by wet etching using hot phosphoric acid as an etchant. Therefore, the first poly-silicon layer 38a uncovered bv the silicon oxide laver 41 is exposed. Referring to Figure 33H, using dry etching. the exposed first poly-silicon layer 38a is etched. A crown structured pot-,silicon laver 38b is formed by controlling the etching time.

In the above process. a self-align process for fabricating a crown structure 38b is used, so that the width v of the circum-colu= of the crown structure 38b is not restricted by photo-resolution during photo I itho graphy. That is, the width v can be reduced as required. With the reduction of the width v, a larger surface of the bottom electrode is obtain, and therefore. the capacitance is increased.

Referring to Figure 31, the oxide layer 41 is removed. An HSG-Si layer 41 is selectively formed on the crown structure 38b. The HSG-Si laver 42 is doped with dopant. A bottom electrode is formed by the assemble of the HSG-Si layer 42 and the crown structure 38b. A dielectric layer 43, for example, an oxide/nitnde/oxide (ONO) layer is formed on the HSG-Si layer 42. On the dielectric layer 43, a top electrode 44 is formed.

7 In the above embodiment, a crown structured bottom electrode is formed by self align process. The restriction of design rule for fabrication, and the limited dimension reduction of devices due to photo-resolution are overcome. With the deposition of HSG on the crown structure. the surface area is further increased. The capacitance is increased further-more.

Other embodiment of the invention will appear to those skilled in the art from consideration of the specification and practice of the invention disclosed herein. It is intended that the specification and exam les considered as exemplary only, with the true p scope and spirit of the invention being indicated by the following claims.

Claims

8 WHAT IS CLAIMED IS. I. A method of fabricatina a capacitor. wherein a

semiconductor substrate having a metal -oxi de-semi conductor transistor is provided, comprising: forming a first insulation laver to cover the transistor and the substrate. patterning the first insulation laver to form a via hole which penetrates through the first insulation layer. so that a source,'drain region of the transistor is exposed. formin2 a first conductive layer on the first insulation layer and fills the via hole: formina a second insulation layer on the first conductive laver: forming and patterning a photo-resist layer on the second insulation layer to define the second insulation laver and the first conductive laver. so that a cvllnder structure comprising the second insulation layer, the first conductive laver including the first conductive layer within the via hole is formed, removing a part of the photo-resist laver to define the second insulation laver. so that a rim of a top surface and a side wall of the first conductive layer are exposed, forming a silicon oxide laver on the exposed first conductive laver-, removing the second insulation layer, so that the first conductive layer which is not covered by the silicon oxide layer is exposed, removing the exposed first conductive laver by using the silicon oxide laver as a mask, until a croA-n structure is formed, removing the silicon oxide layer; forminQ a dielectric layer on the first conductive layer-, and forminQ a second conductive layer on the dielectnc layer.

9 2. The method according to claim 1, wherein a bit line coupled with another source/drain region of the transistor is further comprised.

3. The method according to claim 1, wherein the first conductive layer includes a doped poly-silicon layer.

irst conductive layer has a 4. The method according to claim 1, wherein the f thickness of about 1 OOOA to 1 OOOOA.

5. The method according to claim 1, wherein the second insulation layer is a silicon nitride layer.

6. The method according to claim 5, wherein the second insulation layer is removed bv wet etchinc, 7. The method according to claim 6, wherein the wet etching is performed by using phosphoric acid.

8. The method according to claim 1, wherein the second insulation layer has a 20 thickness of about 50.A to 1 OOOA.

9. The method according to claim 1, wherein the part of the photo-resist layer is removed by a plasma process in an oxygen environment.

10. The method according to claim 1, wherein silicon oxide layer is formed by thermal oxidation.

11. The method according to claim 1, wherein the silicon oxide layer has a thickness of about 100- to 3000A.

11 The method according to claim 1. wherein before the dielectric laver is formed. an hemispherical grain layer is formed on the first conductive layer.

13. The method according to claim 1. wherein the second conductive layer includes a doped poly-silicon laver.

14. A method of fabricating a capacitor, wherein a semiconductor substrate having a metal-oxide-semiconductor transistor is provided, comprising:

forming a first insulation layer to cover the transistor and the substrate-, patterning the first insulation layer to form a via hole which penetrates through the first insulation laver, so that a source/drain region of the transistor is exposed.

forming a poly-silicon laver on the first insulation laver and fills the via hole; forming a silicon nitride laver on the poly-silicon layer; forming and patterning a photo-resist layer on the silicon nitride layer to define the silicon nitride laver and the poly-silicon laver, so that a cylinder structure comprising 'the silicon nitride laver, the poly-silicon laver including the poly-silicon within the via hole is formed; removing a part of the photo-resist laver to define the silicon nitride laver, so that a rim of a top surface and a side wall of the poly-silicon layer are exposed; forming a silicon oxide laver is on the exposed poly-silicon laver:

removin2 the silicon nitride layer, so that the poly-silicon layer which is not covered by the silicon oxide layer is exposed; removing the exposed poly-sillcon laver by using the silicon oxide laver as a mask. until a crown structure is formed:

removing the silicon oxide layer; forming an hemispherical grain silicon layer on the poly-silicon layer; forming a dielectric layer on the hemispherical grain silicon laver; and formimz a second conductive layer on the dielectric layer.

15. The method according to claim 14, wherein a bit line coupled with another source/drain region of the transistor is fta-ther comprised.

16. The method according to claim 14, wherein the poly-silicon laver is doped with a dopant.

17. The method according to claim 14, wherein the poly-silicon layer has a thickness of about I OOOA to I OOOOA.

18. The method according to claim 14, wherein the silicon nitride layer is removed by wet etching.

12 19. The method according to claim 18, wherein the wet etching is perform, ed by. using phosphonc acid.

20. The method according to claim 14. wherein the silicon nitride layer has a thickness of about 50-, to 1000-.

21. The method according to claim 14, wherein the part of the photoresisz laver is removed by a plasma process in an oxygen environment.

n n The method accord= to claim 14. 1 1 1 -her,-In silicon oxide laver is formed b-,; thermal oxidation.

The method accordinz to claim 11, wherein 1 1 1 the silicon oxide laver has a thickness of about 100,t,-,- to 3000A.

24. The method according to claim 14, wherein the second conductive layer includes a doped poly-silicon layer.

25. A method of fabricating a capacitor, substantially as hereinbefore described with reference to and/or substantially as illustrated in any. one of or any combination of FiLys. 3A to 31 of the accompanying drawings.