GB2341248A

GB2341248A - Interrupt handling for a module of a microprocessor system

Info

Publication number: GB2341248A
Application number: GB9815619A
Authority: GB
Inventors: Roland Hermann Schwarz; Giuseppe Amato
Original assignee: Motorola Inc
Current assignee: Motorola Solutions Inc
Priority date: 1998-07-18
Filing date: 1998-07-18
Publication date: 2000-03-08
Also published as: GB9815619D0

Abstract

Interrupt arrangement for a module 10 of a microprocessor system having a particular interrupt scheme. A number of submodules of the module, e.g. I/O submodules 11-16, each having an interrupt source, are arranged to provide an interrupt signal indicating the state of the interrupt source. Submodule request controllers 30, 40 are each coupled to receive the interrupt signals from a series of submodules, and have a set of interrupt registers (fig. 3) which are arranged to contain interrupt attributes for each interrupt. Interrupt controllers 50, 52 and a Direct Memory Access (DMA) Controller 70 provide an interface between the submodule request controllers 30, 40 and the system. Different interrupt levels of the main and I/O processors of the system and the DMA function are handled by different pairs of registers in the submodule request controllers (fig. 3). The submodule request controllers are the only parts of the design of the module 10 which are dependent upon the interrupt scheme of the system and thus greater design flexibility is provided.

Description

1 -1- 2341248 WWRRMP ANGFMI'lJT

Field of the Invention

This invention relates to an interrupt arrangement suitable for a module of a microprocessor system.

Background of the Invention

Microprocessor systems are being increasingly used in many fields. There is a requirement in such systems for design flexibility, such that when a new application is required, rather than designing a new system from scratch, existing systems and portions thereof can be adapted and re-used for the new application.

A typical microprocessor system includes a central processor, a bus and a number of 'modules', each of which has a particular function. For example, a timing module may be used to trigger a number of events at certain time intervals. Each module may have a number of submodules, which provide one aspect of the overall function of the module. For example, a timing module may have submodules for various time-triggered events.

Modules and submodules help greatly with design flexibility because a designer typically has a library of existing submodules from which appropriate choices can be made, depending upon the requirements of the new system.

However, a problem with this arrangement is that different processors have different interrupt schemes for handling interrupts caused by the submodules. For example, one processor may have 2 interrupt levels, while another has 8 or more. This means that either each submodule library must have a number of similar submodules which perform the same functions but arranged for different interrupt schemes, or that not all features of the processor interrupt scheme will work with all submodules. Either way flexibility is compromised.

This invention seeks to provide an interrupt arrangement which mitigates the above mentioned disadvantages.

Summaa of the Invention According to the present invention there is provided an interrupt arrangement for a module of a microprocessor system, the system having an interrupt scheme, the arrangement comprising: a plurality of submodules, each submodule having an interrupt source and each submodule arranged to provide an interrupt signal indicating the state of the interrupt source; a submodule request controller, coupled to receive the interrupt signals from the plurality of submodules and having a set of interrupt registers which are arranged to contain interrupt attributes for each interrupt source of the plurality of submodules; and, an interrupt controller coupled to the submodule request controller and arranged to provide an interface between the system and the submodule request controller; wherein the interrupt attributes are arranged in dependence upon the interrupt scheme of the system such that interrupts arising from the interrupt sources are adapted to the system.

Preferably the interrupt controller comprises a main processor portion arranged to provide an interface with a main processor of the system, and a peripheral processor portion, arranged to provide an interface with a peripheral processor of the system. The set of interrupt registers preferably include main processor registers arranged to contain interrupt attributes of the main processor of the system, and peripheral processor registers arranged to contain interrupt attributes of the peripheral processor of the system. 30 Preferably the peripheral processor is an input/output (1/0) processor arranged to control the activities of a main bus of the system. The interrupt controller preferably includes a direct memory access control portion arranged to provide a direct memory access interface with the system. 35 Preferably the set of interrupt registers include direct memory access registers arranged to contain interrupt attributes relating to direct memory access. The submodules, submodule request controller and interrupt controller are preferably coupled together via a request bus of the module.

In this way an interrupt arrangement is provided which allows for submodule libraries having generic submodules designed for use with any processor, and which ensures that all interrupt features of a particular interrupt scheme will work with all submodules. Greater design flexibility is thus provided.

Brief Description of the Drawings

An exemplary embodiment of the invention will now be described with reference to the drawing in which:

FIG. 1 shows a preferred embodiment of a microprocessor system in accordance with the invention; FIG. 2 shows the system of FIG. 1 in greater detail; and, FIG. 3 shows a portion of the system of FIGs. 1 and 2.

Detailed Description of a Preferred Embodiment

Referring to FIG. 1, there is shown an interrupt arrangement incorporated in a module 10 of a microprocessor system (not shown). The module includes a number of input/output (1/0) submodules 11-16, which each have an interrupt source and an output (not shown). The interrupt sources may be timing function results, sensor output values, user operated switch outputs or any similar functions to be provided by the submodule.

Each submodule 11-16 is coupled to a request bus 20, to be further described below. First and second request controller submodules (RQSM) 30 and 40 respectively are also coupled to the request bus 20, each containing a number of data registers to be further described below. The first RQSM 30 is arranged to manage interrupt requests from a first series of submodules 11, 12 and 13, and the second RQSM 40 is arranged to manage interrupt requests from a second series of submodules 14, 15 and 16. Each of the first and second RQSMs 30 and 40 respectively is capable of managing up to 16 interrupt requests from 16 different submodules (i.e. the first and second series of submodules may comprise up to 16 submodules).

The request bus 20 is further coupled to first and second interface submodules 50 and 60 respectively and to a Direct memory Access Controller submodule (DMASM) 70, each of which provide an interface to a main bus (not shown) of the microprocessor system. 10 The first interface submodule 50 comprises a first interrupt controller submodule (IRQSM) 52 and a first bus interface submodule (BISM) 54 and is arranged to provide an interface to an 1/0 processor (not shown) connected to the 1/0 bus of the system. 15 The second interface submodule 60 comprises a second interrupt controller submodule (IRQSM) 62 and a second bus interface submodule (BISM) 64 and is arranged to provide an interface to a main processor (not shown) connected to the main bus of the system. 20 Referring now also to FIG. 2, the module 10 is now depicted with signals transmitted on dedicated lines of the request bus 20. Each 1/0 submodule of the first series 11-13 has a flag signal output to the first RQSM 30. Similarly each 1/0 submodule of the second series 14-16 has 25 a flag signal output to the second RQSM 40. The flag signals indicate the interrupt state of the 1/0 submodules. The first RQSM 30 has two interrupt level request lines 201 and 202 coupled to the first IRQSM 52, an interrupt level request line 203 coupled to the 30 second IRQSM 62, and a DMA level request line 204 coupled to the DMASM 70. The first RQSM 30 is also coupled to receive two interrupt level arbitration lines 205 and 206 from the first IRQSM 52, an interrupt level arbitration line 207 from the second IRQSM 62, and a DMA arbitration line 208 and a DMA complete line 209 from the DMASM 70. The first RQSM 30 35 is also coupled to first and second interrupt flag number buses 210 and 220 respectively, and to a DMA flag number bus 230.

Similarly the second RQSM 40 has two interrupt level request lines 211 and 212 coupled to the first IRQSM 52, an interrupt level request line 213 coupled to the second IRQSM 62, and a DAM level request line 214 coupled to the DMASM 70. The second RQSM 40 is also coupled to receive two interrupt level arbitration lines 215 and 216 from the first IRQSM 52, an interrupt level arbitration line 217 from the second IRQSM 62, and a DMA arbitration line 218 and the DMA complete line 209 from the DMASM 70. The second RQSM 40 is also coupled to the first and second interrupt flag number buses 210 and 220 respectively, and to the DMA flag number bus 230.

The first interrupt flag number bus 210 is coupled to the first IRQSM 52, the second interrupt flag number bus 220 is coupled to the second IRQSM 62, and the DUA flag number bus 230 is coupled to the DMASM 70.

In operation, and referring now also to FIG. 3, there is shown a series of 10 16-bit data registers of the first RQSM 30. A software flag register 301 is arranged to store the flag signal outputs received from the first series of 1/0 submodules. In this way the first series of submodules may constitute up to 16 1/0 submodules. A DMA flag register 302 is also arranged to store the flag signal output received from the first series of 1/0 submodules. The same flag signal output from the series of 1/0 submodules is sent contemporary to the Software Flag Register 301 and to the DMA Flag Register 302.

Different interrupt levels of the main and 1/0 processors of the system and the DMA function are handled by pairs of registers. A first level of interrupt of the main processor is handled by a first enable register 303 and a first pending register 304. Similarly a first level of interrupt of the 1/0 processor is handled by a second enable register 305 and a second pending register 306. A second level of interrupt of the 1/0 processor is handled by a third enable register 307 and a third pending register 308. Finally a first level of DMA interrupt is handled by a fourth enable register 309 and a fourth pending register 310.

The number of registers are dependent upon the particular interrupt scheme of the system, and in particular, the number of interrupt levels provided for by the main processor, the 1/0 processor (if present) and the number of DMA levels. Two registers are provided for each interrupt/DMA level, in addition to the software and DMA flag registers 301 and 302 respectively.

The enable registers 303, 305, 307 and 309 are initialised by system software.

Bits set to '1' in the first, second and third enable registers 303, 305, and 307 indicate which submodules are enabled for creating interrupt requests.

Bits set to'l'in the fourth enable register 309 indicate which submodules are enabled for creating DMA requests.

The content of the enable registers is used by the RQSM 30 to determine whether to use the software flag register 301 or the DMA flag register 302.

A bit set to '1' in the fourth enable register 309 causes the corresponding bit in the DMA flag register 302 to be validated.. When a DMA level is enabled for a particular bit, an active flag signal output of the corresponding submodule will be stored in the DMA flag register 302, and if no DMA level is enabled, the software flag register 301 is used.

The software initialisation will decide via the Software Enable Registers 303, 305, 307 or the DMA Enable Register 309 if the selected submodules will generate an Interrupt Request or a DMA request. The initialisation software can also allow a submodule to generate both interrupt request and DMA request.

In this way the only parts of the design of the module 10 which are dependent upon the interrupt scheme of the system are the first and second RQSMs 30 and 40. Therefore if a designer wishes to adapt the module 10 for use with a system having a different main processor, only the RQSMs need to be adapted. Hence design flexibility is greatly improved.

It will be appreciated that alternative embodiments to the one described above are possible. For example, the number of interrupt request levels and the number of DM-A request levels used above are exemplary only, and other numbers of levels are also envisaged.

Furthermore, the provision of an 110 processor in the system is not mandatory and is described above only by way of an example. Finally, the number of RQSMs required by a module are determined by the number of submodule interrupt sources and by the addressing scheme. If 32-bit addressing is used, then each RQSM can handle up to 32 interrupt sources.

Claims

Claims

An interrupt arrangement for a module of a microprocessor system, the system having an interrupt scheme, the arrangement comprising: a plurality of submodules, each submodule having an interrupt source and each submodule arranged to provide an interrupt signal indicating the state of the interrupt source; a submodule request controller, coupled to receive the interrupt signals from the plurality of submodules and having a set of interrupt, registers which are arranged to contain interrupt attributes for each interrupt source of the plurality of submodules; and, an interrupt controller coupled to the submodule request controller and arranged to provide an interface between the system and the submodule request controller; wherein the interrupt attributes are arranged in dependence upon the interrupt scheme of the system such that interrupts arising from the interrupt sources are adapted to the system.
2. The interrupt arrangement of claim I wherein the interrupt controller comprises a main processor portion arranged to provide an interface with a main processor of the system, and a peripheral processor portion, arranged to provide an interface with a peripheral processor of the system.
3. The interrupt arrangement of claim 2 wherein the set of interrupt registers include main processor registers arranged to contain interrupt attributes of the main processor of the system, and peripheral processor registers arranged to contain interrupt attributes of the peripheral processor of the system.
4. The interrupt arrangement of claim 2 or claim 3 wherein the peripheral processor is an input/output (1/0) processor arranged to control the activities of a 1/0 bus of the system.
5. The interrupt arrangement of any preceding claim wherein the interrupt controller includes a direct memory access control portion arranged to provide a direct memory access interface with the system.
6. The interrupt arrangement of claim 5 wherein the set of interrupt registers include direct memory access registers arranged to contain interrupt attributes relating to direct memory access. 5
7. The interrupt arrangement of any preceding claim wherein the submodules, submodule request controller and interrupt controller are coupled together via a request bus of the module.
8. An interrupt arrangement substantially as hereinbefore described and with reference to the drawings.