GB2339287A - Correcting phase differences in a transducer circuit - Google Patents

Description

2339287 TRANSDUCER CIRCUIT The present invention relates to a transducer

circuit and a control circuit for use with the transducer circuit.

The transducer circuit has particular, but not exclusive, relevance to metrological instruments for measuring surface characteristics such as form, for example roundness, and roughness or surface texture.

WO 95/08096 describes such a metrological instrument, the Form Talysurf Plus manufactured by Taylor Hobson Limited, Leicester, England, UK. In this instrument, a stylus is pivotally mounted on an arm and the tip of the stylus is traversed across the surface of a workpiece. A transducer outputs a signal in accordance with the movement of the tip of the stylus in response to a surface characteristic, in the case of the Form Talysurf Plus the surface roughness or texture, of the workpiece.

The transducer of the Form Talysurf Plus comprises an inductance which has a centre tap connected to earth and a moveable core which moves in response to movements of the stylus tip. A bridge circuit is formed by connecting each end of the inductance to a respective end of a variable potentiometer whose wiper is connected to earth.

An oscillator, whose centre tap is grounded, supplies an 2 An oscillator, whose centre tap is grounded, supplies an oscillating voltage via matched resistors to the bridge circuit. The voltages at the ends of the inductance are sampled and processed through a summing circuit and a difference circuit. When the bridge circuit is balanced, the output of the summing circuit is a null signal as the voltages at opposite ends of the inductance have identical amplitudes but are 180' out of phase. If the bridge circuit is not balanced, for example due to movement of the core in response to movement of the stylus, the summing circuit will provide a non-null output signal. The output of the difference circuit is an oscillating signal with a substantially constant amplitude.

A digital output representative of the position of the stylus is obtained by:

i) supplying the output of the difference circuit to a multiplying digital -to-analogue converter (DAC) which multiplies the output of the difference circuit by a digital value; ii) comparing the output of the DAC with the output of the summing circuit; and iii) adjusting the value by which the DAC multiples the 3 output of the difference circuit so that the output of the DAC has an identical amplitude and is 180' out of phase with the output of the summing circuit.

The digital value by which the multiplying digital-toanalogue converter multiplies the output of the difference circuit provides a digital signal representative of the position of the stylus.

WO 95/08096 discloses how to adjust the circuit described above to reduce a number of errors which may be present in the measurement. One particular adjustment involves incorporating a variable phase shift network between the difference circuit and the multiplying DAC. This variable phase shift network can be adjusted to allow for phase shift between the outputs of the summing circuit and the difference circuit.

The variable phase shift network is automatically 20 controlled by monitoring a signal obtained by summing the output of the summing circuit and the output of the multiplying DAC. If the outputs of the summing circuit and the difference circuit are out of phase there will be a residual ripple voltage when these two signals are added together. The phase shift circuit is automatically adjusted to minimise this ripple voltage thereby ensuring that the signals are substantially in phase.

4 Although the instrument disclosed in WO 95/08096 provides accurate measurement of surface characteristics, the instrument is also expensive.

The present invention is concerned with developing alternative instruments to that disclosed in WO 95/08096. In particular, the present invention aims to provide an instrument which can be manufactured at a significantly reduced cost compared to the cost of the instrument disclosed in WO 95/08096.

In one aspect, the present invention provides a metrological instrument, for example an instrument for measuring surface form and/or roughness, or a transducer circuit suitable for use in such an instrument, wherein a position transducer such as, for example, an LVDT (Linear Variable Differential Transducer) is provided with a digitally generated excitation signal.

In one aspect, the present invention provides a metrological instrument, for example an instrument for measuring surface form and/or roughness, or a transducer circuit suitable for use in such an instrument, wherein in order to ensure that the output of a position transducer, for example an LVDT (Linear Variable Differential Transducer), is sampled at a known point, for example at a known phase of the output signal, the output signal is compared with a number of samples corresponding to an excitation signal (which may be a digitally generated signal) supplied to the position transducer but each of different phase from one another to determine which of the samples is closest in phase to the output signal of the position transducer.

In one aspect, the present invention provides a metrological instrument, for example an instrument for measuring surface form and/or roughness, or a transducer circuit suitable for use in such an instrument, wherein in order to identify a peak in the output of a position transducer, for example an LVDT (Linear Variable Differential Transducer), a number, generally two, of points of the output signal having a known phase relationship with one another are sampled, by, for example, sampling the output signal when an excitation signal (which may be a digitally generated signal) supplied to the position transducer has first and second given phases.

In an embodiment, the present invention provides a transducer circuit, comprising: a sub-circuit for generating a periodically varying signal for supply to a position-to-electrical transducer, the position-toelectrical transducer being arranged to produce an analogue electrical signal dependent upon the position 6 of a probe; an analogue-to-digital converter for converting the analogue electrical signal to a digital electrical signal; and a processor for analysing signals received from the analogue-to-digital converter and the sub-circuit to provide a measurement signal for providing a measurement of the position of the probe, wherein the sub-circuit includes digital components arranged to generate the periodically varying signal in accordance with a clock signal.

An advantage obtained by using a digitally based system to generate the periodically varying signal is that the properties of the periodically varying signal generated are well-defined and predictable and so it is not necessary to continuously monitor the properties of the periodically varying signal.

The replacement of the analogue oscillator of WO 95/08096 with a digitally based system can also lead to a reduction of the total number of components required in the transducer circuit as an increased amount of signal processing can be carried out in the processor due to the well-defined signal produced. There is also a reduction of noise due to the removal of analogue components which have an inherent noise and are susceptible to electrical pick-up.

7 In an embodiment, the present invention provides a transducer circuit, comprising: a clock producing a train of clock signals at a constant frequency; a sub-circuit for providing an analogue signal, whose voltage varies periodically, to a transducer for producing an electrical signal dependent on the position of a probe; an analogueto-digital converter for converting the electrical signal into a digital signal; and a processor for analysing signals received from the sub-circuit and the analogueto-digital converter to provide a measurement signal providing a measurement of the position of the probe, wherein the processor is adapted to correct for any phase shift between the analogue signal and the electrical signal in accordance with information received from the sub-circuit and the analogue-to-digital converter.

Preferably, the clock is a crystal oscillator as a crystal oscillator provides a signal which is substantially immune to frequency drift. Furthermore, a crystal oscillator does not require a long warm-up period.

Preferably the crystal oscillator is an integral part of the processor thereby reducing the total number of components in the circuit.

Conveniently, the amplitude of the analogue signal varies 8 sinusoidally.

In an embodiment of the present invention, the transducer circuit is provided in a metrological instrument for measuring a characteristic of a surface of a workpiece, wherein the probe is a stylus and the position-toelectrical transducer is an inductive transducer having a coil and a core for the coil, the inductive transducer being arranged so that movement of the stylus in response to the characteristic of the surface causes relative movement between the coil and the core, and the instrument further comprises an arm for holding the stylus so that the stylus may be traversed relative to the surface of the workpiece.

A transducer circuit embodying the present invention is particularly well suited to metrological instruments of the type described above as high resolution can be obtained over a large measurement range.

Exemplary embodiments of the present invention will now be described with reference to the accompanying drawings in which:

Figure 1 is a very schematic diagram of a metrological instrument suitable for incorporating a transducer circuit according to the present invention; 9 Figure 2 is a very schematic diagram of control circuitry of the metrological instrument shown in Figure 1.

Figure 3 is an overall schematic diagram of z-position 5 transducer circuitry according to the present invention for the instrument shown in Figures 1 and 2; Figure 4 is a block diagram of a first embodiment of a transducer circuit according to the present invention; Figure 5 is a block diagram showing a number of subroutines stored in a processor of a transducer circuit according to the first embodiment; Figure 6 is a graphical representation of an output of an EPROM of a transducer circuit according to the first embodiment of the present invention; Figures 7A and 7B show a flow chart indicating a routine used in the first embodiment of the present invention to identify a sample overlay whose phase is closest to a signal input to an analogue-to-digital converter of the transducer circuit; Figure 8 is a flow chart indicating a routine used in the first embodiment of the present invention to remove any DC offset in a signal input into the analogue-to-digital converter:

Figure 9 is a block diagram in accordance with a third embodiment of a transducer circuit according to the 5 present invention; Figure 10 is a block diagram in accordance with a fourth embodiment of a transducer circuit according to the present invention; Figure 11 is a graph showing the amplitude of a signal input to an analogue-to-digital converter of an embodiments of the present invention against the relative displacement of the core of the inductive transducer; Figure 12 is a schematic diagram illustrating an alternative variable inductive transducer.

For exemplary purposes only, the present invention will be described in the context of a metrological instrument for measuring the surface roughness or texture of a surface 2 of a workpiece 4, as shown very schematically in Figure 1.

The metrological instrument comprises a base 6 which supports the workpiece 4. A vertical column 8 is secured to the base 6 and supports a first carriage 10 which can 11 be moved up and down the vertical column 8 to position the stylus 18 on the workpiece 4.

A horizontal datum bar 12 is mounted on the first carriage 10. A second carriage 14 is mounted for horizontal movement along the datum bar 12. A stylus arm 16 carrying a stylus 18 is pivotally mounted on the second carriage 14.

In operation, the second carriage 14 is moved along the datum bar 12 in the direction marked x in figure 1, thus traversing the stylus 18 along the surface 2 of the workpiece 4. The movement of the stylus 18 in the direction marked z in figure 1 in response to the surface 2 causes a respective relative movement between a core and a coil of a linear variable differential transducer (LVDT) (not shown in Figure 1) thereby enablingmeasurement of the movement of the stylus 18 as it follows the surface 2 being measured. 20 As the stylus 18 may have a small range of movement for which an accurate signal can be produced, the first carriage 10 may be moved up and down the vertical column 8 during operation to increase the measurement range of the instrument.

A signal from the LVDT representative of the surface 2 12 is supplied to an interface module 19 where it is processed to produce measurement data for the surface 2. The interface module 19 is connected to a computer 20 which can access and analyse the measurement data. The computer has a facility for receiving a disc 22 which may either contain software for controlling the computer or may provide a memory for storing measurement data., A very schematic diagram of the control circuitry of the metrological instrument shown in Figure 1 is illustrated in Figure 2. Typically, only the core and the coil of the LVDT used in the z-position transducer circuit will be housed in the second carriage 14, all the other measurement circuitry being located in the interface module 19.

A master controller 1000, in response to an instruction by a user to initiate a measurement, controls a motor (not shown) to move the second carriage 14 along the datum bar 12 in the x-direction. Additionally the master controller 1000 may activate a second motor (not shown) to move the first carriage 10 along the vertical column 8 in the z-direction to locate the stylus 18 on the surface 2 or to increase the measurement range.

The x-position transducer 1002 is provided to determine the position of the second carriage 14 along the datum 13 bar 12. The x-position transducer may be, for example, an optical interferometer with a diffraction grating mounted on one of the second carriage 14 and the datum bar 12 and the interferometer system mounted on the other of the second carriage 14 and the datum bar 12 (similar to that described in US-A-5517307 but using a planar grating as used in, for example, an optical transducer such as that described in US-A-5063291).

In use, when the second carriage 14 reaches selected positions along the datum bar 12, the x-position transduce-- sends a signal V,,, to a zposition transducer 1004 initiating a measurement of the displacement in the z-direction of the stylus 18. Additionally, the x- position transducer sends a signal Vx2 to the master controller 1000 informing the master controller 1000 that a new measurement by the z- position transducer had been initiated. The master controller 1000 subsequently receives a signal V. from the z-position transducer 1004 providing a measurement of the displacement of the stylus 18 in the z- direction. The master controller 1000 then stores in the memory 1006 the displacement of the stylus 18 in the z-direction for the associated x position.

Figure 3 illustrates the main elements of the z-position transducer 1004. A carrier wave generator 24 supplies 14 an oscillating voltage signal Vosc to a gauge circuit 26.

Included in the gauge circuit 26 is the LVDT (not shown) whose output varies in response to the movement of the stylus 18.

A processor 28 outputs a signal V, to the carrier wave generator 24 which provides timing information for the production of the oscillating voltage signal Vosc. The carrier wave generator 24 provides a signal V2 to the processor 28 providing phase information about the oscillating voltage signal Vosc.

The gauge circuit 26 outputs a digital measurement signal VD representative of the position of the stylus in the z direction to the processor 28 in response to a trigger signal VT from the processor 28. The trigger signal VT is generated by the processor 28 in response to the signal Vx, from the x-position transducer 1002 initiating a measurement. The exact timing of the trigger signal VT is dependent upon the signal V2 providing phase information about the oscillating voltage signal Vosc as will be described in detail hereafter. on the basis of this, the processor 28 outputs a signal V, providing a measurement of the position of the stylus 18 in the z direction.

With reference to Figure 4, there will now be described in greater detail a first embodiment of the transducer circuit. The carrier wave generator 24 and gauge circuit 26 of Figure 3 have been indicated by dashed blocks.

In the first embodiment, a conventional counter 30 provides an 8-bit digital number. The 8-bit number is increased by one each time a clock signal Clk is received from the processor 28 so that the output of the counter 30 cycles from 0 to 255. In this embodiment, the clock signal has a frequency of 2.5MHz and is derived from a crystal oscillator (not shown) in the processor 28.

The 8-bit digital number is input to an EPROM 34 as the address of a corresponding memory location in the EPROM 34 containing another 8-bit digital number. The EPROM 34 stores 8-bit digital numbers such that, when the memory locations are addressed in ascending order by the output of the counter 30, a train of digital values representing a digitized sine wave signal SW is output from the EPROM 34.

The digitized sine wave signal SW is input to a digitalto-analogue converter (DAC) 36 which converts the digital signal SW into a f irst analogue signal V,j having a voltage which oscillates in phase with the digitized sine wave signal SW. The DAC 36 also outputs a second 16 analogue signal V.2 which has a voltage having the same peak value as the first analogue signal V., but which oscillates 1801 out of phase with the digitized sine wave signal SW. In this embodiment the DAC 36 is a conventional DAC-08 8-bit high-speed D/A converter available from Analog Devices.

The first and second analogue signals V,1 and V,2 are supplied to respective buffer amplifiers 38, 40 of the gauge circuit 26. The buffer amplifiers 38, 40 are required in this embodiment to drive the gauge circuit with sufficient power and at the correct voltage level.

In this example, the variable impedance transducer in the gauge circuit consists of an inductor having two E-shaped cores 42, 44 (that is cores having a backbone with three equally spaced fingers projecting therefrom) and an I shaped core 46 (that is a core having only a backbone).

The I-shaped core 46 is connected to the stylus arm 16 in conventional manner (for example as shown in US-A5517307) so that movement of the stylus 18 causes a corresponding movement of the I-shaped core 46. A coil 43, 45 is wound around the central finger of each Eshaped core 42, 44. One end of each coil 43, 45 is connected to ground while the other end is connected to a respective end of an adjustable potentiometer 48. The 17 wiper of the adjustable potentiometer 48 is connected to ground (earth).

In this way a bridge circuit BC is formed by the coils 43, 45 around the two E-shaped cores 42,44 and the potentiometer 48.

The first and second analogue signals V,1, V,2 are supplied to respective ends 48a and 48b of the potentiometer 48 via respective ones of a pair of matched resistors 50, 52.

The crystal oscillator used to generate the clock signal is advantageous as it provides a clock signal with substantially no frequency drift and hence frequency drift in the analogue signals V.,, V.2 supplied to either end of the potentiometer 48, which can be a problem in conventional oscillators, is substantially eliminated.

In a balanced condition, the voltages at the ends 48a and 48b of the potentiometer 48 will have identical peak values and be 1801 out of phase with each other.

However, if the bridge circuit BC is not balanced, for example due to movement of the I-shaped core 46 caused by movement of the stylus 18, the amplitudes of the voltages at either end 48a, 48b of the potentiometer 48 will no longer be identical.

18 The voltages at either end 48a, 48b of the potentiometer 48 are supplied to a conventional sum circuit 54, which produces a signal obtained by adding the two voltages together, and a conventional difference circuit 56, which produces a signal obtained by subtracting the two voltages. The sum circuit 54 includes a variable component which can be adjusted to vary the gain of the sum circuit 54. The sum circuit 54 and the difference circuit 56 are identical to those disclosed in Figure 12 of WO 95/08096, the whole contents of which are hereby incorporated by reference.

When the bridge circuit BC is balanced, as the signals at the ends 48a and 48b of the bridge circuit DC will be of equal amplitude but 180' out of phase, the output Vsig of the sum circuit 54 will be a null signal. However, if the bridge circuit is not balanced the output Vsig of the sum circuit 54 will be an oscillating signal whose frequency is identical to the frequency of the first and second analogue signals V.,, V.2 and whose amplitude will vary depending on the position of the I-shaped core 46 in relation to the coils 43, 45.

The output of the difference circuit 56 will be a signal 25 Va,,f with a substantially constant amplitude independent of the position of the Ishaped core 46 over the normal, 19 linear range of the gauge.

As explained in WO 95/08096, slight differences in the resistances of the two coils 43, 45 will introduce a quadrature component into the voltages at the ends of the potentiometer 48. The position of the wiper of the variable potentiometer 48 can be adjusted to reduce this quadrature component. In this embodiment the position of the wiper is manually set prior to use.

A switch 58 feeds either the output Vsi, of the sum circuit 54 or the output VRef of the reference circuit 56 to an analogue-to-digital converter (ADC) 60. In this embodiment the ADC 60 is a LTC 1605 16-Bit, 100 ksps sampling ADC supplied by Linear Technology of Milpitas, California, USA. The ADC 60 tracks the signal and, in this embodiment, produces a 16-bit digital signal to be input into the processor 28.

The output of the counter 30 is also supplied to a sample decoder 64. In this embodiment, the sample decoder 64 stores sample overlays each of which consists of timing information for a respective different one of sixty-four sine waves having the same frequency as the sine wave stored in the EPROM 34 but successively phase-shifted by 1.40. In this embodiment the thirty-second sample overlay corresponds to a sine wave having the same phase as the sine wave generated by the EPROM 34 so that sample overlays corresponding to sine waves with phase shifts in the range of -450 to +450 compared to the phase of the digitized sine wave signal SW are stored in the sample decoder 64. The sample decoder 64 is made in this embodiment using EPROM.

The processor 28 is connected to the sample decoder 64 so that the processor 28 can select one of the stored sample overlays. The timing information of the sample overlays stored in the sample decoder 64 enables the sample decoder 64 to send signals to the processor 28 indicating when the phase of the selected sample overlay passes through 450, 900, 1350 and 2700.

The processor 28 processes information from the ADC 60 and the sample decoder 64. In this embodiment the processor 28 is an Intel MCS251 Processor. The processor 28 is connected to the switch 58 enabling the processor 28 to switch the input to the ADC 60 between Vsig and VR,f.

The processor 28 is also connected to the ADC 60 enabling the processor 28 to trigger the ADC 60 to sample the input and output a 16 bit digital value representative of the sampled input.

For each x-direction position indicated by a signal Vxj from the x-position transducer 1002, the processor 28 21 produces a signal Vz, dependent on the signals received from the ADC 60 and the sample decoder 64, which provides a measurement of the corresponding displacement in the z-direction of the stylus 18. This signal can be output as either parallel or series data. An advantageous feature of this embodiment is that the transducer circuit can be made compact as analogue components employed in generating an oscillating voltage are bulkier than the corresponding digital components.

As shown in Figure 5, a number of procedures are stored in the processor 28. These procedures include an "identify sample overlay" sub-routine 70, a "calculate DC offset" sub-routine 72, a "Check Amplitude of VR.f" sub-routine 73 and a "measure surface" sub-routine 74. The "identify sample overlay" sub-routine identifies the sample overlay stored in the sample decoder 64 corresponding to a sine wave whose phase most closely matches the phase of the signal input to the ADC 60. The "calculate DC offset" sub-routine calculates the DC offset of the signal input to the ADC 60. The "Check Amplitude of VR,f" sub-routine 73 checks that the amplitude of the output of the dif f erence circuit VR,,f has not drifted, and the "measure surface" sub-routine 74 is used when measuring the characteristic of the surface of the workpiece.

22 Figure 6 shows an example of the sinusoidal output of the DAC 36. Since, in this embodiment, the counter 30 has 256 separate values and the clock is driven at a frequency of 2.5MHz, the frequency at which the output varies is 9.76KHz and the value of the output of the EPROM 34 changes every 1.4'. In the highlighted portion 78, the digital nature of the output from the EPROM 34 has been magnified.

The signal input to the ADC 60 will also have a sinusoidal variation of magnitude. A problem which needs to be addressed is how to ensure that the output of the ADC 60 is sampled at a point whose phase is known so that each measurement is made at the same phase of the output of the ADC 60 because, as has been previously mentioned, the output of the DAC 36 is not necessarily in phase with the signal input to the ADC 60 and hence the sampling of the ADC 60 cannot be triggered straight from the output of the EPROM 34.

The solution proposed in the present embodiment is to identify ',-,he sample overlay stored in the sample decoder 64 whose phase most closely matches the phase of the signal input to the ADC 60, and to use this sample overlay to trigger the sampling of the ADC 60. In the present embodiment, the identification of the correct sample overlay is achieved by employing the feature of 23 a sinusoidally varying signal that the magnitude of the signal when the phase is at 45', Pl in Figure 6, is equal to the magnitude of the signal when the phase is at 135, P2 in Figure 6.

Figures 7A and 7B shows the steps of the "identify sample overlay" subroutine used to identify the correct sample overlay.

As step Sl the sample N whose phase is identical to the phase of the output of the EPROM 34 is selected by the processor 28. In this embodiment it is the thirty second sample overlay whose phase matches the output of the EPROM 34. A number S stored in the processor 28 is set to be equal to N.

Next, in step S3, the value X. is calculated, where Xs is given by the value obtained by sampling the output of the ADC 60 when the sample decoder 64 indicates that the phase of the sample overlay S passes through 45' minus the value obtained by sampling the output of the ADC 60 when the sample decoder 64 sends a signal indicating that the phase of the sample overlay S passes through 1351.

The processor 28 checks, in step S5, if Xs is equal to zero. If Xs is equal to zero then the phase of the 24 selected sample S stored in the sample decoder 64 matches the phase of the signal input into the ADC 60 and the sub-routine is terminated at step S7. If Xs is not equal to zero, then the sub-routine proceeds to step S9.

In step S9 the processor checks if Xs is greater than zero. If Xs is greater than zero then the phase of the sample S stored in the sampledecoder 64 leads the phase of the signal input into the ADC 60. In this case, in step S11, the processor 28 selects the sample N-1, whose phase lags that of the sample N by 1. 40. Also in step Sll the processor 28 sets the value of a number T stored in the processor 28 equal to N-1.

If the value of X, is less than zero then the phase of the sample overlay N lags the phase of the signal input to the ADC 60 and the processor 28, in step S13, selects the sample overlay N+1 whose phase leads that of the sample overlay N by 1.4'. In step S13 the processor 32 sets the value of T equal to N+1.

In step S15 the processor calculates the value of XT. At this point, the processor 28 has stored a number T indicating the number of the sample overlay being currently tested and the value XT which is a measure for the sample overlay T of the value obtained by subtracting the value sampled from the ADC 60 when the phase of the sample overlay T passes through 135' from the value sampled from the ADC 60 when the phase of the sample overlay T passes through 45'. The processor 28 also stores a number S indicating the number of the sample overlay which had been tested immediately before the' current sample overlay T, and the value Xs for sample overlay S.

The processor 28 checks, in step S17, if the value XT is equal to zero. If the value of XT is equal to zero then the phase of the selected sample overlay T matches the phase of the signal input into the ADC 60 and the subroutine is terminated in step S19. If the value of XT is not equal to zero then the sub-routine proceeds to step S21.

In step S21 the processor 28 investigates whether the modulus of Xs is less than the modulus of XT' If the modulus of Xs is less than the modulus of XT then the sample overlay S will be the sample overlay whose phase most closely matches that of the signal input to the ADC 60. In this case, in step S23 the sample overlay S is selected and, in step S25, the initialisation process is ended.

26 If the modulus of Xs is greater than the modulus of XT then the processor 28 investigates in step S27 if XT is greater than zero. If XT is greater than zero then, in step S29, sample T-1 is selected and S is set to be equal to the value of T and subsequently the value of T is set equal to T-1. The process then returns to step S15.

If the value of XT is less than zero then, in step S31, the processor 28 selects sample T+1 and sets the value of S equal to the value of T and subsequently increases the value of T by 1. The process then returns to step S15 and continues until the sample overlay stored in the sample decoder 64 whose phase most closely matches that of the signal input to the ADC 60 has been identified.

A DC component to the signal input to the ADC 60 will also cause inaccuracy in the measurement value. As shown in Figure 8, the steps of the "calculate DC offset" sub routine are as follows.

In step S41 the processor 28 samples the value, V90, of the output of the ADC 60 when the sample decoder 64 indicates that the phase of the selected sample overlay passes through 900. In step S43 the processor 28 samples the value, V2701 of the ADC 60 when the sample decoder 64 indicates that the phase of the selected sample overlay 27 passes through 270'. The difference A between V90 and V270 is then calculated in step S45 and the DC offset value is obtained in step S47 by subtracting half the value of A f rom V90.

The "calculate DC offset" sub-routine is run periodically to check if there have been any fluctuations in the DC level of the signal input to the ADC 60.

The value of the phase shift between the output of the DAC 36 and the signal input to the ADC 60 will vary significantly if the position of the movable I-shaped core 46 in relation to the E-shaped cores 42, 44 moves outside a certain range. Therefore, in this embodiment, the routine for identifying the sample overlay stored in the sample decoder 64 having the closest phase relationship with the input to the ADC 60 is run whenever the displacement of the movable I-shaped core 46 passes through pre-determined points where the change in phase shift becomes significant.

The reference value output from the difference circuit 56 is also monitored, using the "Check Amplitude of VR,,f" sub-routine 73, to check if there have been any fluctuations in the amplitude of the output of the DAC 36.

28 Accordingly, the steps of the "measure surface" subroutine 74 include measuring the characteristic of the surface by sampling the ADC 60 when the sample decoder 64 indicates that the phase of the selected sample 5 overlay passes through 900 and:

i) periodically checking the reference value outputfrom the difference circuit 56; ii) periodically running the "calculate DC offset" subroutine 72; and iii) running the "identify sample overlay" sub-routine 70 whenever the I- shaped core passes through one of the predetermined points.

In this embodiment the point at which the ADC 60 is sampled is when the phase of the sinusoidal signal is equal to 90', P90 in Figure 6, and hence the sinusoidal signal is at its peak.

There will now be described a second embodiment of the present invention. A problem which may occur with the transducer circuit of the first embodiment of the present invention is that noise on the signal input to the ADC 60 due to electrical pick-up and inherent component noise may lead to an incorrect sample overlay stored in the 29 sample decoder 64 being identified and may also lead to errors in the measurement signal.

The solution proposed in the present embodiment is to sample the signal at the same point in a number of cycles and then calculate the total value obtained by adding the sampled values. This is possible when the rate of change of the characteristic of the surface being measured is slow compared with the frequency of the oscillator which is generally the case where surface roughness or texture is being measured.

The transducer circuit according to the second embodiment of the present invention is substantially identical to that of the first embodiment with the exception that the processor 28, when sampling the ADC 60 when the sample decoder 64 indicates that the currently selected sample overlay passes through a given phase, samples the ADC 60 on a plurality of cycles of the signal input to the ADC 60 and adds together the values of the samples. The value obtained by adding the samples is directly converted by the processor 28 into a measurement of the z-position of the stylus using an appropriate conversion look-up table.

The multiple measurement technique described above may be used any time the processor 28 samples a value output from the ADC 60, for example during surface measurement, the "identify sample overlay" sub-routine and the "calculate DC offset" sub-routine.

A third embodiment of the present invention will now be described with reference to Figure 9. In Figure 9 components that are identical to the corresponding components in Figure 4 have been numbered with the same numerals. The main difference is in the replacement of the sample decoder 64 by an EPROM 80 which stores only phase information for the digital sine wave stored in the EPROM 34 and outputs to the processor a signal when the output of the EPROM 34 passes through 450, 900, 1350 and 2700.

In this embodiment, rather than finding a sample overlay whose phase matches the phase of the signal input to the ADC 60, two points of the signal input to the ADC 60 having a known phase relationship are sampled when carrying out measurements. In this embodiment, the two points are when the phase of the digital sine wave output from the EPROM 34 passes through 451 and 1350, points Pl and P2 in Figure 6.

Therefore, the "identify sample overlay" sub-routine 70 is not required in this embodiment, but rather the,,measure surface" sub-routine 74 is modified as described 31 below.

Assuming that there is a phase shift of x between the output of the EPROM 34 and the input to the ADC 60, then:

VP45 = VPk sin(45+x) (1) where VP45 is the value sampled from the ADC 60 when the EPROM 80 indicates that the phase of the output from the EPROM 34 passes through 451, and Vk is the peak value of the signal input to the ADC 60. By expanding out the sine term, this is equivalent to:

VP45 Vpk sinx + COSX) (2) Similarly:

VP135 VPk sin(135+x) (3) where VP135 is the value sampled from the ADC 60 when the EPROM 80 indicates that the phase of the output of the EPROM 34 passes through 1350, the sine term being expandable to give:

V VP135 Pk (- sinx+ co (4) From equations 2 and 4 the following relations can be 32 derived:

sinx VP45-VP135 (5) V7VPk CoSX VP45+VP135 (6) V7Vpk By squaring and adding equation 5 and equation 6, the following relationship is obtained:

V2 2 P45 + VP135 (7) 2 Vk From equation 7, the following expression for Vk can be derived:

VP2 2 (8) Vpk 45+VP135 As the peak value is calculated by taking the square root of a number, the sign of the peak value can not be derived from equation 8. To overcome this, the values of VP45 and VP135 can be taken into account. If the values Of VP45 and VP13.5 are higher than the DC of f set level then the sign of Vpk is positive while if the signs Of VP45 and 33 VP135 are lower than the DC of f set level then the sign of VP, is negative. In practice, the phase shift between the output of the DAC 36 and the signal input to the ADC 60 does not vary sufficiently for VP45 and VP13-5 to have 5 amplitudes on opposite sides of the DC offset level.

To calculate the any DC offset level in the signal input to the ADC 60, the same routine as used in embodiment 1 and shown in Figure 7 may be employed with the phase information stored in the EPROM 80 being used instead of the phase information of the selected sample overlay.

Therefore, the "measure surface" sub-routine used in the third embodiment includes sampling the ADC 60 when the EPROM 80 indicates that the output of the EPROM 34 corresponds to a phase of 450, sampling the ADC 60 when the output of the EPROM 80 indicates that the output of the EPROM 34 corresponds to a phase of 135' and calculating, based on these values, the correct value of Vpy.

The third embodiment has the advantage that the EPROM 80 requires less memory and is therefore cheaper than the sample decoder 64 of the first embodiment. However, compared with the first embodiment it has the disadvantage that when taking measurements the signal 34 input to the ADC 60 must be sampled at two points with different phase relationships and the processor 28 must carry out additional processing compared with the first embodiment. This may reduce the number of transducer 5 circuits which can be controlled by a single processor 28 having a given processing power.

It will be appreciated that, as in the second embodiment, the points may be sampled a number of times and arranged to reduce the effects of noise.

A fourth embodiment of the present invention will now be described with reference to Figure 10. In Figure 10, components which are identical to corresponding components in the first embodiment as shown in Figure 4 are identified by the same numerals as in Figure 4.

In the fourth embodiment of the present invention the counter 30, EPROM 34, and sample decoder 64 of the first embodiment have all been incorporated in an application specific integrated circuit (ASIC) 90, thereby reducing the number of components in the circuit. The ASIC 90 performs exactly the same function as the components of the first embodiment which the ASIC 90 replaces.

Similarly, the ASIC 90 could perform the functions of the counter 30, EPROM 34, and EPROM 80 of the third embodiment of the present invention.

The use of the ASIC 90 to replace a number of components has the advantage of reducing the number of components and thereby enabling the circuit to be made smaller and cheaper. Additionally by using the ASIC 90 to replace a number of components has the advantage of reducing noise as there are less digital circuits. The ASIC 90 also allows for easy modification.

As indicated in Figure 11, the transducer used in the previous embodiments is conventionally used within a range A in which there is a linear relationship between the voltage input to the ADC 60 and the displacement of the I-shaped core 46 from the position in which the bridge circuit is balanced. The working range for the displacement of the I-shaped core 46 can be extended to a range B including additional regions B1 and B2 where there is a non-linear response in the signal input to the ADC 60 by carrying out a calibration procedure. However, when the range of measurement is extended there will be a corresponding reduction in measurement resolution if the same number of values of the output from the ADC 60 must cover the extended range. Furthermore, in the range B the phase shift between the oscillating voltage sig nal Vosc and the input to the ADC 60 will vary significantly.

36 In a fifth embodiment of the present invention, the processor 32 also stores an "initialisation" or calibration sub-routine which is activated when either the metrological instrument is switched on or a manual command is received from a user and which enables, if desired, the transducer to be operated outside its normal linear range as described above. The transducer ci.rcuit of the fifth embodiment of the present invention is essentially identical to that of the first embodiment of the present invention with the addition of the "initialisation" sub- routine.

In the "initialisation" sub-routine the position of the I-shaped core 46 is moved step by step throughout an extended range using a reference sample having a known well-defined shape to its surface 2. At each step, the processor runs the "identify sample overlay" sub-routine 70, the "calculate DC offset" sub-routine 72, the "Check Amplitude of VR,f" sub-routine 73, and obtains a measurement corresponding to the position of the I-shaped core using the "measure surface" sub-routine 74 at a number of known z displacements positions. This information may be stored as a look-up table in the memory 1006 so that the master controller 1000 can determine what z displacement is represented by a given output signal from the z-position transducer circuit.

37 In this embodiment two modes of operation are available to the user, a first mode in which the movement of the I-shaped core 46 is limited to the substantially linear range and a second mode in which the movement of the I- shaped core 46 can be over the entire extended range but the measurement is produced with a reduced resolution.

Because the phase shift between the oscillating voltage signal Vosc and the input to the ADC 60 will vary more rapidly in the extended range B, the transducer circuit according to the present invention is particularly advantageous since the phase shift between the oscillating voltage signal v0sc and the input to the ADC 60 can be constantly monitored so that, even in the extended range B, the input to the ADC 60 is always sampled at the same phase value.

A number of modifications can be made to the abovedescribed embodiments without departing from the inventive concept of the invention. Some of these modifications will now be described.

In all the previous embodiments the transducer has been an inductive transducer formed by an I-shaped core 46 and two E-shaped cores 42, 44 with wire coiled around the central projection of each of the E-shaped cores 42, 44. However, the present invention can be applied equally to 38 any other f orm of inductive transducer and also to other transducers such as capacitive transducers.

An example of an alternative variable inductive 5 transducer is shown in Figure 12. An I-shaped core 100 (that is a core having only a backbone) is connected to the stylus arm 16 such that it is aligned longitudinally along the stylus arm 16. The centre of the I-shaped core 100 is located directly adjacent the pivot point 102 of the stylus arm 16.

An E-shaped core 104 (that is a core having a backbone with three equally spaced fingers 106, 108, 110 projecting therefrom) is located opposite to the I-shaped core 100 with the projections facing one of the elongate surfaces of the I-shaped core 100. The central projection 106 is disposed opposite the pivot point 102 and coils 112, 114 are wrapped around respective ones of the two outer projections 108, 110. This variable inductive transducer has the advantages of low cost, as only one E-shaped core is required, and compactness. Although it is advantageous to locate the I-shaped core 100 symmetrically about the pivot point 16, since the stylus is then able to move the largest distance in the z-direction before the I-shaped core 100 makes contact with the E-shaped core 104, the I-shaped core 100 may also be mounted away from the pivot point.

39 Another common feature of all the previously described embodiments is that a switch 58 is used to select either the output of the sum circuit Vsig or the output of the difference circuit Va,f as the input to the ADC 60.

Alternatively, a second ADC could be added and the output of the sum circuit Vsis and the output of the difference circuit VR.f can be input to respective ones of the two ADCs. Alternatively as the amplitude of VR,, f should remain substantially constant, the output of the sum circuit Vsig can be fed directly into the ADC 60 and the difference circuit 56 and the switch 58 can be removed. In this case, a measurement proceeds on the assumption that the value of the amplitude Of VRet is a constant.

A further common feature of all the previously described embodiments is that the clock is incorporated in the processor 28. Alternatively, a separate clock could be used. The clock frequency may be varied to vary the frequency of the voltages output from the DAC 36.

The DAC 36 of the previously described embodiments converts an 8 bit number into two corresponding analogue signals, one with an amplitude equivalent to the 8 bit number and one with an amplitude equivalent to the negative of the 8 bit number. It will be appreciated that the inventive concept could equally well be applied to other word sizes for example 16 bit and 32 bit. Similarly, the output of the counter 30 can be of different word sizes. Also, clock frequencies other than 2.5MHz can be used. One of the advantages of the present invention is the ease in which the components can be upgraded as new and better components enter onto the market.

In the first embodiment, a counter 30 is used to output an 8-bit number, the value of which increments up by one each time a clock signal Clk is received from the processor 28. This 8-bit number is then used to trigger a change in the value of the digitised sine wave signal Sw. Therefore the value of the digitised sine wave signal SW changes approximately every 1.40. Further, the sample decoder 64 stores sample overlays consisting of timing information for a respective different one of 64 sine waves having the same frequency as the sine wave stored in the EPROM 34 but successfully phase shifted by 1.40. In this way, the information of 64 sine waves having phase shifts in the range of -451 to +45 compared to the phase of the digitised sine wave signal SW are stored in the sample decoder 64.

Alternatively, the counter 30 could produce a 10-bit number, the most significant eight bits of which are used to address the EPROM 34 similar to the first embodiment, 41 but all ten bits of which are used to address the sample decoder. Then, the sample decoder 64 may store sample overlays each of which consists of timing information for respective different one of 64 sine waves having the same frequency as the sine wave stored in the EPROM 34 but successively phase shifted by 0.350. In other words, it is not necessary that the phase difference between the sine waves stored in the sample decoder 64 be equal to the phase difference corresponding to the time for which the digitised sine wave signal SW is constant.

In addition, the digital sine wave may not be generated by the technique used in the previously described embodiments. For example, the digital sine wave may be generated directly by a processor using software.

The points chosen for sampling the ADC 60 in the previous embodiments are examples only. In the first embodiment, for identifying the correct sample overlay it is only necessary to pick two phases where the magnitude of the sine wave should be identical. If the DC offset is calculated before the correct sample overlay is identified, it is even possible to use two phases for which the modulus of the amplitude of the sine wave is identical.

In addition, the first embodiment can be adjusted so that 42 the sample decoder 64 need only notify the processor 28 when the phase of the selected sample overlay passes through three points. In this case, for example, the sample decoder 64 indicates when the selected sample overlay passes through 45' and 1351 to identify the correct sample overlay, when the selected sample overlay passes through 45' and 225 to calculate the DC offset, and when the sample overlay passes through 451 to measure the characteristic of the surface.

It will be further appreciated that it is not necessary to use a sine wave at all - The important feature is that the DAC 36 produces an analogue signal having a periodically varying voltage whose amplitude varies continuously in a well known manner.

As mentioned in the first embodiment, the processor 28 can be connected to a host computer via an optical fibre link. A number of other links may be used. For example, it may be preferable to use an infra-red link in some situations where it is not desirable to have a direct connection between the metrological instrument and the host computer.

In the first embodiment, a pattern recognition process is essentially being carried out. The processor 28 43 identifies the sample overlay corresponding to the sine wave (pattern) stored in the sample decoder 64 which most closely matches the input to the ADc 60. It will be recognised that such pattern recognition may be carried out entirely in software in the processor 28. In this case, there is no need for the sample decoder 64.

For the case where the rate of change of the characteristic of the surface being measured is small compared to the frequency of the signal Vosc output from the DAC 36, it is not necessary to compare points on the same cycle when comparing values sampled from the ADC 60 when the phase of the signal input to the ADC 60 passes through different values. For example, in the "identify sample overlay" 70 of the first embodiment, the value of the output of the ADC 60 when the sample decoder 64 indicates that the phase of the selected sample passes through 451 in one cycle can be compared with the value of the output of the ADC 60 when the sample decoder 64 indicates that the phase of the selected sample passes through 1351 for a neighbouring cycle.

The previously described embodiments have been related to a metrological instrument in which a stylus 18 is mounted on an arm 16. The arm 16 is pivotally attached to the second carriage 14 and movement of the stylus 18 44 causes a corresponding relative movement between a core 46 in a coil 42, 44. The previously described embodiments could equally be applied to a metrological instrument where the movement of the arm 16 is axial rather than pivotal.

In addition, the metrological instrument could be for measuring roundness like, for example, the Talyrond series manufactured by Taylor Hobson Limited, Leicester, 10 England, UK, rather than surface texture.

Alternatively, the transducer circuit of the present invention could be used in a pressure sensing system as described in, for example, US-A4140998.

Claims (36)

1. A control circuit f or use with a transducer f or converting the position of a probe into a corresponding electrical signal, comprising: an excitation signal generator for providing to the transducer an excitation signal whose voltage varies in a known manner with time; and a processor for analysing an electrical signal from the transducer to generate a measurement signal providing a measurement of the position of the probe; wherein the processor is adapted to correct for any phase shift between the excitation signal and the electrical signal.

2. A control circuit for use with a transducer for converting the position of a probe into a corresponding electrical signal, comprising: an excitation signal generator for providing to the transducer an excitation signal whose voltage varies in a known manner with time; and a processor for analysing an electrical signal from the transducer to generate a measurement signal providing a measurement of the position of the probe; 25 wherein the processor is adapted to calculate the phase of the electrical signal by comparing the electrical signal with information about a number of 46 patterns with varying phase properties and identifying the pattern whose phase most closely matches that of the electrical signal.

3. A transducer circuit for providing a measurement signal indicative of the displacement of a probe as it follows a measurement surface, comprising:

a transducer for providing in response to an excitation signal an output signal which changes with displacement of the probe as it follows the measurement surface; signal generating means for generating as the transducer excitation signal a signal having an amplitude which varies with time in a predetermined manner; processing means for determining the displacement of the probe as it traverses the measurement surface by comparing information relating to the excitation signal and derived from the signal generating means with the output signal of the transducer to determine whether there is any phase difference between the output signal from the transducer and the excitation signal and for determining the displacement of the probe from the output signal af ter compensating for any such phase difference.

4. A circuit according to claim 1 or 3, wherein the excitation signal generation is arranged to provide the excitation signal so that its amplitude varies 47 sinusoidally.

5. A circuit according to claims 1, 3 or 4, f urther comprising phase signal producing means for producing a phase signal indicating when the phase of the excitation signal passes through a first predetermined value.

6. A circuit according to claim 5, wherein the processor is arranged to sample the electrical signal in response to the phase signal provided by the phase signal producing means.

7. A circuit according to claim 5 or 6, wherein the phase signal producing means is arranged also to output a phase signal when the phase of the excitation signal passes through a second predetermined value different from the first predetermined value.

8. A circuit according to claim 7, wherein the processor is adapted to correct for any phase shift between the excitation signal and the electrical signal by comparing a first value of the electrical signal, sampled in response to a phase signal generated when the phase of the analogue signal passes through the first predetermined value, and a second value of the electrical signal, sampled in response to the phase signal generated when the phase of the analogue signal passes through the 48 second predetermined value.

9. A circuit according to claim 8, wherein the f irst predetermined value of the phase is 45' and the second 5 predetermined value of the phase is 135'.

10. A circuit according to claim 8 or claim 9, wherein the processor is adapted to calculate the sum of the square of the first value and the square of the second value, thereby obtaining a value that is independent of any phase shift between the analogue signal and the electrical signal.

11. A circuit according to claim 2, wherein the processor is arranged to sample the value of the electrical signal when the phase of the pattern whose phase most closely matches that of the electrical signal passes through a predetermined value.

12. A circuit according to any one of claims 6 to 11, further comprising analogue-to-digital converting means for converting the electrical signal into a digital signal before the electrical signal is sampled by the processor. 25

13. A transducer circuit for use with a transducer for converting the position of a probe into an electrical 49 signal dependent on the probe position, comprising: a clock for producing a train of clock signals at defined intervals; a sub-circuit for providing an analogue signal, whose voltage varies periodically in accordance with the train of clock signals, to the transducer; an analogue-to-digital convertor for converting the electrical signal into a digital signal; and a processor for analysing signals received from the sub-circuit and the analogue-to-digital convertorto provide a measurement signal providing a measurement of the position of the probes, wherein the processor is adapted to correct for any phase shift between the analogue signal and the electrical signal in accordance with information received from the subcircuit and the analogue-to-digital convertor.

14. A transducer circuit according to claim 13, wherein the clock is a crystal oscillator.

15. A transducer circuit according to claim 14, wherein the crystal oscillator is an integral part of the processor.

16. A transducer circuit according to any of claims 13 to 15, wherein the sub-circuit is arranged to provide the analogue signal so that the amplitude of the analogue signal varies sinusoidally.

17. A transducer circuit according to any of claims 13 to 16, wherein the sub-circuit is arranged to produce a phase signal indicating when the phase of the analogue signal passes through a first predetermined value.,

18. A transducer circuit according to claim 17, wherein the processor is arranged to sample the digital signal in response to the phase signal input from the subcircuit.

19. A transducer circuit according to either claim 17 or claim 18, wherein the sub-circuit is arranged also to output a phase signal when the phase of the analogue signal passes through a second predetermined value different from the first predetermined value.

20. A transducer circuit according to claim 19, wherein the processor is adapted to correct for any phase shift between the analogue signal and the electrical signal by comparing a first value of the digital signal, sampled in response to a phase signal generated when the phase of the analogue signal passes through the first predetermined value, and a second value of the digital signal, sampled in response to the phase signal generated 51 when the phase of the analogue signal passes through the second predetermined value.

21. A transducer circuit according to claim 20, wherein the first predetermined value of the phase is 45 and the second predetermined value of the phase is 1350.

22. A transducer circuit according to claim 20 or claim 21, wherein the processor is adapted to calculate the sum of the square of the first value and the square of the second value, thereby obtaining a value that is independent of any phase shift between the analogue signal and the digital signal.

23. A transducer circuit according to any of claims 13 to 16, wherein the processor is adapted to compare phase information for the electrical signal with a number of reference signals have varying phases and to thereby identify the reference signal whose phase most closely matches that of the electrical signal.

24. A transducer circuit according to claim 13, wherein the processor is arranged to sample the value of the digital signal output from the analogue-to-digital convertor when the phase of the reference signal whose phase most closely matches that of the electrical signal passes through a predetermined value.

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25. A transducer circuit according to any of claims 13 to 24, wherein the sub-circuit comprises: a counter for outputting a first train of predetermined numbers whose values cycle, the value of the output predetermined number being increased by one in response to a clock signal received from the clock; a memory containing a number of predetermined numbers stored in a number of memory locations identified by an address, the counter and the memory being arranged so that, in use, the output of the counter is input to the memory as the address of a memory location and the memory outputs the predetermined number stored in the memory location to form a second train of predetermined numbers whose values vary periodically; and a digital-to-analogue convertor for converting the second train predetermined numbers into the electrical signals.

26. A metrological instrument for measuring a characteristic of a surface of a workpiece, the instrument comprising an arm for holding a stylus to be traversed relative to the surface of the workpiece, a transducer for converting the position of the stylus into a corresponding electrical signal, and a control circuit comprising: an excitation signal generator for providing an excitation signal whose voltage varies in a known manner 53 with time to the transducer; and a processor for analysing the electrical signal from the transducer to generate a measurement signal providing a measurement of the position of the stylus; wherein the processor is adapted to correct for any phase shift between the excitation signal and the electrical signal.

27. A metrological instrument for measuring a characteristic of a surface of a workpiece, the instrument comprising an arm for holding a stylus to be traversed relative to the surface of the workpiece, a transducer for converting the position of the stylus into a corresponding electrical signal, and a control circuit comprising: an excitation signal generator for providing to the transducer an excitation signal whose voltage varies in a known manner with time; and a processor for analysing the electrical signal from the transducer to generate a measurement signal providing a measurement of the position of the stylus; wherein the processor is adapted to calculate the phase of the electrical signal by comparing the electrical signal with information about a number of patterns with varying phase properties and identifying the pattern whose phase most closely matches that of the electrical signal.

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28. A metrological instrument for measuring a characteristic of a surface of a workpiece, the instrument comprising an arm for holding a stylus to be traversed relative to the surf ace of the workpiece and a transducer circuit for providing a measurement signal indicative of the displacement of the stylus as it follows the surface of the workpiece, said transducer circuit comprising:

a transducer for providing in response to an excitation signal an output signal which changes with displacement of the stylus as it follows the surface of the workpiece; signal generating means for generating as the transducer excitation signal a signal having an amplitude which varies with time in a predetermined manner; processing means for determining the displacement of the stylus as it traverses the surface of the workpiece by comparing information relating to the excitation signal and derived from the signal generating means with the output signal of the transducer to determine whether there is any phase difference between the output signal from the transducer and the excitation signal and for determining the displacement of the stylus from the output signal after compensating for any such phase difference.

29. A metrological instrument for measuring a characteristic of a surface of a workpiece, the instrument comprising an arm for holding a probe to be traversed relative to the surface of the workpiece and a circuit according to any one of claims 1 to 25. 5

30. A metrological instrument for measuring a characteristic of a surface of a workpiece, -said metrological instrument comprising: an arm for holding a stylus to be traversed relative to the surface of the workpiece, said arm being pivotably mounted on the main body of the metrological instrument; and a variable inductance transducer for converting the position of the stylus into a corresponding electrical signal, said variable inductance transducer including a core having at least two coils located thereon and spaced apart along the length of the arm such that, in use, pivotal movement of the arm causes different changes in the inductance of the coils thereby providing indication of the position of the stylus.

31. A metrological instrument according to claim 30, wherein the two coils are spaced along the length of the arm so as to be arranged symmetrically about the pivot point of the arm.

32. A metrological instrument for measuring a 56 characteristic of a surface of a workpiece, said metrological instrument comprising: an arm for holding a stylus to be traversed relative to the surf ace of the workpiece, said arm being pivotably mounted on the main body of the metrological instrument; and a variable inductance transducer f or converting the position of the stylus into a corresponding electrical signal, said variable inductance transducer including:

a first core; a second core having a backbone and portions projecting away from the backbone and each carrying a respective coil, such that, in use, pivotal movement of the arm causes relative movement between the first core and the second core thereby altering the inductance of the coils.

33. An instrument according to claim 32, wherein the second core further comprises an intermediate portion projecting from the backbone, between said coil carrying projecting portions.

34. An instrument according to claim 33 or 34 wherein one of the f irst and second cores is mounted so as to move with the arm and the other of the first and second cores as fixed to the main body.

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35. An instrument according to any one of claims 30 to 34 wherein the core carrying the coils is fixed to the main body.

36. A variable inductance transducer for a metrological instrument having the variable inductance transducer features recited in any one of claims 30 to 35.