GB2337619A - Threshold voltage verification method and circuit for program and erasure verification of a non-volatile memory cell - Google Patents

Threshold voltage verification method and circuit for program and erasure verification of a non-volatile memory cell Download PDF

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Publication number
GB2337619A
GB2337619A GB9910010A GB9910010A GB2337619A GB 2337619 A GB2337619 A GB 2337619A GB 9910010 A GB9910010 A GB 9910010A GB 9910010 A GB9910010 A GB 9910010A GB 2337619 A GB2337619 A GB 2337619A
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United Kingdom
Prior art keywords
threshold voltage
erasure
cell
program
circuit
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
GB9910010A
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GB9910010D0 (en
GB2337619A8 (en
GB2337619B (en
Inventor
Bok Nam Song
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SK Hynix Inc
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Hyundai Electronics Industries Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Priority claimed from KR1019950005924A external-priority patent/KR0145382B1/en
Application filed by Hyundai Electronics Industries Co Ltd filed Critical Hyundai Electronics Industries Co Ltd
Publication of GB9910010D0 publication Critical patent/GB9910010D0/en
Publication of GB2337619A publication Critical patent/GB2337619A/en
Publication of GB2337619A8 publication Critical patent/GB2337619A8/en
Application granted granted Critical
Publication of GB2337619B publication Critical patent/GB2337619B/en
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

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Classifications

    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C16/00—Erasable programmable read-only memories
    • G11C16/02—Erasable programmable read-only memories electrically programmable
    • G11C16/06—Auxiliary circuits, e.g. for writing into memory
    • G11C16/34—Determination of programming status, e.g. threshold voltage, overprogramming or underprogramming, retention
    • G11C16/3436—Arrangements for verifying correct programming or erasure
    • G11C16/344—Arrangements for verifying correct erasure or for detecting overerased cells
    • G11C16/3445—Circuits or methods to verify correct erasure of nonvolatile memory cells
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C16/00—Erasable programmable read-only memories
    • G11C16/02—Erasable programmable read-only memories electrically programmable
    • G11C16/06—Auxiliary circuits, e.g. for writing into memory
    • G11C16/34—Determination of programming status, e.g. threshold voltage, overprogramming or underprogramming, retention
    • G11C16/3436—Arrangements for verifying correct programming or erasure
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C16/00—Erasable programmable read-only memories
    • G11C16/02—Erasable programmable read-only memories electrically programmable
    • G11C16/06—Auxiliary circuits, e.g. for writing into memory
    • G11C16/34—Determination of programming status, e.g. threshold voltage, overprogramming or underprogramming, retention
    • G11C16/3436—Arrangements for verifying correct programming or erasure
    • G11C16/3454—Arrangements for verifying correct programming or for detecting overprogrammed cells
    • G11C16/3459—Circuits or methods to verify correct programming of nonvolatile memory cells
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C16/00—Erasable programmable read-only memories
    • G11C16/02—Erasable programmable read-only memories electrically programmable
    • G11C16/06—Auxiliary circuits, e.g. for writing into memory
    • G11C16/34—Determination of programming status, e.g. threshold voltage, overprogramming or underprogramming, retention
    • G11C16/3436—Arrangements for verifying correct programming or erasure
    • G11C16/3468—Prevention of overerasure or overprogramming, e.g. by verifying whilst erasing or writing
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
    • G11C29/04—Detection or location of defective memory elements, e.g. cell constructio details, timing of test signals
    • G11C29/50—Marginal testing, e.g. race, voltage or current testing
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
    • G11C29/04—Detection or location of defective memory elements, e.g. cell constructio details, timing of test signals
    • G11C29/50—Marginal testing, e.g. race, voltage or current testing
    • G11C29/50004—Marginal testing, e.g. race, voltage or current testing of threshold voltage
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
    • G11C29/52—Protection of memory contents; Detection of errors in memory contents
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F2201/00—Indexing scheme relating to error detection, to error correction, and to monitoring
    • G06F2201/81—Threshold
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C16/00—Erasable programmable read-only memories
    • G11C16/02—Erasable programmable read-only memories electrically programmable
    • G11C16/04—Erasable programmable read-only memories electrically programmable using variable threshold transistors, e.g. FAMOS

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  • Read Only Memory (AREA)

Abstract

A threshold voltage verification method or circuit for program or erasure verification of a non-volatile memory cell comprises supplying a bias voltage to a gate, a drain and a source of a non-volatile memory cell during program mode or erasure mode and sensing threshold voltage of the cell by using means, such as an inverter of which the input logic threshold voltage is equal to the threshold voltage of the cell. A further aspect relates to generating first logic signals, such as from inverters G1-G3 according to each drain current of selected memory cells 4 for a program mode, generating a program verification signal S1 from a combination of the first logic signals, such as in a NOR gate, generating second logic signals, such as from inverters G4-G6 according to each drain current of selected memory cells 4 for an erasure mode, and generating an erasure verification signal S2 according to a combination of the second logic signals, such as in an AND gate. Even if the threshold voltage of any memory cell is less than a predetermined threshold voltage for an erasure mode, over erasure can be prevented by an output signal S3 of a NAND gate connected to inverters G7-G9.

Description

1 2337619 THRESHOLD VOLTAGE VERIFICATION CIRCUIT OF A NON-VOLATILE MEMORY
CELL AND PROGRAM AND ERASURE VERIFICATION METHOD USING THE SAME
FIELD OF THE INVENTION
This invention relates to a non-volatile memory cell, and more particularly to a threshold voltage verification circuit of a nonvolatile memory cell and a program and erasure verification method using the same which can automatically verify a threshold voltage to the cell according to the change of electron charge which is injected to a floating gate of the cell in program operation and erasure operation for the cell.
INFORMATION DISCLOSURE STATEMENT
Generally, a flash EEPROM (Electrically Erasable Pr ogrammable Read Only Memory) cell having program and erasure functions has a plurality of merits, thereby gradually increasing its demand. In a case where program bias voltage (for example, 12 volts) is applied to a control gate electrode for a desired time, tl through t2 time of FIG. 1B, using a bias voltage generator 1 of FIG. 1A, and a source electrode is ground while a constant voltage (V D) is applied to a drain electrode. electron charge is injected to a floating gate of the cell, so the cell is programmed. To verify whether or not the charge is injected to the floating gate by the predetermined amount, a read bias voltage, for example, 5 volts, is applied to the control gate electrode 2, from the bias voltage generator 1, for a desired time, t2 through t3 1 time of FIG. 1B, then cell current (that is, cell threshold voltage) is sensed. If the sensed threshold voltage is smaller that a predetermined level, a program bias voltage (12 volts) from the bias voltage generator 1 must be applied to the control gate electrode, for t3 through t4 time of FIG. 1B, and threshold voltage of the cell must be verified again. That is, the threshold voltage must be verified after the program bias voltage is repeatedly applied to the control gate electrode, so that electron charge is injected to the floating gate and the threshold voltage of the cell reaches a predetermined voltage level. In charging and discharging the control gate to a desired level, a lot of time is spent because the bias voltage applied to the control gate 2 swings between a program mode and a verification mode, that is, from 12 volts to 5 volts or in inversion. Accordingly, there are problems that byte program time is increased and it is difficult to embody a verification circuit. Also, there is a shortcoming that over-erasure occurs for erasure mode.
SUMARY OF IMMNTION
Therefore, an object of this invention is to provide a threshold verification circuit of a non-volatile memory cell and a program and erasure verification method using the same which can solve the above problems, by automatically verifying threshold voltage of the cell according to the change of electron charge which is injected to a floating gate of the cell in program and erasure operations for the cell.
To accomplish the above object, a threshold voltage verification circuit of a non-volatile memory device comprising:
2 a first means for generating logic signals according to each drain current of selected memory cels for program mode; means for generating a program verification signal according to combination of said logic signals from said first means; a second means for generating logic signals according to each drain current of selected memory cells for erasure mode; and means for generating an erasure verification signal according to combination of said logic signal from said second means.
A program verification method of the invention, comprises the steps of:
supplying a bias voltage for program mode to a control gate, a drain and a source of a non-volatile memory cell; and sensing threshold voltage of said cell by using an inverter of which input logic threshold voltage is equal to threshold voltage of said cell.
An erasure verification method of the comprises the steps of:
invention, supplying a bias voltage for erasure mode to a gate, a drain and a source of a non-volatile memory cell; and sensing threshold voltage of said cell by using an inverter of which input logic threshold voltage is equal to threshold voltage of said cell.
BRIEF DESCRIPTION OF THE DRAWINGS
For fuller understanding of the nature and objects of the invention, reference should be made to the following detailed description and the accompanying drawings in which:
3 FIG - 1A is a cross-sectional view of a flash EEPROM cell; FIG. 1B is a waveform for explaining the electrical operation of FIG. 1A; FIG. 2A and FIG. 2B are threshold voltage verification circuits of a non- volatile memory cell according to the present invention; FIG. 3A and FIG. 3B are equivalent circuits of a flash EEPROM cel.l; FIG. 4 is a waveform illustrating threshold voltage and drain current of the flash EEPROM cell; FIG- 5 is a waveform illustrating change of drain current which is changed according to floating gate voltage of a flash EEPROM cell; and FIG. 6 is a circuit for explaining program and erasure verification method.
Similar reference characters refer to similar parts in the several views of the drawings.
DETAILED DESCRIPTION OF THE INVENTION
FIG. 2A and FIG. 2B are threshold voltage verification circuits of a nonvolatile memory cell, which will be described with reference to FIG. 3A and FIG. 3B.
Cell current (1d) flowing through a drain electrode during program operation or erasure operation is determined by the channel inversion of a flash EEPROM cell, that is, such a cell current is actually determined by floating gate voltage (Vfg) which acts in gate. Voltage (Vfg) induced to a floating gate through a capacitor is dependent upon a control gate voltage (Vcg), which is an external applied voltage, and drain 4 voltage (Vd) will be obtained as follows:
Vfg = KP X Vcg + M X Vd + Qfg/Ct Vtx = -Qf g/kp where, KP; control gate to floating gate coupling ratio (about 0. 5) kd: drain to floating gate coupling ratio (about 0.25) Qf g: stored charge in f loating gate; Ct: parallel capacitance of Cp and Cox (Cl + C2) Vtx: cell threshold voltage.
That is, the floating gate voltage will be expressed as the following equation:
Vf g (t) = Kp X Vcg + M X Vd - Kp X Vtx (t) (A) By the above equation (A), reflects that change of cell threshold voltage (Vtx) according to change of the time is linearly proportional to the floating gate voltage (Vfg). Where the cell threshold voltage (Vtx) is from 2 volts through 5 volts, the floating gate voltage Vfg will be presumed 'as follows:
If Vtx = 2 volts, Vfg = 8 volts; If Vtx = 5 volts, Vfg = 6 volts.
Hence, assuming that the cell is operated in the linear region of a MOS transistor, cell current (1d) is proportional to the floating gate voltage. As a result, the cell current (1d) is reduced more than 25 percent (6V/8V). as a minimum.
FIG. 4 illustrates change of cell threshold voltage (Vtx) according to change of the time (t), and change of cell current (1d), while FIG. 5 ilustrates change of cell current according to the floating gate voltage (Vf g) Assuming that the circuit to automatically verify the cell threshold voltage during program operation is constructed as FIG. 2A, cell drain voltage (Vd(t)) is as follows:
Vd (t) = Vcc-R X Id(t) (B) Where, Vcc: supply voltage; R: resistor; Id(t): drain current of the cell.
Hence, assuming that the cell current (1d) is reduced as much as Io from initial current (1o) due to programming for t=tl time, drain voltage (Vd(t)) is obtained as follows:
Vd(t) = Vcc-R (Io - I0) (C) Accordingly, if input threshold voltage level of an inverter 11 of FIG. 2A follows the equation (C), an output of the inverter 11 is inverted at that time. As a result, the cell threshold voltage can be automatically sensed simultaneously with programming of the cell.
FIG. 2B illustrates a circuit for erasure mode and a bias condition thereof. The circuit of erasure mode is equivalent to that of program mode, except for the bias condition. Accordingly, erasure state of the cell can be verified in the same manner as for the program mode of FIG. 2A. However, to verify the erasure state, together with prevention of overerasure phenomenon of the cell during erasure mode, two (2) inverters, of which threshold voltage is different from each other, are required. An embodiment of the invention which can verify a desired threshold voltage during a byte program and a byte erasure using the above principle will be explained through FIG. 6.
In program operation, program voltage (5 volt) from a bias voltage generator 1 is applied to a cell array 4. During 6 program operation, if memory cells selected from each cell array 4 are sufficiently programmed, the threshold voltage of each cell is inverted by inverters G1, G2 and G3, respectively, and the program state is then verified by an output signal S1 of a NOR gate (NOR), whose input terminals are connected to output terminals of the inverters G1, G2 and G3.
In erasure operation, erasure voltage (12 volt) from the bias generator 1 is applied to the cell array 4. During erasure operation, if memory cells selected from each cell array 4 reach a predetermined threshold voltage level of an erasure state, the threshold voltage of each cell is inverted by inverters G4, G5 and G6, respectively and the erasure state is then verified by an output signal S2 of an AND gate (AND), whose input terminals are connected to output terminals of the inverters G4, G5 and G6.
In the meantime, even if the threshold voltage of any one memory cell is less than a predetermined threshold voltage for erasure mode, overerasure can be prevented by an output signal S3 of NAND gate NAND, whose input terminals are connected to inverters G7, G8 and G9.
If the bias voltage generator is adequately controlled by the output signals SI, S2 and S3, it is possible to verify cell threshold voltage rapidly.
As described above, according to the present invention, since cell threshold voltage can be automatically verified by change of electron charge injected to a floating gate during program and erasure mode, program and erasure time for the cell is reduced, and over-erasure, which often occurs in stacked type cell, is prevented. An excellent advantage is 7 that this can. simplify the whole circuit of a flash memory device, since a separate threshold voltage verification circuit is not required.
The foregoing description, although described in its preferred embodiment with a certain degree of particularity, is only illustrative of the principle of the present invention. It is to be understood that the present invention is not to be limited to the preferred embodiments disclosed and illustrated herein. Accordingly, all expedient variations that may be made within the scope of the present invention are to be encompassed as further embodiments of the present invention.
8

Claims (12)

  1. What is claimed is: 1. A threshold voltage verification c-ircuit of a
    nonvolatile memory device comprising: a first means for generating logic signals according to each drain current of selected memory cells for program mode; means for generating a program verification signal according to combination of said logic signals from said first means; a second means for generating logic signals according to each drain current of selected memory cells for erasure mode; and means for generating an erasure verification signal according to combination of said logic signal from said second means.
  2. 2. The current of claim 1, wherein said first means comprises a plurality of inverters.
  3. 3. The circuit of claim 1, wherein said comprises a plurality of inverters.
    second means
  4. 4. The circuit of claim 1, wherein said means for generating the program verification signal comprises a NOR gate.
  5. 5. The circuit of claim 1, wherein said means for generating the erasure verification signal comprises an AND gate.
  6. 6. The circuit of claim 2 or claim 3, wherein each input logic threshold voltage of said inverters is equal to each threshold voltage of said cells.
    9
  7. 7. The circuit of claim 1, further comprising: a third means for generating logic signals according to each drain current of selected memory cell for erasure mode; and means f or an over erasure signal according to the combination of said logic signal f rom said third means.
  8. 8. The circuit of claim 7, wherein said third means comprises a plurality of inverters.
  9. 9. The circuit of claim 1, wherein said means for generating the over erasure signal comprises a NAND gate.
  10. 10. The circuit of claim 8, wherein each input logic threshold voltage of said inverters is equal to each threshold voltage of said cells.
  11. 11. A program verification method comprising the steps of: supplying a bias voltage for program to a control gate, a drain and a source of a nonvolatile memory cell; and sensing threshold voltage of said cell by using an inverter of which input logic threshold voltage is equal to threshold voltage of said cell.
  12. 12. An erasure verification method, comprising the steps of: supplying a bias voltage for erasure to a gate, a drain and a source of a nonvolatile memory cell; and sensing threshold voltage of said cell by using an inverter of which input logic threshold voltage is equal to threshold voltage of said cell.
GB9910010A 1995-03-21 1996-03-19 Threshold voltage verification circuit of a non-volatile memory cell and program and erasure verification method using the same Expired - Fee Related GB2337619B (en)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
KR1019950005924A KR0145382B1 (en) 1995-03-21 1995-03-21 Auto-threshold verify circuit of flash eeprom
GB9605762A GB2299190B (en) 1995-03-21 1996-03-19 Threshold voltage verification circuit of a non-volatile memory cell

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GB9910010D0 GB9910010D0 (en) 1999-06-30
GB2337619A true GB2337619A (en) 1999-11-24
GB2337619A8 GB2337619A8 (en) 1999-11-29
GB2337619B GB2337619B (en) 2000-03-01

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Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0246965A1 (en) * 1986-05-23 1987-11-25 Thomson Composants Militaires Et Spatiaux Security device for an EPROM
GB2215155A (en) * 1988-02-17 1989-09-13 Intel Corp Program/erase selection for flash memory
EP0438172A1 (en) * 1990-01-19 1991-07-24 Kabushiki Kaisha Toshiba Semiconductor memory device having monitoring function
US5371706A (en) * 1992-08-20 1994-12-06 Texas Instruments Incorporated Circuit and method for sensing depletion of memory cells

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0246965A1 (en) * 1986-05-23 1987-11-25 Thomson Composants Militaires Et Spatiaux Security device for an EPROM
GB2215155A (en) * 1988-02-17 1989-09-13 Intel Corp Program/erase selection for flash memory
EP0438172A1 (en) * 1990-01-19 1991-07-24 Kabushiki Kaisha Toshiba Semiconductor memory device having monitoring function
US5371706A (en) * 1992-08-20 1994-12-06 Texas Instruments Incorporated Circuit and method for sensing depletion of memory cells

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GB9910010D0 (en) 1999-06-30
GB2337619A8 (en) 1999-11-29
GB2337619B (en) 2000-03-01

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Effective date: 20130319