GB2337361A - A method of etching a tantalum oxide layer in the fabrication of a DRAM - Google Patents
A method of etching a tantalum oxide layer in the fabrication of a DRAM Download PDFInfo
- Publication number
- GB2337361A GB2337361A GB9809657A GB9809657A GB2337361A GB 2337361 A GB2337361 A GB 2337361A GB 9809657 A GB9809657 A GB 9809657A GB 9809657 A GB9809657 A GB 9809657A GB 2337361 A GB2337361 A GB 2337361A
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- reactive gas
- gaseous
- chlorine
- flow rate
- nitrogen
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- 238000000034 method Methods 0.000 title claims abstract description 47
- BPUBBGLMJRNUCC-UHFFFAOYSA-N oxygen(2-);tantalum(5+) Chemical compound [O-2].[O-2].[O-2].[O-2].[O-2].[Ta+5].[Ta+5] BPUBBGLMJRNUCC-UHFFFAOYSA-N 0.000 title claims abstract description 39
- 229910001936 tantalum oxide Inorganic materials 0.000 title claims abstract description 39
- 238000005530 etching Methods 0.000 title claims description 41
- 238000004519 manufacturing process Methods 0.000 title claims description 10
- IJGRMHOSHXDMSA-UHFFFAOYSA-N Atomic nitrogen Chemical compound N#N IJGRMHOSHXDMSA-UHFFFAOYSA-N 0.000 claims abstract description 56
- FAQYAMRNWDIXMY-UHFFFAOYSA-N trichloroborane Chemical compound ClB(Cl)Cl FAQYAMRNWDIXMY-UHFFFAOYSA-N 0.000 claims abstract description 44
- 239000000460 chlorine Substances 0.000 claims abstract description 40
- 239000007789 gas Substances 0.000 claims abstract description 40
- 239000003990 capacitor Substances 0.000 claims abstract description 36
- ZAMOUSCENKQFHK-UHFFFAOYSA-N Chlorine atom Chemical compound [Cl] ZAMOUSCENKQFHK-UHFFFAOYSA-N 0.000 claims abstract description 32
- 229910052801 chlorine Inorganic materials 0.000 claims abstract description 32
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims abstract description 29
- 229920005591 polysilicon Polymers 0.000 claims abstract description 29
- NRTOMJZYCJJWKI-UHFFFAOYSA-N Titanium nitride Chemical compound [Ti]#N NRTOMJZYCJJWKI-UHFFFAOYSA-N 0.000 claims abstract description 28
- 229910052757 nitrogen Inorganic materials 0.000 claims abstract description 28
- 239000008246 gaseous mixture Substances 0.000 claims abstract description 24
- 230000004888 barrier function Effects 0.000 claims abstract description 12
- 239000000758 substrate Substances 0.000 claims abstract description 12
- 239000004065 semiconductor Substances 0.000 claims abstract description 10
- 238000000059 patterning Methods 0.000 claims description 12
- 238000000151 deposition Methods 0.000 claims description 9
- ZOXJGFHDIHLPTG-UHFFFAOYSA-N Boron Chemical compound [B] ZOXJGFHDIHLPTG-UHFFFAOYSA-N 0.000 claims 2
- 229910052796 boron Inorganic materials 0.000 claims 2
- 239000000203 mixture Substances 0.000 claims 1
- 125000000449 nitro group Chemical group [O-][N+](*)=O 0.000 claims 1
- 229910052715 tantalum Inorganic materials 0.000 claims 1
- GUVRBAGPIYLISA-UHFFFAOYSA-N tantalum atom Chemical compound [Ta] GUVRBAGPIYLISA-UHFFFAOYSA-N 0.000 claims 1
- FIDSKVVUWACGOK-UHFFFAOYSA-N [Cl].ClB(Cl)Cl Chemical compound [Cl].ClB(Cl)Cl FIDSKVVUWACGOK-UHFFFAOYSA-N 0.000 abstract 1
- 239000004615 ingredient Substances 0.000 description 6
- 238000006243 chemical reaction Methods 0.000 description 4
- 239000002131 composite material Substances 0.000 description 4
- 238000010586 diagram Methods 0.000 description 4
- 238000011109 contamination Methods 0.000 description 3
- 230000008859 change Effects 0.000 description 2
- 150000001455 metallic ions Chemical class 0.000 description 2
- 238000012986 modification Methods 0.000 description 2
- 230000004048 modification Effects 0.000 description 2
- 229920002120 photoresistant polymer Polymers 0.000 description 2
- 239000003795 chemical substances by application Substances 0.000 description 1
- 238000013500 data storage Methods 0.000 description 1
- 238000010494 dissociation reaction Methods 0.000 description 1
- 230000005593 dissociations Effects 0.000 description 1
- 239000000463 material Substances 0.000 description 1
- 229910044991 metal oxide Inorganic materials 0.000 description 1
- 150000004706 metal oxides Chemical class 0.000 description 1
- QJGQUHMNIGDVPM-UHFFFAOYSA-N nitrogen group Chemical group [N] QJGQUHMNIGDVPM-UHFFFAOYSA-N 0.000 description 1
- 238000002161 passivation Methods 0.000 description 1
- 230000008569 process Effects 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/3105—After-treatment
- H01L21/311—Etching the insulating layers by chemical or physical means
- H01L21/31105—Etching inorganic layers
- H01L21/31111—Etching inorganic layers by chemical means
- H01L21/31116—Etching inorganic layers by chemical means by dry-etching
- H01L21/31122—Etching inorganic layers by chemical means by dry-etching of layers not containing Si, e.g. PZT, Al2O3
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L28/00—Passive two-terminal components without a potential-jump or surface barrier for integrated circuits; Details thereof; Multistep manufacturing processes therefor
- H01L28/40—Capacitors
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B12/00—Dynamic random access memory [DRAM] devices
- H10B12/01—Manufacture or treatment
- H10B12/02—Manufacture or treatment for one transistor one-capacitor [1T-1C] memory cells
- H10B12/03—Making the capacitor or connections thereto
Landscapes
- Engineering & Computer Science (AREA)
- Power Engineering (AREA)
- Computer Hardware Design (AREA)
- Manufacturing & Machinery (AREA)
- Chemical & Material Sciences (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Chemical Kinetics & Catalysis (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Physics & Mathematics (AREA)
- Inorganic Chemistry (AREA)
- General Chemical & Material Sciences (AREA)
- Semiconductor Memories (AREA)
Abstract
The method comprises the steps of forming the lower capacitor electrode structure 22 comprising polysilicon on a semiconductor substrate 20. Then, a tantalum oxide layer 23, a titanium nitride barrier layer 24 and a conductive layer 25 comprising polysilicon are sequentially formed over the lower electrode structure and the substrate. Next, the conductive layer 25 is pattern using a first reactive gas that includes a gaseous mixture of boron trichloride chlorine and nitrogen (BCl 3 /Cl 2 /N 2 ). Thereafter, the barrier layer 24 is patterned using a second reactive gas that includes a gaseous mixture of boron trichloride, chlorine and nitrogen (BCl 3 /Cl 2 /N 2 ). Finally, the tantalum oxide layer 23 is patterned using a third reactive gas that includes a gaseous mixture of boron trichloride, chlorine and nitrogen (BCl 3 /Cl 2 /N 2 ).
Description
2337361 METHOD FOR ETCHING TANTALUM OXIDE LAYER
BACKGROUND OF THE INVENTION
Field of Invention
The present invention relates to a method for etching a tantalum oxide (TaO,) layer. More particularly, the present invention relates to a method of manufacturing dynamic random access memory (DRAM) that involves the sequential etching of a polysilicon layer and a tantalum oxide layer to form a pattern without having to switch etchiner stations.
Description of Related Art
A conventional dynamic random access memory (DRAM) structure at least includes a metal oxide semiconductor (MOS) transistor and a capacitor. The gate of the transistor is connected to a word line, and one of the source/drain regions is connected to a bit line BL. The other source/drain region is electrically connected to a capacitor, which in turn is connected to a ground. The capacitor structure in a DRAM can be regarded as a critical component in data storage. If the number of charges stored by a capacitor is large, the data bit stored in the capacitor is more stable. When the data bit stored in the capacitor is read out by an amplifier, a large capacitance is more capable of combating external noise.
In semiconductor manufacturing, a DRAM capacitor is formed by several steps. First, at least one transistor structure is formed on a semiconductor substrate, and then a stora.e node is formed above one of the source/drain reuions of the transistor, thereby c Z 2 forming the lower electrode structure of a capacitor. Next, a tantalum oxide layer, a titanium nitride layer (TiN) and a polysilicon layer are formed sequentially over the lower electrode structure. The titanium nitride layer is formed above the tantalum oxide layer, and the two layers together constitute a composite dielectric layer for the capacitor. The polysilicon layer acts as an upper electrode structure of the capacitor. Finally, the tantalum oxide layer, the titanium nitride layer and the polysilicon layer are patterned to complete the DRAM capacitor structure.
Fig. 1 is a flow diagram showing the conventional manufacturing steps in patterning a multi-layered capacitor structure. First, step 10 represent the beginning of the operation where the multllayered structure of the capacitor, including the lower electrode structure, the tantalum oxide layer, the titanium nitride layer and the polysilicon layer, has already been deposited. Next, step 12 is carried out by first performing a photolithographic operation, and then etching the polysilicon layer to form the upper electrode structure of the capacitor. Preferably, the etchant for etching the polysilicon layer is a gaseous mixture containing HBr/C12/He-0,. Thereafter, a change in etching station is performed in step 14. The change is necessary because the etchant for etching the polysillcon layer is unsuitable for etching the tantalum oxide layer and the titanium nitride layer. Next, step 16 is carried out etching the titanium nitride layer and the tantalum oxide layer (TiN/Ta,0J, thereby patterning the composite dielectric layer of the capacitor.
In patterning the tantalum oxide layer, the titanium nitride layer and the polysilicon layer, some problems often arise. The most severe problem occurs when etching of the polysilicon layer is finished, and the titanium nitride layer needs to be etched next. The etchant for etching the polysilicon layer is a gaseous mixture 3 containing liBr/C],/He-O., which is unsuitable for etching titanium nitride. Therefore, both the processing station and the etchants need to be changed before subsequent etching of the titanium nitride layer and the tantalum oxide can be performed. This switchover of processing station and etchants increases the number of processing steps.
Moreover, some residual etchants used in etching the polysilicon layer may be carried over into the next etching operation. When they come into contact with the titanium nitride layer, some metallic ion dissociation may occur. Consequently, the reaction chamber may be contaminated.
In light of the foregoing, there is a need to improve the process of etching the io polysilicon layer, the titanium nitride layer and the tantalum oxide layer.
SUMMARY OF THE rNVENTION
Accordingly, the present invention provides a method of etching a tantalum oxide layer that uses innovative etchants including a gaseous mixture 0 0 /N containin boron trichloride, chlorine and nitroaen (BC13/C12 1_). Using the gaseous mixture, the multi-layered structure of a capacitor can be etched in a single etching operation, moreover, there is no contamination of the reaction chamber.
To achieve these and other advantages and in accordance with the purpose of the invention, as embodied and broadly described herein, the invention provides a method of etching tantalum oxide layer in the fabrication of DRAM. The method comprises the steps of forming the lower electrode structure of a capacitor on a semiconductor substrate and then sequentially forming a tantalum oxide layer, a barrier layer and a conductive layer over the substrate and the lower electrode structure. Next, the conductive layer I's patterned using a first reactive gas that includes a gaseous mixture of 1 4 boron trichloride, chlorine and nitrogen (BC1,Xl,/N,). Thereafter, the barrier layer is pattern using a second reactive gas that includes a gaseous mixture of boron trichloride, chlorine and nitrogen (BC131C12). Finally, the tantalum oxide layer is patterned IN using a third reactive gas that includes a gaseous mixture of boron trichloride, chlorine and nitrogen (BC'3/C',-N,-).
It is to be understood that both the foregoing general description and the following detailed description are exemplary, and are intended to provide further explanation of the invention as claimed.
is BRIEF DESCRIPTION OF THE DRAWINGS
The accompanying drawings are included to provide a further understanding of the invention, and are incorporated in and constitute a part of this 1 ification. The drawings illustrate embodiments of the invention and, together with specl 1 the description, serve to explain the principles of the invention. In the drawings,
Fig. 1 is a flow diagram showing the conventional manufacturing steps in patterning a multi-layered capacitor structure; Figs. 2A and 2B are cross-sectional views showing the progression of manufacturing steps in patterning a multi-layered capacitor structure (including a tantalum oxide layer) on a capacitor according to one preferred embodiment of this 20 invention; and Fig. 3 Is a flow diagram showing the steps in patterning a multi-layered capacitor structure according to the preferred embodiment of this invention.
DESCRIPTION OF THE PREFERRED EMBODIMENTS
Reference will now be made in detail to the present preferred embodiments of the invention, examples of which are illustrated in the accompanying drawinas. Wherever possible, the same reference numbers are used in the drawings and the description to refer to the same or like parts.
This invention provides an innovative etchant that contains a gaseous mixture of boron trichloride, chlorine and nitrogen (BC1,Xl,/N.). The characteristic property of this etchant is that it can etch polysilicon, titanium nitride (TiN) and tantalum oxide (Ta,0,), Therefore, a single etching operation can be used to form the multi-layered structure of a capacitor. Moreover, the method is capable of reducing severe contamination of the reaction chamber.
Figs. 2A and 2B are cross-sectional views showing the progression of manufacturing steps in patterning a multi-layered capacitor structure (including a tantalum oxide layer) on a capacitor according to one preferred embodiment of this invention. First, as shown in Fig. 2A, a patterned insulating layer 21 is formed over a semiconductor substrate 20. Next, the lower electrode structure 22 of a capacitor, for example, a polysilicon layer is formed in the insulating layer 21 for electrically connecting a source/drain region (not shown) in the substrate 20. Thereafter, a multilayered structure is formed over the lower electrode structure 22 and the insulating layer 21. The multi-layered structure is formed by depositing a thin tantalum oxide layer 23, a thin titanium nitride layer 24 and a polysilicon layer 25. The titanium nitride layer 24 is formed over the tantalum oxide layer 23, and the two layers together form a composite dielectric structure. Since tantalum oxide has a very hiah dielectric constant of about 20 to 30, the tantalum oxide layer 23 is capable of increasing the capacitance of 6 the capacitor. Hence, the tantalum oxide layer has applications in fabricating 16M DRAM. Subsequently, a photoresist layer 26 is formed over the polysilicon layer 25.
Next, as shown in Fig. 2B, photolithographic and etching operations are carried out using the photoresist layer 26 as a mask. The polysilicon layer 25, the thin titanium nitride layer 24 and the thin tantalum oxide layer 23 are etched sequentially using the characteristic etchant of this invention. The etchant is a gaseous mixture including boron trichloride, chlorine and nitrogen (BCI,/C'.,/N2). The ingredients of the gaseous mixture are mixed together in a ratio according to Table 1 below.
Table L Relative gas flow rate of gaseous ingredients for etching polysilicon, c) titanium nitride and tantalum oxide.
Ingredients (Gaseous) Gas Flow Rate (Unit: sccm) Chlorine (CL) 20-80 Boron Trichloride (BC13) 20-80 Nitrogen (NJ 20-80 In Table 1, the unit sccm refers to the gas flow rate in standard cubic centimeter per minute, and each ingredient in the gaseous mixture performs a definite function.
W For example, chlorine Cl. is a main reactive gas for etching, boron trichloride BC13 'S used as an agent for carrying out physical bombardment, and the gaseous nitrogen functions as sidewall passivation material.
Fig. 3 is a flow diagram showing the steps in patterning a multi-layered capacitor structure according to the preferred embodiment of this invention. First, step 30 represent the beginning of the operation where the multi-layered structure of the 7 capacitor, including the lower electrode structure, the tantalum oxide layer, the titanium nitride layer and the polysilicon layer, has already been deposited. Next, step 32 is carried out by first performing a photolithographic operation, and then etching the polysilicon layer to form the upper electrode structure of the capacitor. Preferably, the etchant for etching the polysilicon layer is a gaseous mixture of boron trichloride, chlorine and nitrogen (BC1,/CL/N.). Next, step 34 is carried out, etching the titanium nitride layer and the tantalum oxide layer (TiN/Ta,05) to form the composite dielectric structure of the capacitor. Preferably, the etchant for etching the polysilicon layer is a gaseous mixture of boron trichloride, chlorine and nitrogen (BCI,/CI,/N.). Hence, a complete capacitor structure is formed in a single etching operation using the gaseous mixture includin., boron trichloride, chlorine and nitrogen.
In summary, the method of etching tantalum oxide layer provided by this invention has the following advantages including:
(1) The etchant provided by this invention, namely, a gaseous mixture having the ingredients BCI,/CI./N,, is capable of etching a polysilicon layer, a titanium nitride layer and a tantalum oxide layer to form a uniform pattern.
(2) The etchant provided by this invention, namely, a gaseous mixture having the ingredients BC13ICI,/N., is able to etch a pattern out of the multi-layered structure in a single etching operation. Therefore, processing steps are saved.
(3) The etchant used in this invention does -not dissociate metallic ions on contact with a titanium nitride layer. Therefore, contamination of reaction chamber is greatly reduced.
It will be apparent to those skilled in the art that various modifications and variations can be made to the structure of the present invention without departing ftorn 8 the scope or spirit of the invention. In view of the foregoing, it is intended that the present invention cover modifications and variations of this invention provided they fall within the scope of the following claims and their equivalents.
9
Claims (12)
1. A method for etching tantalum oxide, the method comprising the steps of. providing a semiconductor substrate and then sequentially forming a first conductive structure, a dielectric layer and a second conductive layer over the substrate; performing photolithographic and etching operations, wherein patterning of the second conductive layer is achieved by using a first reactive gas that contains boron trichloride (BC13), and performing photolithographic and etching operations, wherein patterning of the dielectric layer is achieved by using a second reactive gas that contains boron trichloride (BC13).
2. The method of claim 1, wherein the step of forming the dielectric layer includes depositing tantalum oxide (Ta,O,).
3. The method of claim 1, wherein the step of forming the second conductive layer includes depositing. polysilicon.
4. The method of claim 1, wherein the flow rate of gaseous boron trichloride (BC13) in the first reactive gas is about 20 to 80 sccm.
5. The method of claim 1, wherein the first reactive gas further includes chlorine (Cl.), and the flow rate of gaseous chlorine is about 20 to 80 sccm.
6. The method of claim 1, wherein the first reactive gas further includes nitrogen (N.), and the flow rate of gaseous nitrogen is about 20 to 80 sccrn.
7. The method of claim 1, wherein the first reactive gas includes a gaseous mixture of boron trichloride, chlorine and nitrogen BQ/C1,1N, 1 0
8. The method of claim 1, wherein the flow rate of gaseous boron trichloride (BQ) in the second reactive gas is about 20 to 80 scem.
9. The method of claim 1, wherein the second reactive gas further includes chlorine (Cl,), and the flow rate of gaseous chlorine is about 20 to 80 sccm.
10. The method of claim 1, wherein the second reactive gas further includes nitrogen (N,), and the flow rate of gaseous nitrogen is about 20 to 80 sccm.
11. The method of claim 1, wherein the second reactive gas includes a gaseous mixture of boron trichloride, chlorine and nitrogen BC13/C12/N2.
12. A semiconductor device substantially as hereinbefore described with reference to Figures 2 and 3 of the accompanying drawings.
12. The method of claim 1, wherein after forming the dielectric layer, further lo includes depositing a barrier layer over the dielectric layer before depositing the second conductive layer, and then the barrier layer is patterned using a reactive gaseous mixture that includes boron trichloride, chlorine and nitrogen BC13/C1, /N I_.
13. The method of claim 12, wherein the step of forming the barrier layer includes depositing titanium nitride (TiN).
14. A method for etching tantalum oxide, wherein the method is suitable for fabricating dynamic random access memory, the method comprising the steps of providing a semiconductor substrate, forming the lower electrode structure of a capacitor, and then sequentially depositing a tantalum oxide layer, a barrier layer and a conductive layer over the substrate and the lower electrode structure; performing photolithographic and etching operations, wherein patteming of the conductive layer is achieved by using a first reactive gas that contains boron trichloride (BC13), performing photolithographic and etching operations, wherein patterning of the barrier layer is achieved by using a second reactive gas that contains boron trichloride (BCI,), and performing photolithographic and etching operations, wherein patterning of the tantalum oxide (Ta,O,) layer is achieved by using a third reactive gas that contains boron trichloride (BC13).
15. The method of claim 14, wherein the step of forming the barrier layer includes depositing titanium nitride (TiN).
W 16. The method of claim 14, wherein the step of forming the conductive layer io includes depositing polysilicon.
17. The method of claim 14, wherein the flow rate of gaseous boron trichloride (BCI,) in the first reactive gas is about 20 to 80 sccm.
18. The method of claim 14, wherein the first reactive gas further includes chlorine(C12), and the flow rate of gaseous chlorine is about 20 to 80 sccm.
19. The method of claim 14, wherein the first reactive gas further includes nitro en (NJ, and the flow rate of gaseous nitrogen is about 20 to 80 sccm.
9 0 20. The method of claim 14, wherein the first reactive gas includes a gaseous mixture of boron trichloride, chlorine and nitrogen BC13/C12-IN,.
21. The method of claim 14, wherein the flow rate of gaseous boron trichloride (BCI,) in the second reactive gas is about 20 to 80 sccm.
22. The method of claim 14, wherein the second reactive gas further includes chlorine (Cl,), and the flow rate of gaseous chlorine is about 20 to 80 sccm.
23. The method of claim 14, wherein the second reactive gas further includes nitrogen (N.), and the flow rate of gaseous nitrogen is about 20 to 80 sccm.
c - 1 12 24. The method of claim 14, wherein the second reactive gas includes a gaseous mixture of boron trichloride, chlorine and nitrogen BC1,/CUN, 25. The method of claim 14, wherein the flow rate of gaseous boron trichloride (BC1) in the third reactive gas is about 20 to 80 sccm.
26. The method of claim 14, wherein the third reactive gas further includes chlorine (Cl.), and the flow rate of gaseous chlorine is about 20 to 80 sccm.
27. The method of claim 14, wherein the third reactive gas further includes nitrogen (N.), and the flow rate of gaseous nitrogen is about 20 to 80 sccm.
28. The method of claim 14, wherein the third reactive gas includes a gaseous lo mixture of boron trichloride, chlorine and nitrogen BC1,/CUN, .z) Amendments to Ille C1:11111s have been fided as 1. A rnethod of etching a structure that comprises a semiconductor substrate a condo(tive SLI-Ucture 0Verlaid by, a dielectric including a tantalum o.\.1(ic layer (1',i,k),) and a conductive laYer Of POlysilicon, the inethod comprising performIng photolithographic and etching operations 011 Z:) b both the polysilicon layer and the dielectric, making use of a reactive gas that contains boron trichlorlde (PCI..,).
2. A metliod accordin. to claim 1 the flow rate of gaseous boron triclilorldc (BC1, _) in the reactive gas 's between 20 and 80 sccm.
3. A method according to claim 1 or 2 wherein the reactive gas includes chlorine (Clj with a flow rate of between 20 and 80 sccm.
4.. A rriethod according to any preceding claim wherein the reactive gas includes nitrogen (NTJ with a flow rate of between 20 and 80 sccm.
5. A method according to any preceding claim wherein the dielectric 2.0 includes a barrier layer overlying the tantalum oxide layer, which is etched by the reactive gas.
6. A method according to claim 5 wherein the barrier layer is formed of titanium nitride (rIN).
7. A method of making a capacitor by patternng the conductive layers and the dielectric layer as claimed in any preceding claim.
A method of making a capacitor substantially as hereinbefore described with reference to Figures 2 and 3 of the accompanying drawings.
9. A method according to any preceding claim used in the making of a dynamic ILY random access memory.
10. A capacitor made by a method according to any preceding claim.
11. A dynamic random access memory made by a method according to any one of claims 1 to 9.
Priority Applications (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| GB9809657A GB2337361B (en) | 1998-05-06 | 1998-05-06 | Method of etching tantalum oxide layer |
| NL1009201A NL1009201C2 (en) | 1998-05-06 | 1998-05-19 | Method for etching a tantalum oxide layer. |
Applications Claiming Priority (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| GB9809657A GB2337361B (en) | 1998-05-06 | 1998-05-06 | Method of etching tantalum oxide layer |
| NL1009201A NL1009201C2 (en) | 1998-05-06 | 1998-05-19 | Method for etching a tantalum oxide layer. |
Publications (3)
| Publication Number | Publication Date |
|---|---|
| GB9809657D0 GB9809657D0 (en) | 1998-07-01 |
| GB2337361A true GB2337361A (en) | 1999-11-17 |
| GB2337361B GB2337361B (en) | 2000-03-29 |
Family
ID=26313600
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| GB9809657A Expired - Fee Related GB2337361B (en) | 1998-05-06 | 1998-05-06 | Method of etching tantalum oxide layer |
Country Status (2)
| Country | Link |
|---|---|
| GB (1) | GB2337361B (en) |
| NL (1) | NL1009201C2 (en) |
Citations (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS60152031A (en) * | 1984-01-20 | 1985-08-10 | Hitachi Ltd | Etching method |
| JPH05198743A (en) * | 1992-01-20 | 1993-08-06 | Mitsubishi Electric Corp | Semiconductor device |
| US5279985A (en) * | 1991-09-19 | 1994-01-18 | Nec Corporation | Semiconductor device and method of fabrication thereof |
| EP0637067A2 (en) * | 1993-06-16 | 1995-02-01 | Applied Materials, Inc. | Plasma etching using xenon |
| US5508221A (en) * | 1993-12-02 | 1996-04-16 | Nec Corporation | Method for forming capacitor element of DRAM |
| GB2313708A (en) * | 1996-05-30 | 1997-12-03 | Nec Corp | Etching aluminium alloy and titanium nitride multilayer films |
Family Cites Families (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2910382B2 (en) * | 1992-03-09 | 1999-06-23 | 日本電気株式会社 | Method for manufacturing semiconductor device |
| JPH09251983A (en) * | 1996-03-15 | 1997-09-22 | Rohm Co Ltd | Dry etching method |
-
1998
- 1998-05-06 GB GB9809657A patent/GB2337361B/en not_active Expired - Fee Related
- 1998-05-19 NL NL1009201A patent/NL1009201C2/en not_active IP Right Cessation
Patent Citations (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS60152031A (en) * | 1984-01-20 | 1985-08-10 | Hitachi Ltd | Etching method |
| US5279985A (en) * | 1991-09-19 | 1994-01-18 | Nec Corporation | Semiconductor device and method of fabrication thereof |
| JPH05198743A (en) * | 1992-01-20 | 1993-08-06 | Mitsubishi Electric Corp | Semiconductor device |
| EP0637067A2 (en) * | 1993-06-16 | 1995-02-01 | Applied Materials, Inc. | Plasma etching using xenon |
| US5508221A (en) * | 1993-12-02 | 1996-04-16 | Nec Corporation | Method for forming capacitor element of DRAM |
| GB2313708A (en) * | 1996-05-30 | 1997-12-03 | Nec Corp | Etching aluminium alloy and titanium nitride multilayer films |
Non-Patent Citations (2)
| Title |
|---|
| Patent Abstracts of Japan, Section E, Section No 318, Vol 9,p 100, 13/12/93 & JP60-152031A (HITACHI) * |
| Patent Abstracts of Japan, Section E, Section No 625, Vol 17, p 166, 18/11/93 & JP5-198743A * |
Also Published As
| Publication number | Publication date |
|---|---|
| NL1009201C2 (en) | 1999-11-22 |
| GB9809657D0 (en) | 1998-07-01 |
| GB2337361B (en) | 2000-03-29 |
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| PCNP | Patent ceased through non-payment of renewal fee |
Effective date: 20060506 |