GB2334167A

GB2334167A - Drain current control circuit for RF MOSFET amplifier

Info

Publication number: GB2334167A
Application number: GB9802571A
Authority: GB
Inventors: John Waterhouse
Original assignee: Motorola Ltd
Current assignee: Motorola Solutions UK Ltd
Priority date: 1998-02-07
Filing date: 1998-02-07
Publication date: 1999-08-11
Anticipated expiration: 2018-02-07
Also published as: GB9802571D0; GB2334167B

Abstract

The drain current ID of an earthed-source MOSFET 70 in a portable radio unit transmitter amplifier is adjusted to a desired level at the commencement of each transmission. The gate bias voltage 77 of the MOSFET rises as the capacitor C122 is charged through the resistor 118, causing the drain current to rise to the required level. When this level is reached, the comparator 100 actuates transistor 106 to disable transistor 108, which opens the switch 116, isolating the capacitor 122. The gate bias is then held on capacitor 122 throughout the transmission. Amplifier current is sensed by resistor 98. Capacitor 122 is discharged by transistor 118 when the unit enters reception mode.

Description

AMPLIFYING CIRCUIT AND METHOD FOR DETERMINING OPTIMAL BIAS VOLTAGES THEREIN Field of the Invention This invention relates to Rrmplifving circuits of electronic equipment.

The invention is applicable to, but not limited to, amplifying circuits of mobile and/or portable radio units.

Background of the invention An amplifier is an electronic circuit which accepts an electrical input and provides an electrical output such that there is a prescribed relationship between the input and output signal's. The amplifier circuit requires an amplifying device to perform the signal amplification operation. For the majority of amplification semiconductor devices, such as bipolar junction transistors, field-effect transistors (FETs) etc., the amplifying device requires specific bias voltages/currents to be applied to the device terminals' to ensure that the device operates correctly and provides the desired output signal.

One problem associated with the design of amplifier circuits is that the desired bias voltage/current varies from device to device, especially between different production batches, even when the devices are to be used for the same application. Hence, for some applications, there is a need for an adaptive bias network design, instead of a fixed bias network design, to accommodate for variations in amplifying device characteristics.

In particular, for metal-oxide semiconductor (MOS)FET applications, the bias voltage needs to be precisely arranged around the threshold voltage of the MOSFET device, to avoid excessive drain current consumption of the device, as known to those skilled in the art. There are several methods used to try to accurately bias MOSFETs to achieve very precise bias voltages on the MOSFET gate terminal. These methods involve using a fixed voltage reference, arranged to be at a higher voltage than the maximum possible threshold voltage of the MOSFET device, and a potential divider network.

One such method is to manually tune a potential divider to set the bias voltage to the MOSFET. Potential dividers are well known to those skilled in the art. An enhancement to the manual tuning process is to laser trim the resistive elements in a potential divider, where the resistance of a resistive element located in one of the arms of the potential divider is adjusted. This results in a change in the output of the potential divider network. Careful laser trimming enables a desired voltage to be set. More specifically, a value of the resistive element is selected such that it delivers a voltage that is below the lowest possible threshold voltage of the amplifying device prior to any trimming. Clearly, as the resistive element is trimmed, its resistance, together with the voltage across the resistive element, increases. The trimming process is complete when the gate bias voltage has reached a desired voltage level, with the optimal bias point being determined by measuring the drain current of the amplifying device. The accuracy in setting the gate bias voltage is dictated by the accuracy of the trimming process.

A problem associated with using a laser trimming process is "overshoot", which results in excessive trimming of the resistive element and hence, a non-optimal gate bias voltage setting. Laser trimming stations are also very expensive and hence, are not usable in 'the field' for repairing or replacing amplifier devices and circuits. Consequently board swapping or radio unit exchanging is currently a more expedient solution for the repair of a faulty amplification circuit.

A further known method for accurately setting bias voltages is described in UK Patent Application 9510666.2. The circuit used for setting such bias voltages is shown in FIG. 1. In FIG. 1, an amplifying circuit 10 comprises an amplifying device 11 e.g. a metal oxide semiconductor fieldeffect transistor (MOSFET), having drain (D), gate (G) and source (S) terminals. A voltage 18 is supplied to the drain terminal of the amplifying device 11 via a shunt resistor 16 and a radio frequency (RF) choke 14. The drain terminal of the amplifying device 11 is also connected to an output port via an output matching circuit 12. The amplifying device 11 receives an input signal onto its gate terminal via an input matching circuit 22 and a direct current (dc) blocking capacitor 20. Bias voltage is also input to the gate terminal via the bias voltage input 24. The source terminal of the amplifying device 11 is connected to a zero dc voltage point (earth). The supply voltage at the input of the shunt resistor 16 and the voltage at the output of the shunt resistor 16 are connected to the input of a dc amplifier 34 via paths 26 and 28. The dc amplifier 34 has a supply voltage 30 and is connected to earth via path 32. The dc amplifier output 36 is input to an analog-to-digital converter (ADC) 38, which is operably coupled to a processing device 40, e.g. a microprocessor, and a digital-to-analog converter (DAC) 42. The processing device 40 is connected to a memory unit 46, containing random access memory (RAM) and read only memory (ROM) facilities, and an electronically erasable programmable read only memory (EEPROM) 44, used as a codeplug personality for the processing device 40.

The DAC output is operably coupled to the bias voltage input 24 of the amplifying device 11.

In operation, the amplifying device 11 is activated by the application of a supply voltage 18 and the operating mode of the amplifying device 11 is determined by the bias voltage input 24, which sets a bias voltage at the input of the amplifying device 11. A current sensing means comprises the shunt resistor 16, operably coupled to the direct current supply of the amplifying device 11, to provide a first signal representative of the direct current supplied to the amplifying device 11. The current sensing means further comprises the dc amplifier 34 for providing an amplified first signal to the analog-to-digital converter 38. In this manner the current sensing means measures the direct current (drain current (ID)) supplied to the amplifying device 11. The drain current (ID) drawn by the amplifying device 11 is proportional to the voltage drop across the shunt resistor 16. This voltage drop is input to the dc amplifier 34, of gain 'g', to provide an input voltage rVADC' (first signal) to the analog-to-digital converter (ADC) 38 which is representative of the shunt voltage 'Vshunt' multiplied by the gain 'g' of the dc amplifier 34, e.g. VADC = g* Vshunt. The gain 'g' of the dc amplifier 34 is chosen for best operating conditions of the ADC 38. The ADC 38 is operably coupled to the current sensing means for digitizing the first signal from the current sensing means to provide a digitized first signal. The processing device 40 processes the digitized first signal, to determine the drain current drawn by the amplifying device 11, and provides a digital bias voltage control signal to a digital-to-analog converter (DAC) 42. The DAC 42 converts the digital bias voltage control signal to an analog bias voltage control signal which controls the bias voltage at the input of the amplifying device.

A problem associated with using such a DAC tuning process is that the circuit requires a microprocessor, thereby adding complexity and current drain to the design. In addition, software is required to be written to perform the tuning function and special arrangements need to be made in the factory to perform the tuning operation during manufacture, thereby increasing the manufacturing time. For lower and mid-tier radio products, this additional complexity and cost is undesirable.

Thus, it is desirable to have an accurately biased amplifying circuit with a method of optimally setting the gate bias voltage. It would also be beneficial to have an arrangement for continually optimising the gate bias voltage settings, without having to make special tuning operations in the factory.

Summarv of the Invention In a first aspect of the present invention, an amplifying circuit is provided comprising an amplifying device having an input, an output and a direct current supply for providing direct current to the amplifying device. A bias voltage input for setting a bias voltage at the input of the amplifying device is applied and current sensing means are provided for measuring the direct current supplied to the amplifying device and for providing a first signal representative of the supplied direct current. Sample and hold means are operably coupled to the current sensing means for interpreting the direct current supplied to the amplifying device and adjusting the bias voltage at the input of the amplifying device in response thereto.

In this manner, an optimal bias voltage of the amplifying device is advantageously controlled according to the direct current supplied to the amplifying device. In the preferred embodiment of the invention, with regard to its use in a portable radio application, the initiation of the bias voltage setting process commences with depression of the PrIT button in a request to talk. Hence, advantageously, the optimal bias voltage is set on each depression of the PTT, thereby ensuring that whenever the transmitter amplifier is used the bias voltage is optimised.

Preferably the amplifying circuit also includes switching means operably coupled to the current sensing means and the sample and hold means for selectively enabling the adjustment of the bias voltage at the input of the amplifying device in response to the current sensing means. In the preferred embodiment of the invention, the current sensing means comprises a shunt resistor, operably coupled to the direct current supply of the amplifying device for providing a signal representative of the direct current supplied to the amplifying device, and a direct current amplifier for providing an amplified direct current level signal to a comparator circuit. The direct current supplied to the amplifying device is thereby translated into a voltage value and compared with a predetermined threshold value to determine whether the optimum gate bias voltage has been reached.

In this manner, the level of direct current supplied to the amplifying device is maintained in an inexpensive manner, requiring much less complex circuitry and tuning operations than contemporary solutions.

In a second aspect of the present invention, a method of determining optimal bias voltages for an amplifying circuit is provided. The amplifying circuit includes an amplifying device with input and output ports, a direct current supply to the amplifying device which is operably coupled to a current sensing means and a sample and hold function. The method includes the steps of measuring direct current supplied to the amplifying circuit by the current sensing means, providing a signal, indicative of the direct current supplied to the amplifying circuit, to the sample and hold function, and adjusting, by the sample and hold function, the voltage input to the amplifying device until a required bias voltage is reached.

In this manner, the known bias voltage input to the amplifying device is compared to the direct current supplied to the amplifying device and adjusted accordingly. Advantageously, an optimal setting for the bias voltage of each and every amplifying device, independent of the varying operational characteristics of the amplifying devices, are obtained.

Preferably the method further includes the step of comparing the direct current supplied to the amplifying device to a predetermined threshold voltage to determine when the required bias voltage is reached. In the preferred embodiment of the invention the method also includes the steps of disabling the sample function when the required bias voltage is reached, and enabling the hold function to maintain the bias voltage to the amplifying device.

A preferred embodiment of the invention will now be described, by way of example only, with reference to the drawings.

Brief Description of the Drawings FIG. 1 is a block diagram of a prior art amplifying circuit.

FIG. 2 is a block diagram of an amplifying circuit, according to a preferred embodiment of the invention.

FIG. 3 is a flowchart describing a method for determining optimal bias voltages in accordance with the preferred embodiment of the invention.

Detailed Descnption of the Drawings Referring first to FIG. 2, a block diagram of an amplifying circuit 60 according to a preferred embodiment of the invention is shown. The preferred embodiment of the invention is described with reference to its operation in a radio transceiver unit. The amplifying circuit 60 includes a radio frequency (RF) circuit 62 having an amplifying device 70. The amplifying device 70 is preferably a metal oxide semiconductor field-effect transistor (MOSFET), having drain (D), gate (G) and source (S) terminals.

The amplifying circuit 60 further includes a sensing circuit 64 operably coupled to the RF circuit 62 for sensing a drain current supplied to the RF circuit 62. The sensing circuit 64 is operably coupled to a reference circuit 66. The reference circuit 66 is operably coupled to the sample and hold circuit 68, which in turn is operably coupled to the RF circuit 62 for setting the gate voltage of the amplifying device 70.

The RF input 72 fed to the RF circuit 70 is preferably controlled, to ensure that it is turned off during the tuning process. Capacitors 74 and 78, together with inductor 76 form a matching circuit to match the RF input 72 to the gate port of the amplifying device 70. The drain port 79 of the amplifying device 70 is connected to an inductor 80 and capacitors 82 and 84 to form a matching circuit between the amplifying device 70 and RF output signal 86. The RF output is connected to an antenna switch and antenna (not shown). The drain port 79 is also connected to choke 88 and capacitor 90 to provide RF decoupling from the supply control, in addition to providing a drain current supply.

The drain current supply is provided by the sensing circuit 64. The sensing circuit 64 includes a sense resistor 98. The voltage drop across the sense resistor 98 equates to the current being supplied to the drain port of the amplifying device 70. As the voltage is relatively small in the preferred embodiment of the invention, the voltage measured across the sense resistor 98 is amplified by the sub-amplifier circuit including dc amplifier 92 and resistors 94, 96. The amplified, measured voltage is fed to the reference circuit 66, where the voltage is compared by the comparator 100, to the voltage set by the potential divider, formed by resistors 102 and 104.

The output from the comparator 100 is input to the sample and hold circuitry 68 which includes switching FETs 106, 108. The second switching FET 108 is also biased by a transmit (TX) input signal 112, via a resistor 110.

The drain port of the second switching FET 108 is controlled by an input signal SWB 114 via a resistor 118. The drain port of the second switching FET 108 is also connected to the sample and hold element 116, fed by the TX input signal 112 via resistor 118, The output of the sample and hold element 116 is input via a storage function comprising storage capacitor 122 to the input of the amplifying device 70. The output of the sample and hold element 116 is also biased by a receive (RX) signal 124, via FET 118 and resistor 116.

The operation of the amplif yin circuit is described with reference to its use in a portable radio unit. The portable radio unit typically uses a Press-To-Talk (PTT) switch whenever a user wishes to transmit. The operation of this circuit is preferably initiated whenever the Per is depressed. In operation, the ampliteying device 70 in the circuit of FIG. 2 requires a certain gate voltage to set the drain current at the correct level, e.g. 50-300 mA dependent upon the device. Transistor manufacturers typically specify a wide range of possible gate voltage values, e.g. 1.5V - 3.5V, at which the recommended amount of drain current flows. Hence, the need for associated circuitry to operate the device in an acceptable manner, across the operating range of the amplif yin device 70. A stable performance from the amplifying device is required, thereby requiring the gate voltage to be accurately set for a variety of ampiiirmg devices, across a number of batches, to ensure a steady dc drain current. The stable performance of the amplifying device 70 is also required across temperature and battery variations of the radio unit. The present invention performs this stabilising effect in the following manner. The drain current supplied to the amplifying device is sensed by the current sensing circuit 64. The drain current is equivalent to the drop in voltage across the sense resistor 98 and this small voltage is then amplified by dc amplifier 92 and compared with a predetermined threshold voltage at comparator 100. As the amplifying device 70 is turned "on" and increases its amplifying capability, the corresponding drain current increases. This causes the equivalent voltage drop to increase until the predetermined threshold voltage value is reached.

When the predetermined threshold value is reached, the comparator output causes the FET switch 106 to turn "on", thereby stopping FET switch 108 conducting. Once the FET switch 108 stops conducting the sample and hold function 116 opens, thereby enabling the storage capacitor 122 to maintain the required gate voltage input to the amplifying device 70, via resistor 121, at the desired value.

When the user releases the PRINT switch, thereby entering a receive mode of the radio, the voltage stored by storage capacitor 122 needs to be discharged. This causes the gate voltage to reduce to zero volts, in turn removing any drain current requirement of the amplifying device 70. The TX input 112 is set to zero volts in receive mode, thereby turning "off" the operation of the sample and hold function 116. The radio unit remains in the receive mode until the PTT switch is depressed and the amplifying device 70 is turned "on" again.

Preferably, the circuit is included within one die of an integrated circuit (IC), thereby providing a substantially self-contained, "self-biasing" amplifying device, with minimal external components.

Advantageously the bias voltage of the amplifying device 70 is continually optimised on every depression of the PTT switch. There is no need to incorporate microprocessor functionality and associated software programming to ensure the desired gate voltage is set. Furthermore, there is no need for any special tuning operation to be performed in the factory to ensure such desired gate voltages are achieved, as the voltages are beneficially automatically set at the beginning of each transmission, according to the prevalent conditions with respect to temperature, battery voltage etc. at the time. Also, as this is an improved and simpler method over the DAC solution of the prior art, no "digital" or digital/analogue conversion circuitry is required. In addition, with the continued development of integrated circuits (ICs), most of the described circuitry can be incorporated within such ICs at minimal additional cost.

Issues such as transient transmitter response, e.g. cyclic keying, will not be any different to conventional configurations as the circuit dc conditions have been settled before the RF input is applied to the amplifying device 70.

This continual optimisation is accomplished by using the sample and hold circuit as described with reference to FIG. 2. The present invention is particularly useful for RF power amplifying devices with high input impedances, for example MOSFETs, vertical MOS devices (VMOS) or lateral diffused MOSFETS (LDMOS). Such RF power transistors need accurate biasing of the gate voltage to ensure that the RF input voltage is at the correct level to yield good RF gain.

Glossary: SWB+ = switched battery supply that is at the battery voltage in both transmit and receive mode; + 5V TX = this is a 5 volt rail that is only at 5 volt when the radio is in transmit mode; + 5V RX = this is a 5 volt rail that is only at 5 volt when the radio is in receive mode; RF IN = this is the RF signal input from the previous stage; Sense resistor 98 = small value, high current resistor, typically < 1 ohm; and Storage capacitor = typical value is about luF.

Referring now to FIG. 3, a flowchart describing the method for determining optimal bias voltages for an amplifying circuit, as shown in FIG.

2 is shown. The process is initiated upon depression of PRINT, as shown in step 200. The transmit voltage is turned on, as in step 202, thereby turning transistor 108 "on" and into a conducting mode, as shown in step 204. The sample and hold gate 116 conducts, as shown in step 206 and the voltage across storage capacitor 122 increases, thereby increasing the gate voltage applied to the MOSFET amplifying device 70, as in step 208. As the gate voltage increases, the drain current through the MOSFET amplifying device 70 increases, as shown in step 210, the voltage across the sense resistor 98 increases, as in step 212 and the output voltage of the dc amplifier 92 increases, as shown in step 214.

The output voltage from the dc amplifier 92 is compared to the predetermined threshold voltage by the comparator 100, as shown in step 216. If the output voltage from the dc amplifier 92 is less than the predetermined threshold voltage, transistor 106 does not conduct, as shown in step 218 and the increasing gate bias voltage process continues from step 204. If the output voltage from the dc amplifier 92 is greater than the predetermined threshold voltage, switching transistor 106 does conduct, as in step 220, which stops switching transistor 108 conducting, as shown in step 222. The sample and hold gate 108 is consequently turned "off" and no longer conducts, as in step 224 and RF input is applied at port 72, as shown in step 226. The desired gate bias voltage is then maintained by the storage capacitor 122, until the PTT is released in step 228. At this time, the radio enters a receive mode of operation and RF input at port 72 is discontinued, as shown in step 230. At this time, the transmit supply signal 112 is turned "off" and the receive supply signal 124 is turned "on", as in step 234.

Consequently, transistor 108 stops conducting, as in step 236, and the sample and hold gate turns "off', as shown in step 238. Switching transistor 118 is also then turned "on", as in step 240, thereby discharging capacitor 120 via resistor 116. The gate voltage at the MOSFET amplifying device 70, is then reduced to zero volts, as shown in step 242. Consequently the drain current to the MOSFET amplifying device 70 is reduced, as shown in step 244, and the voltage across the sense resistor 98 goes low, as in step 246. This causes the voltage applied to transistor 106 to go low, as in step 248, thereby causing the switching transistor 106 to stop conducting, as shown in step 250.

The circuitry and process then remain in this state until the PIT is depressed again, as in step 252.

It is within the contemplation of the invention that alternative circuit arrangements and details can be used to perform the same operation, for example alternative sensing, comparator and switching arrangements.

Furthermore, it is within the contemplation of the invention that alternative means can be used to initiate operation of the circuit, for example voice operated circuitry as compared to PTT operation. For high accuracy situations or where speed to set the optimal bias voltage is imperative, it is possible to combine the presnt invtention with the prior art, factory tuning process. This would enable the factory tuning process to provide a rough guide to the optimal setting and then the present invention can be used for fine tuning the rough value dependent upon the prevailing conditions of the equipment, for example temperature and battery levels of the radio. In addition, it is within the contemplation of the invention that it is not limited to a transceiver radio operation, requiring separate transmit and receive modes of operation.

Thus an accurately biased amplifying circuit with a method of optimally setting the gate bias voltage is provided.

Claims

Claims 1. An amplifying circuit comprising: an amplifying device having an input, an output and a direct current supply for providing direct current to the amplifying device, a bias voltage input for setting a bias voltage at the input of the amplifying device, current sensing means for measuring the direct current supplied to the amplifying device and providing a first signal representative of the supplied direct current, and sample and hold means operably coupled to the current sensing means for interpreting the direct current supplied to the amplifying device and adjusting the bias voltage at the input of the amplifying device in response thereto.
2. An amplifying circuit according to claim 1, further comprising switching means operably coupled to the current sensing means and the sample and hold means for selectively enabling the adjustment of the bias voltage at the input of the amplifying device in response to the current sensing means.
3. An amplifying circuit according to claim 2, wherein the switching means comprises comparator means operably coupled to the current sensing means for comparing the first signal with a predetermined threshold level and enabling the adjustment of the bias voltage at the input of the amplifying device in response thereto,
4. An amplifying circuit according to claims 1, 2 or 3, wherein the current sensing means comprises: a shunt resistor operably coupled to the direct current supply of the amplifying device for providing the first signal representative of the direct current supplied to the amplifying device, and a direct current amplifier for providing an amplified first signal to the sample and hold means.
5. An amplifying circuit according to any one of the preceding claims wherein the amplifying device is a field-effect transistor having an input, an output, a direct current supply for providing direct current to the field-effect transistor, and a bias voltage input operably coupled to the sensing means for adjusting the bias voltage at the input of the field-effect transistor.
6. A method of determining optimal bias voltages for an amplifying circuit having an amplifying device with input and output ports, a direct current supply to the amplifying device which is operably coupled to a current sensing means and a sample and hold function, the method comprising the steps of: measuring direct current supplied to the amplifying circuit by the current sensing means, providing a signal, indicative of the direct current supplied to the amplifying circuit, to the sample and hold function, and adjusting, by the sample and hold function, the voltage input to the amplifying device until a required bias voltage is reached.
7. The method of claim 6, wherein the step of measuring the direct current supplied to the amplifying device by the current sensing means, further comprises the step of: comparing, the direct current supplied to the amplifying device to a predetermined threshold voltage to determine when the required bias voltage is reached.
8. The method of claims 6 or 7 further comprising the steps of: disabling the sample function when the required bias voltage is reached, and enabling the hold function to maintain the bias voltage to the amplifying device.