GB2332995A

GB2332995A - CMOS and NMOS output drivers with programmable drive capability

Info

Publication number: GB2332995A
Application number: GB9827722A
Authority: GB
Inventors: Sang-Jae Rhee
Original assignee: Samsung Electronics Co Ltd
Current assignee: Samsung Electronics Co Ltd
Priority date: 1997-12-30
Filing date: 1998-12-16
Publication date: 1999-07-07
Anticipated expiration: 2018-12-16
Also published as: FR2773286B1; GB2332995B; GB9827722D0; DE19856690A1; FR2773286A1

Abstract

A data output driver 405 for a memory IC comprises a number of component driver circuits (figures 5 and 6) connected to an output line and enabled or disabled by control signals MRS1-MRS4 to increase or decrease drive capability. The output drive control signals MRS1-MRS4 may be dependent on address signals A1-A4.

Description

2332995 OUTPUT DRIVER CIRCUITS HAVING PROGRAMAIABLE PULL-UP AND PULL-DOWN

CAPABILITY FOR DRIVING VARIABLE LOADS The present invention relates to integrated circuit devices, and more particularly to integrated circuit devices having output driver circuits therein.

Integrated circuit devices may contain specialized output driver circuits for driving external devices when the loads associated with the external devices are appreciable. Referring now to FIG. 1, an integrated circuit device may also be provided having a plurality of memory modules Ill, 113, 115 and 117 therein which are electrically coupled to a data bus (DATA), a command bus (CMD) and a chip select (CS) signal line. Each memory module may itself be comprised of a plurality of memory devices 101, 103, 105 and 107. As will be understood by those skilled in the art, an increase in the number of memory modules on an integrated circuit system board may lead to unbalanced loading on the memory modules. Such unbalanced loading may be caused by the unequal lengths in the signal lines connected to the modules and may result in clock skew which limits high frequency performance.

FIG. 2 illustrates a conventional output driver circuit which comprises a PMOS pull-up transistor P1 and an NMOS pull-down transistor NI, connected as illustrated. As will be understood by those skilled in the art, application of logic 0 signals as DOKP and DOKN to the gates of the PMOS pull-up transistor PI and NMOS pull-down transistor NI will cause the output DOUT to be pulled to WC.

1 is Similarly, application of logic 1 signals as DW and DOKN to the gates of the PMOS pull-up transistor P1 and NMOS pull-down transistor N1 will cause the output DOUT to be pulled to VSS. Finally, simultaneous application of a logic 1 signal as DOKI? to the gate of the PMOS pull-up transistor P1 and a logic 0 signal as DOKN to the gate of the NMOS pulldown transistor NI will cause the output DOUT to float in a high impedance state.

FIG. 3 illustrates another conventional output driver circuit which comprises an NMOS pull-up transistor N2 and an NMOS pull-down transistor N3, connected as illustrated. As will be understood by those skilled in the art, application of logic 1 and logic 0 signals as DOKP and DOKN, respectively, will cause the output DOUT to be pulled to WC. Similarly, application of logic 0 and logic 1 signals as DW and DOKN, respectively, will cause the output DOUT to be pulled to VSS. Finally, simultaneous application of logic 0 signals as DOKP and DOKN will cause the output DOUT to float in a high impedance state.

Unfortunately, the driving capability of the circuits of FIG. 2 and 3, which is a function of the sizes of the pull-up and pull-down transistors, is fixed and typically cannot be varied in response to dynamic or static variations in loading. Thus, notwithstanding these conventional driver circuits, there continues to be a need for improved driver circuits which account for variations in loading.

2 is According to a first aspect of the present invention, a programmable output driver circuit comprises:

first and second control signal lines; a first pull -up/pull-down driver circuit, said first pull -up/pull -down driver circuit having first and second data inputs, a first control input electrically coupled to said first control signal line, a second control input and an output; and, a second pull-up/pull-down driver circuit, said second pull-up/pulldown driver circuit having first and second data inputs electrically coupled to the first and second data inputs of said first pull-up/pull-down driver circuit, respectively, a first control input electrically coupled to said second control signal line, a second control input and an output electrically coupled to the output of said first pull-up/pulldown driver circuit.

Preferably, first and second complementary control signals lines (e.g., MRS 1, MRS 2) are also provided and the second control inputs of the first pull -up/pul 1-down driver circuit and second pull-up/pull-down driver circuit are electrically coupled to the first and second complementary control signal lines, respectively. These control signal lines and complementary control signal lines can be used to control the number of driver circuits that are active within the output driver, based on loading conditions.

Preferably, the first and second pull-up/pull-down driver circuits each comprise first and second PMOS transistors and first and second NMOS transistors. In particular, the first and second NMOS transistors of the first pull-up/pull-down driver circuit have respective gate electrodes which correspond to the first data input and the first 3 control input, respectively, and the first and second PMOS transistors of the first pullup/pull-down driver circuit have respective gate electrodes which correspond to the second data input and the second control input, respectively. Alternatively, the is plurality of pull-up/pull-down driver circuits may each comprise four MOS transistors of the same type electrically connected in series between first and second supply signal lines (e.g., VCC and VSS).

According to a second aspect of the present invention, an integrated circuit memory device comprises: a memory cell array electrically coupled to a pair of differential data lines; an output buffer having first and second inputs electrically coupled to the pair of differential data lines; a plurality of pairs of differential control signal lines; and, a programmable output driver having first and second data inputs electrically coupled to at'least one output of said output buffer and a plurality of pairs of differential control inputs electrically coupled to said plurality of pairs of differential control signal lines.

Preferably, a controller is provided which generates a first pair of complementary control signals on the first control signal line and the first complementary control signal line and generates a second pair of complementary control signals on the second control signal line and the second complementary control signal line, in response to command signals and an address. If the preferred driver circuit is used 4 is in an integrated circuit memory device, a memory array may also be provided which is electrically coupled to a pair of differential data lines and a data buffer may be provided which has first and second inputs electrically coupled to the pair of differential data lines and first and second outputs electrically coupled to the first and second data inputs of the first pul I-up/pull -down driver circuit.

Examples of the present invention will now be described in detail with reference to the accompanying drawings, in which:

FIG. 1 is a block diagram of a system board containing a memory module array therein, according to the prior art;

FIG. 2 is an electrical schematic of an output driver circuit according to the prior art; FIG. 3 is an electrical schematic of another output driver circuit according to the prior art;

FIG. 4 is a block diagram of a preferred memory device according to an embodiment of the present invention, FIG. 5 is an electrical schematic of the programmable output driver of FIG. 4, according to a first embodiment of the present invention; FIG. 6 is an electrical schematic of the programmable output driver of FIG. 4, according to a second embodiment of the present invention; FIG. 7 is a block diagram of the controller of FIG. 4; FIG. 8 is an electrical schematic of an embodiment of the control signal generator of FIG. 7; and, FIG. 9 is a timing diagram which illustrates operation of the controller of FIG. 7.

is Referring now to FIG. 4, a preferred memory device includes a memory cell array block 401, a data output buffer 403, a programmable output driver 405 (which is coupled to an output pad DOUT) and an output driver controller 407. The data output buffer 403 receives differential output data from the memory cell array block 401 via complementary data buses DB and DB, and generates first and second output signals DOKP and DOKN. The programmable output driver 405 has a driving capability which can be varied in response to a plurality of control signals MRS I /M R S 1 MRS41M R S 4 and in response to the first and second output signals DOKP and DOKN. The output driver controller 407 is also provided to generate the plurality of control signals MRS I/MRS 1 - MRS4/MRS 4, in response to command signals (CMD) and address signals Al.-A4. These command signals include a row address strobe signal RAS, a column address strobe signal CAT and a write enable signal WE.

In particular, the driving capability of the preferred output driver 405 can be programmed when the command signals RA S, CA S and WE are properly activated, the addresses AI-A4 are applied and the plurality of control signals MRS1/MRS 1 MRS4/MRS 4 are generated. These control signals are generated at respective complementary levels based on the values of the addresses Al-A4, as described more fully hereinbelow with respect to FIGS. 7-8.

Accordingly, when a system board includes a plurality of modules and each module includes a plurality of semiconductor memory devices, as illustrated by FIG. 1, the 6 size of the output driver for each memory device can be selectively programmed to account for different loading conditions associated with each device and module. Thus, the skew between signals generated by memory devices within modules at different positions within a system board can be efficiently reduced.

is The structure and operation of preferred programmable output driver circuits 405 will now be described with reference to FIGS. 5-6. Referring specifically to FIG. 5, the programmable output driver circuit 405 according to a first embodiment includes four output driving units 501, 503, 505 and 507 for driving an output pad DOUT in response to first and second output signals DOKP and DOKN. Each of the output driving units 501, 503, 505 and 507 is independently controlled by corresponding control signals MRS I/MRS 1 - MRS4/MRS 4. The number of programmable output driving units can be adjusted depending upon application. Each of the output driving units 501, 503, 505 and 507 includes: (i) PMOS switch transistors 501a, 503a, 505a and 507a (each of which has a source to which a power supply voltage VCC is applied and a gate to which a corresponding inverted control signal, one of MRS I MRS 4, is applied); (ii) PMOS pull-up transistors 501b, 503b, 505b and 507b (each of which has a source connected to a respective drain of a PMOS switch transistor, a gate to which the first output signal DOKP is applied and a drain connected to the pad DOUT); (iii) NMOS pull-down transistors 501c, 503c, 505c and 507c (each of which has a drain connected to the pad DOUT and a gate to which the second output signal DOKN is applied); and (iv) NMOS switch transistors 501d, 503d, 505d and 507d (each of which has a drain connected to source of a respective NMOS pull-down 7 transistor, a gate to which a corresponding control signal, one of MRS1- MRS4, is applied and a source to which a ground voltage VSS is applied).

is Based on this configuration of driving units, the effective size of the output driver 405 can be controlled by selectively turning on or off the PMOS switch transistors 501a, 503a, 505a and 507a (which are controlled by the inverted control signals MRS 1 MRS 4) and turning on or off the corresponding NMOS switch transistors 501d, 503d, 505d and 507d controlled by the control signals MRSI.-MRS4. For example, when the control signals MRS1-MRS4 are set to the PMOS switch transistors 501a, 503a, 505a and 507a and the NMOS switch transistors 501d, 503d, 505d and 507d of the output driving units 501, 503, 505 and 507 are all turned on.

This means the driving units 501, 503, 505 and 507 all drive the output pad DOUT in parallel in response to the first and second output signals DOKP and DOKN.

However, when the control signals MRS1-MRS4 are set to (0,0,0,1), the PMOS switch transistors 501a, 503a and 505a and the NMOS switch transistors 501d, 503d and 505d of the output driving units 501, 503 and 505 are turned off, and the PMOS switch transistor 507a and the NMOS switch transistor 507d of the output driving unit 507 are turned on. Accordingly, only a single driving unit 507 drives the output pad DOUT in response to the first and second output signals DOKP and DOKN. Finally, when the control signals MRS I -MRS4 are set to (0,0,0,0), no output drive capability is provided.

8 is To address this limitation of the driver of FIG. 5 when the control signals MRS1MRS4 are set to (0,0,0,0), an additional driving unit can be added which is not responsive to the control signals. In particular, the programmable output driver circuit 405 of FIG. 6 includes an additional driving unit 609 which is responsive to the first and second output signals DOU and DOKN and provides output drive. capability even if the control signals MRS1-MRS4 are set to (0,0,0,0).

Referring specifically to FIG. 6, the programmable output driver circuit 405 according to a second embodiment includes five output driving units 601, 603, 605, 607 and 609 for driving an output pad DOUT in response to first and second output signals DOKP and DOKN. Each of the output driving units 601, 603, 605 and 607 is independently controlled by corresponding control signals MRSl/MRS 1 MRS4/M R S 4. Each of the output driving units 601, 603, 605 and 607 includes: (i) PMOS switch transistors 601a, 603a, 605a and 607a (each of which has a source to which a power supply voltage VCC is applied and a gate to which a corresponding inverted control signal, one of MRS 1 -MRS 4, is applied); (ii) PMOS pull-up transistors 601b, 603b, 605b and 607b (each of which has a source connected to a respective drain of a PMOS switch transistor, a gate to which the first output signal DOKP is applied and a drain connected to the pad DOUT); (iii) NMOS pull-down transistors 601c, 603c, 605c and 607c (each of which has a drain connected to the pad DOUT and a gate to which the second output signal DOKN is applied); and (iv) NMOS switch transistors 601d, 603d. 605d and 607d (each of which has a drain connected to source of a respective NMOS pull-down transistor, a gate to which a 9 is corresponding control signal, one of MRS I-MRS4, is applied and a source to which a ground voltage VSS is applied). Based on this configuration of driving units, the effective size of the output driver 405 can be controlled by selective turning on or off the PMOS switch transistors 601a, 603a, 605a and 607a (which are controlled by the inverted control signals R-ff-SI-RRS4) and turning on or off the corresponding NMOS switch transistors 601d, 603d, 605d and 607d controlled by the control signals MRS1-MRS4. For example, when the control signals MRSI-MRS4 are set to (1, 1, 1, 1), the PMOS switch transistors 601a, 603a, 605a and 607a and the NMOS switch transistors 601d, 603d, 605d and 607d of the output driving units 601, 603, 605 and 607 are all turned on. This means the driving units 601, 603, 605, 607 and 609 all drive the output pad DOUT in parallel in response to the first and second output signals DOKP and DOKN. However, when the control signals MRS1-MRS4 are set to (0,0,0, 1), the PMOS switch transistors 601a, 603a and 605a and the NMOS switch transistors 601d, 603d and 605d of the output driving units 601, 603 and 605 are turned off, and the PMOS switch transistor 607a and the NMOS switch transistor 607d of the output driving unit 607 are turned on. Accordingly, only driving units 607 and 609 drive the output pad DOUT in response to the first and second output signals DOKP and DOKN. Alternative embodiments of the above described driver circuit 405 may also be provided. For example, NMOS transistors may be substituted for the PMOS transistors 601b, 603b, 605b, 6071b and 609a of FIG. 6. In addition, if NMOS transistors are substituted for the PMOS transistors 601a, 603a, 605a and 607a of FIG. 6, the inverted control signals FAK-S1 -PRS 4 need not be generated.

is Referring now to FIGS. 7 and 9, the output driver controller 407 of FIG. 4 preferably includes a mode register set controller 701, a control signal generator 703 and an address buffer 705. The mode register set controller 701 receives a clock signal CLK and generates a mode control signal -(DMRS in response to command signals. These command signals include a row address strobe signal RAS, a column address strobe signal CAS and a write enable signal WE. The mode control signal iPMRS is activated when the command signals are appropriately activated at the time the clock signal CLK transitions from 0-1. The control signal generator 703 generates the control signals MRS1-MRS4 and the inverted control signals KITS-71-MRS4 in response to the mode control signal - :DMRS and buffered address signals ADDIADD4. As will be understood by those skilled in the art, the address buffer 705 buffers the external addresses Al-A4 which are applied.

Referring to FIGS. 8 and 9, the control signal generator 703 of FIG. 7 may include NAND gates 803a-803d and inverters 803c-8031, and reproduces each bit of the addresses ADDI-ADD4 as the control signals MRS1-MRS4 when the mode control signal -PMRS is active. Whenever the mode control signal is inactive (i.e., at a logic 0 potential), the control signals MRS1-MRS4 are set to logic 0 potentials and the inverted control signals FA-KS1-K4- RS4 are set to logic I potentials which turn off the output driver circuit 405.

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Claims

CLAIMS:

1. A programmable output driver circuit, comprising: first and second control signal lines; a first pull-up/pull-down driver circuit, said first pull -up/pul 1 -down driver circuit having first and second data inputs, a first control input electrically coupled to said first control signal line, a second control input and an output; and a second pullup/pull-down driver circuit, said second pull-up/pull-down driver circuit having first and second data inputs electrically coupled to the first and second data inputs of said first pull-up/pull-down driver circuit, respectively, a first control input electrically coupled to said second control signal line, a second control input and an output electrically coupled to the output of said first pull-up/pull-down driver circuit.

2. An output driver circuit according to claim 1, further comprising first and second complementary control signals lines; wherein the second control input of said first pull-up/pull-down driver circuit is electrically coupled to said first complementary control signal line, and wherein the second control input of said second pull-up/pulldown driver circuit is electrically coupled to said second complementary control signal line.

3. An output driver circuit according to claim 1 or 2, wherein said first and second pull-up/pull-down driver circuits each comprise first and second PMOS transistors and first and second NMOS transistors.

12 4. An output driver circuit according to any preceding claim, further comprising a third pull-up/pull-down driver circuit having first and second data inputs electrically coupled to the first and second data inputs of said first pull-up/pull-down driver circuit, respectively.

5. An output driver circuit according to any preceding claim, wherein outputs of said first, second and third pull-up/pull -down driver circuits are electrically coupled together., and wherein said third pul I- up/pull -down driver circuit comprises only a single pair of MOS transistors.

6. An output driver circuit according to claim 5, further comprising means, responsive to a plurality of command signals and an address, for generating a first pair of complementary control signals on the first control signal line and first complementary control signal line and generating a second pair of complementary control signals on the second control signal line and second complementary control signal line, wherein outputs of said first, second and third pull -up/pull-down driver circuits are electrically coupled together, and wherein said third pull-up/pull-down driver circuit is not responsive to said generating means.

7. An output driver circuit according to claim 6, wherein the command signals include a row address strobe signal, a column address strobe signal and a write enable signal.

13 8. A driver circuit according to any preceding claim, further comprising a memory array electrically coupled to a pair of differential data lines, and a data buffer having first and second inputs electrically coupled to the pair of differential data lines and first and second outputs electrically coupled to the first and second data inputs of said first pull-up/pull-down driver circuit.

9. An output driver circuit according to claim 1, wherein the first and second NMOS transistors of said first pull-up/pull-down driver circuit have respective gate electrodes which correspond to the first data input and the first control input, respectively; and wherein the first and second PMOS transistors of said first pull-up/pull-down driver circuit have respective gate electrodes which correspond to the second data input and the second control input, respectively.

10. An output driver circuit according to claim 1, wherein said first pull-up/pulldown driver circuit comprises four MOS transistors of the same type electrically connected in series between first and second supply signal lines.

An integrated circuit memory device, comprising:

a memory cell array electrically coupled to a pair of differential data lines; an output buffer having first and second inputs electrically coupled to the pair of differential data lines; a plurality of pairs of differential control signal lines., and, 14 a programmable output driver having first and second data inputs electrically coupled to at least one output of said output buffer and a plurality of pairs of differential control inputs electrically coupled to said plurality of pairs of differential control signal lines.

12. A memory device according to claim 11, wherein said programmable output driver comprises first, second and third pull-up/pull-down driver circuits having outputs electrically coupled together.

13. A memory device according to claim 12, wherein each of the first, second and third pul I-up/pul 1 -down driver circuits has a pair of inputs electrically coupled to the first and second data inputs.

14. A memory device according to claims 12 or 13, wherein each of the first, second and third pull -up/pull -down driver circuits comprises a pair of PMOS transistors and a pair of NMOS transistors.

15. A memory device according to claim 14, wherein one of the NMOS transistors in the first pull-up/pull-down driver circuit has a gate electrode electrically coupled to one of a first pair of differential control signal lines, and wherein one of the PMOS transistors in the first pull -up/pul 1-down driver circuit has a gate electrode electrically coupled to another of the first pair of differential control signal lines.

16. A memory device substantially as shown in and/or described with reference to any of Figures 4 to 6, with or without reference to Figures 7 to 9.

17. A programmable output driver circuit substantially as shown in and/or described with reference to any of Figures 4 to 6, with or without reference to Figures 7 to 9.

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