GB2332774A - Method of forming contacts to semiconductor device regions - Google Patents

Method of forming contacts to semiconductor device regions Download PDF

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Publication number
GB2332774A
GB2332774A GB9727143A GB9727143A GB2332774A GB 2332774 A GB2332774 A GB 2332774A GB 9727143 A GB9727143 A GB 9727143A GB 9727143 A GB9727143 A GB 9727143A GB 2332774 A GB2332774 A GB 2332774A
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GB
United Kingdom
Prior art keywords
layer
contact
semiconductor device
insulator
conductor
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
GB9727143A
Other versions
GB9727143D0 (en
GB2332774B (en
Inventor
James Thomson
Ian Francis Deviny
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Plessey Semiconductors Ltd
Microchip Technology Caldicot Ltd
Original Assignee
Plessey Semiconductors Ltd
Mitel Semiconductor Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Plessey Semiconductors Ltd, Mitel Semiconductor Ltd filed Critical Plessey Semiconductors Ltd
Priority to GB9727143A priority Critical patent/GB2332774B/en
Publication of GB9727143D0 publication Critical patent/GB9727143D0/en
Priority to DE19859379A priority patent/DE19859379A1/en
Publication of GB2332774A publication Critical patent/GB2332774A/en
Application granted granted Critical
Publication of GB2332774B publication Critical patent/GB2332774B/en
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

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Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/7801—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
    • H01L29/7802—Vertical DMOS transistors, i.e. VDMOS transistors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
    • H01L21/283—Deposition of conductive or insulating materials for electrodes conducting electric current
    • H01L21/285—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation
    • H01L21/28506—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers
    • H01L21/28512—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers on semiconductor bodies comprising elements of Group IV of the Periodic Table
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
    • H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
    • H01L29/42312—Gate electrodes for field effect devices
    • H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
    • H01L29/4232—Gate electrodes for field effect devices for field-effect transistors with insulated gate
    • H01L29/42372—Gate electrodes for field effect devices for field-effect transistors with insulated gate characterised by the conducting layer, e.g. the length, the sectional shape or the lay-out
    • H01L29/4238—Gate electrodes for field effect devices for field-effect transistors with insulated gate characterised by the conducting layer, e.g. the length, the sectional shape or the lay-out characterised by the surface lay-out
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/70—Bipolar devices
    • H01L29/72—Transistor-type devices, i.e. able to continuously respond to applied control signals
    • H01L29/739—Transistor-type devices, i.e. able to continuously respond to applied control signals controlled by field-effect, e.g. bipolar static induction transistors [BSIT]
    • H01L29/7393—Insulated gate bipolar mode transistors, i.e. IGBT; IGT; COMFET
    • H01L29/7395—Vertical transistors, e.g. vertical IGBT
    • H01L29/7396—Vertical transistors, e.g. vertical IGBT with a non planar surface, e.g. with a non planar gate or with a trench or recess or pillar in the surface of the emitter, base or collector region for improving current density or short circuiting the emitter and base regions
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
    • H01L29/417—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions carrying the current to be rectified, amplified or switched
    • H01L29/41725—Source or drain electrodes for field effect devices
    • H01L29/41766—Source or drain electrodes for field effect devices with at least part of the source or drain electrode having contact below the semiconductor surface, e.g. the source or drain electrode formed at least partially in a groove or with inclusions of conductor inside the semiconductor

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Ceramic Engineering (AREA)
  • Manufacturing & Machinery (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
  • Electrodes Of Semiconductors (AREA)

Abstract

An IGBT has an emitter contact 10 contacting a recessed emitter region B through insulator layer 9. The gate contact 40 extends through insulating layer 9 and insulating layer 14. The openings in insulator layer 9 for the emitter and gate contacts are formed during a first etch process step. The opening in insulator 14 for the gate contact is formed during a second etch process step. In the event of mis-alignment between the emitter contact hole formed in insulating layer 9 and the emitter recess B, short circuits between emitter contact 10 and gate layer 12 are prevented by insulator layer 14. The technique is also applicable to MOSFET and MCT devices.

Description

2332774 INSULATED GATE BIPOLAR TRANSISTOR
The present invention relates to semiconductor devices and to methods of manufacturing them and more particularly to methods of manufacturing power transistors such as IGBTs (insulated gate bipolar transistor), MOSFETs (MOS field effect transistor) or MCTs (MOS controlled thyristor), although it could be applied to other types of device which have a MOSFET content.
Due to disadvantages experienced with known planar devices, devices with recessed emitters have been developed. A process for manufacturing such devices with recessed emitters is disclosed in European Application 0 091 686 and an improved process is given in GB Application 2 303 487.
A known problem with the manufacture of such devices is the occurrence of imperfections in the definition of gate features by conventional photolithography and etch processes that lead to failure of the device by an unwanted short-circuit connection between gate and source/emitter terminals.
The present invention provides an improved method of manufacture of such devices which is tolerant of imperfections in the definition of the gate electrode. Large-area MOSFET and IGBT devices utilise an array of gate electrode and source (or emitter) contacts to create high current drive capability. The invention is particularly advantageous when applied to, but is not limited to, such large-area devices comprising an array of contacts where a few malformed or missing source/emitter contacts need not appreciably affect the operation of the device so long as no shortcircuits result.
The invention provides a method for manufacture of a semiconductor device comprising the steps of providing a semiconductor body with a defined surface, arranging a first layer of insulator on the surface, arranging a layer of conductor on the first layer of insulator, arranging a second layer of insulator on the layer of conductor, forming a pattern in the layer of conductor and a pattern in the layers of insulator, wherein the patterns are substantially identical and aligned, with each other; further comprising the step of depositing a third insulating layer on the patterned surface so formed; the method also providing a first and a second contact in the semiconductor device, wherein the first contact is completely etched and the second contact is partially etched in a first etch process; and the etching of the second contact is completed in a second etch process.
The invention also provides a semiconductor device comprising a semiconductor body with a defined surface, a first layer of insulator arranged on the surface, a layer of conductor arranged on the first insulating layer, a second layer of insulator arranged on the conducting layer, wherein each of the first and second insulating layers and the conducting layer comprise a pattern, and the patterns are substantially identical to and aligned with each other; further comprising a third insulating layer arranged on the patterned surface; wherein the device comprises a first contact etched through the third insulating layer but not through the second, and a second _contact etched through the second and the third insulating layers.
3 In a preferred embodiment, the semiconductor device is a power transistor. In a further preferred embodiment, the semiconductor device is an IGI3T.
The invention may be applied to a semiconductor body comprising a substrate or a layer formed in or on a substrate.
An embodiment of the invention will now be described by way of example with reference to the accompanying drawings in which:
Figure 1 shows a plan view of part of an IGBT device, that part comprising three source/emitter contacts and illustrating typical imperfections that can occur; Figure 2 shows a cross-sectional view of the IGBT part of Figure 1, showing the problems which can result in the prior art;
Figure 3 shows the same view as Figure 2, but showing the improvement resulting from the invention; Figures 4 to 8 show a second cross-sectional view of the IGBT device of Figure 1 in various stages of manufacture; With reference to Figure 1, three IGBT source/emitter contacts are shown in plan view. The contact of cell 1 is perfectly formed: source/emitter recess A is defilned correctly and contact area (window B) is well aligned to the centre of the recess. Contacts 2 and 3 1 4 have imperfections. Contact 2 has a misshapen recess wall A coming within the window B at Al. Contact 3 has the recess A missing completely, so that no cell is formed.
Full details of the construction of the device are given below with reference to Figures 4 to 8, but first the beneficial effect of the invention over the prior art will be discussed with reference to Figures 2 and 3.
Figure 2 shows a cross-sectional view of the integrated circuit of Figure 1 with the three recessed-source IGBT contacts 1, 2 and 3 formed according to the prior art method.
In contact 1 of Figure 2 the recess A is correctly formed by cutting through layers 12, 14 and 16 and into silicon layer 18. Insulating layer 9 provided across the surface of the device has windows B opened in it by an etch process and conductive layer 10, typically metal, is then provided to cover insulating layer 9 and to make contact with the emitter source contact areas through windows B. In contact 2 the misshapen recess wall means that gate conductor layer 12 extends too far, coming within the window B. An unwanted short circuit is thus created between the gate conductor layer 12 and overlying conductive layer 10 where the gate conductor layer 12 extends into the recess A.
In contact 3 the recess A is missing completely and, as a result, gate conductor layer 12 extends right the way across the window B. Due to the absence of a recess at contact 3, no cell structure can be formed there. The missing structure is indicated by dashed lines. Again, an unwanted short circuit is thus created between the gate conductor layer 12 and overlying conductive layer 10.
1 Figure 3 shows, by way of contrast with Figure 2, the improved results obtained by using the method of the current invention.
Figure 3 shows a cross-sectional view of the integrated circuit of Figure 1 with the three recessed-source IGBT contacts formed according to the method of the present invention. In contacts 2 and 3, even though gate conductor layer 12 extends too far, coming within the window B, a short circuit between the gate conductor layer 12 and overlying conductive layer 10 is prevented by the additional portion of insulating layer 14 covering the gate conductor layer 12.
The basic structure of the IGBT will now be described with reference to Figure 4.
The IGBT has a substrate of bulk silicon (not shown) on which is formed epitaxial silicon layer 18. The silicon substrate is provided with a metal electric contact layer (not shown) which acts as the collector for the IGBT and would act as the drain in the case of the invention being applied to a MOSFET.
The thickness of the epitaxial layer 18 depends upon the voltage drop required. In the case of a MOSFET layer 18 and the substrate are of the same type and, in the case of an, IGBT layers 18 and the substrate are of opposite type.
In this embodiment the epitaxial layer 18 is n type and the bulk silicon is p type.
The gate of the IGBT cell is formed by gate conductor layer 12 which may be 6 polysilicon overlying gate oxide layer 16 such as silicon dioxide. Gate conductor layer 12 is covered in turn by further insulating layer 14 which could be an oxide and could be thermally grown or deposited on top of the gate conductor layer 12. Insulating layer 14 must be thick enough to act as a mask during subsequent diffusion, implant and etching processes. Electrical contact to the gate conductor layer 12 is made at one or more gate contacts 34.
The source/emitter of the cell is recessed at contacts 32 by etching in a conventional manner through the gate conductor layer 12 and insulator layers 16 and 14, thus creating identical, aligned patterns in thee three layers. This technique ensures that, if errors in the etching of the recesses A lead to imperfections in the pattern of gate conductor layer 12 then the same imperfections will be created in the overlying insulating layer 14. In particular, any unwanted portions of gate conductor layer 12 extending into window B will be covered by corresponding portions of insulating layer 14.
In order to fully insulate the gate conductor layer 12 at the sidewalls of recess A, the edges of the gate conductor layer 12, exposed as a result of the etching of recess A, are passivated by the formation of insulating layer 20, typically oxide. The layer 20 may be generated by well known deposition techniques.
There is an implant/diffusion 22 formed in the epitaxial silicon layer 18. The source of the IGBT comprises the diffusion area 24 which, in this embodiment, is electrically connected to the base of the recess A and the body diffusion area 22 by a silicide layer 26. In this embodiment, a second dose of the implant 22 is indicated at 28 in 7 implant/diffusion 22 adjacent silicide layer 26.
Insulating layer 9 is formed by deposition or other conventional means on the pattemed surface formed by etching recesses A. The insulator 9, typically low temperature oxide (LTO), thereby covering the insulating layers 14 and 20 and the recesses A.
The steps for completing the manufacture of the IGBT will now be described with reference to Figures 4 to 8.
Returning to Figure 4, a resist mask 30 is formed on the surface of the insulating layer 9 so as to expose the areas B intended to form source/emitter contacts 32 and areas C (one of which is shown) intended to form gate contacts 34. A first etch is carried out to form windows in the insulating layer 9. The extent of the etch is limited by timing or using standard end point techniques so that, essentially only material from the insulating 15 layer 9 is removed.
The result of the first etch is shown in Figure 5. Here it is seen that source/emitter window B is complete, whereas the gate window C has not penetrated to the gate conductor layer 12 due to the continued presence of insulating layer 14 covering the gate conductor layer 12.
It will be clear from this figure that any imperfections in the Pattern formed in the gate conductor layer 12 by the etching of recesses A which lead to unwanted portions of the gate conductor layer extending into windows B of the contacts 32 will not result in 8 unwanted short circuits. As the first etching operation applied to the source/emitter contacts 32 is limited to only remove material from layer 9, the insulating layer 14 overlying any such imperfections in the gate conductor layer 12 will remain intact in the same way as that part of insulating layer 14 exposed at gate contact 34 is seen to remain intact following the first etch.
Figure 6 shows a second resist mask 36 formed on the surface of the insulating layer 9 and in windows B so as to only expose the areas C (one of which is shown) intended to form gate contacts 34.
A second etch is carried out using second resist mask 36 to extend windows C into the insulating layer 14 and the etching of the gate contact is thus completed. The resultant, fully etched device is shown in Figure 7.
Conductive layers 10 (for the source/emitter contacts) and layer 40 (for the gate contacts), typically aluminium metallisation, are then deposited, as shown in Figure 8.
Contact windows B, formed in the insulating layer 9, allows conductive layer 10 make contact with the base of each source/emitter contact 32. In this embodiment, the conductive layer 10 need only make contact at the centre of each source/emitter contact 32 as the silicide layer 26 is relied upon to distribute current beneath the insulating layer 9 to the source regions 24.
Contact window C, formed in the insulating layers 14 and 9, allows conductive layer 40 make to contact with the gate conductor layer 12 at gate contacts 34.
1 9 Although described above with reference to the gate conductor layer of a power transistor, the invention is not limited to such applications and the skilled practitioner in the field of semiconductor devices will readily understand how the present invention may be applied to other semiconductor devices to prevent unwanted short circuits. In particular, this invention also applies to planar devices and to the creation of conductive layers other than for use as gates.
r% 1

Claims (13)

1 Method for manufacture of a semiconductor device comprising the steps of providing a semiconductor body with a defined surface, arranging a first layer of insulator on the surface, arranging a layer of conductor on the first layer of insulator, arranging a second layer of insulator on the layer of conductor, forming a pattern in the layer of conductor and a pattern in each of the layers of insulator, wherein the pattems are substantially identical and aligned with each other; further comprising the step of depositing a third insulating layer on the patterned surface so formed; the method also providing a first and a second contact in the semiconductor device, wherein the first contact is completely etched and the second contact is partially etched in a first etch process; and the etching of the second contact is completed in a second etch process.
2.
3.
The method of Claim 1 wherein the first etch process is arranged to only remove material from the third insulating layer and the second etch process is arranged to only remove material from the second insulating layer.
The method of any above claim wherein any imperfections in the pattern created in the conducting layer are reproduced in the second insulator layer.
4. The method of any above claim wherein the patterns are formed by the step of cutting through the first and second insulating layers and the conducting layer prior to the step of depositing the third insulating layer.
11
5. The method of any above claim, wherein the step of forming the patterns exposes one or more edges of the conductor layer, including the step of forming a layer of insulator on such exposed edges of the conductor layer.
6.
The method of any one of the above claims wherein the semiconductor device is a power transistor, the first contact comprising a source or emitter contact and the second contact comprising a gate contact of the transistor.
7. The method of any above claim wherein the conductor layer forms the gate conductor layer of an insulated gate bipolar transistor QGBT).
8. A semiconductor device comprising a semiconductor body with a defined surface, a first layer of insulator arranged on the surface, a layer of conductor arranged on the first insulating layer, a second layer of insulator arranged on the conducting layer, wherein each of the first and second insulating layers and the conducting layer comprise a pattern, and the patterns are substantially identical to and aligned with each other; further comprising a third insulating layer arranged on the patterned surface; wherein the device comprises a first contact etched through the third insulating layer but not through the second, and a second contact etched through the second and the third insulating layers.
12
9. The semiconductor device of Claim 8 comprising a power transistor wherein the first contact comprises a source or emitter contact of the power transistor, and the second contact comprises a gate contact of the power transistor.
10.
The semiconductor device of any one of Claims 8 to 9 comprising an insulated gate bipolar transistor (IGBT) wherein the conductor layer forms the gate conductor layer of the IGBT.
11. The semiconductor device of any one of Claims 8 to 10 wherein any imperfection in the extent or shape of the conductor layer is reproduced in the second insulating layer arranged on said conductor layer.
12. A semiconductor device substantially as hereinbefore described as illustrated by and with reference to the diagrams.
13. A method for the manufacture of a semiconductor device substantially as hereinbefore described as illustrated by and with reference to the diagrams.
GB9727143A 1997-12-24 1997-12-24 Insulated gate bipolar transistor Expired - Fee Related GB2332774B (en)

Priority Applications (2)

Application Number Priority Date Filing Date Title
GB9727143A GB2332774B (en) 1997-12-24 1997-12-24 Insulated gate bipolar transistor
DE19859379A DE19859379A1 (en) 1997-12-24 1998-12-22 Insulating layer bipolar transistor

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
GB9727143A GB2332774B (en) 1997-12-24 1997-12-24 Insulated gate bipolar transistor

Publications (3)

Publication Number Publication Date
GB9727143D0 GB9727143D0 (en) 1998-02-25
GB2332774A true GB2332774A (en) 1999-06-30
GB2332774B GB2332774B (en) 2002-10-30

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GB9727143A Expired - Fee Related GB2332774B (en) 1997-12-24 1997-12-24 Insulated gate bipolar transistor

Country Status (2)

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DE (1) DE19859379A1 (en)
GB (1) GB2332774B (en)

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0697723A2 (en) * 1994-08-15 1996-02-21 International Business Machines Corporation A process for metallization of an insulator layer
US5578524A (en) * 1994-03-30 1996-11-26 Nec Corporation Fabrication process of a semiconductor device with a wiring structure

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5578524A (en) * 1994-03-30 1996-11-26 Nec Corporation Fabrication process of a semiconductor device with a wiring structure
EP0697723A2 (en) * 1994-08-15 1996-02-21 International Business Machines Corporation A process for metallization of an insulator layer

Also Published As

Publication number Publication date
GB9727143D0 (en) 1998-02-25
DE19859379A1 (en) 1999-07-08
GB2332774B (en) 2002-10-30

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Effective date: 20111224