GB2330957A

GB2330957A - Power supply clamp for a smartcard

Info

Publication number: GB2330957A
Application number: GB9722994A
Authority: GB
Inventors: Michael John Gay
Original assignee: Motorola Inc
Current assignee: Motorola Solutions Inc
Priority date: 1997-11-01
Filing date: 1997-11-01
Publication date: 1999-05-05
Anticipated expiration: 2017-11-01
Also published as: GB9722994D0; GB2330957B

Abstract

A personal data carrier or smartcard operating in contactless mode has a tuned circuit 22, 24 which receives a transmitted signal and develops an AC voltage at nodes 26, 28, NMOS transistors 30-36 forming a full wave rectifier having an input connected to nodes 26, 28 and a DC power supply output connected across lines 38, 40, and a clamping circuit 46-50 having a transistor 50 coupled across the AC nodes 26, 28 and controlled in response to the DC power supply voltage across lines 38, 40 to limit/regulate the DC voltage. Placing the clamping transistor 50 across the AC nodes 26, 28 instead of across lines 38, 40 avoids loading the rectifier by the transistor. Transistor 50 is controlled by a transconductance amplifier 46 which compares the DC supply voltage with a reference and has an output coupled to an integrating capacitor 48 to form a regulation loop which is relatively slow, thereby aiding recovery of data amplitude modulated on the AC signal across nodes 26, 28. Diode-configured transistors 60, 62 demodulate the data from the AC nodes 26, 28, rather than from the output of rectifier 30-36. The transistors 30-36 of the rectifier also provide electro-static discharge protection against ESD events causing node 26 or 28 to become positive or negative relative to DC supply line 38 or 40. A second regulation loop with a fast response time may additionally be provided (Fig.4) for situations where the loop 46-50 is not fast enough - eg. when a magnetic field is suddenly applied. The fast loop has a comparator (70) which responds to the DC supply voltage and controls transistors (72), (74) respectively connected between DC line 40 and AC node 28 and between line 40 and AC node 26. The fast loop is also effective when the card is in direct physical contact with a reader connected to apply a supply voltage directly to DC line 40.

Description

POWER SUPPLY CLAMP AND METHOD IN A SMARTCARD Background of the Invention The present invention relates in general to data communications and, more particularly, to a power supply clamp in a contactless personal data carrier (PDC).

In contactless data communications, a typical system comprises a PDC, commonly referred to as a smartcard or chip card, and PDC reader or data terminal. The PDC is commonly made of a polymer material, about the size of a conventional credit card, and includes an integrated circuit (IC) with control circuitry and readable and writable memory. The PDC contains information such as cardholder identification, personal data, financial data, security codes, public transit fares or other useful personal, business or administrative information.

For example, the PDC can be used to store the user's medical history. The user presents the PDC to a health care provider who, through a PDC reader, extracts the patient's medical history, including personal data, primary care physician, health insurance, allergies, medication, past procedures, blood type, religious preference, organ donor, etc. Other applications for PDCs include banking services, identification for nationality and passport, and transportation transactions such as ticket and fare collection. The PDC can be programmed to hold a monetary value. When making a purchase, the user presents the PDC to the PDC reader and the purchase amount is automatically deducted from the stored monetary value. PDCs are applicable virtually anywhere the user needs to convey or exchange data or information.

The PDC typically does not have an internal power source. To initiate a transaction with the PDC, the cardholder places the PDC in the vicinity of a data terminal or PDC reader. The PDC reader includes an inductive coil that is excited by an alternating current which transmits energy by an alternating magnetic field.

The PDC receives the magnetic field which induces a voltage across a coil in the PDC tuned to the vicinity of the frequency of the energizing signal. The alternating voltage induced across the coil is boosted by resonance, rectified and conditioned to operate as the DC power supply voltage for the PDC. The PDC and PDC reader interact to execute and complete the transaction.

The magnitude of the induced voltage increases as the PDC is brought closer to the reader. The PDC typically includes a power supply clamp to limit the level of the DC supply voltage and avoid damaging internal circuitry. A typical power supply clamp includes a full-wave rectifier diode bridge with a shunt regulator coupled across its output. A relatively small shunt capacitor filters the DC output voltage of the diode bridge. The shunt regulator limits the amplitude of the rectified signal. However, the shunt regulator conducts a constant current from the power supply even between peaks of the alternating voltage signal which increases the DC output voltage ripple. Moreover, the shunt regulator tends to respond slowly since it must operate on very low current.

To transmit data from the PDC reader to the PDC, the energizing current in the PDC reader coil is amplitude modulated with the transmitted data. The PDC must be capable of limiting the power supply voltage while preserving the received data.

Another concern with contact less data communication systems is the interaction of multiple PDCs. The cardholder may have multiple PDCs in close proximity to one another, for example, side-by-side in a wallet, purse, badge holder or briefcase. The cardholder often brings the PDCs in the vicinity of the PDC reader as a group. The PDCs are all energized by the magnetic field. Some PDCs may have different tuned coils, supply voltages and clamping circuits which by interaction of the mutual inductances and clamping thresholds tend to suppress the magnetic field and alter the resonant frequency. Such interference between adjacent PDCs is undesirable for the operation of the target PDC.

Hence, a need exists for a power supply clamp in a PDC that does not induce excessive ripple on the DC output voltage or interfere with recovery of the transmitted data.

Brief Description of the Drawings FIG. 1 is a block diagram illustrating a contact less data communication system; FIG. 2 is a block diagram illustrating the PDC; FIG. 3 is a schematic diagram illustrating the power supply block of FIG. 2; and FIG. 4 is a schematic diagram illustrating an alternate embodiment of the power supply block.

Detailed Description of the Preferred Embodiment Referring to FIG. 1, a contactless data communication system is shown including a PDC 10 and a PDC reader 12.

When PDC 10 is placed in the vicinity of PDC reader 12, information is exchanged through a contactless transaction.

The transaction can take many forms and involve many functions such as personal identification, medical records, national identification and passport. PDC 10 can store financial information such as banking information, stock portfolio, and other investments. PDC 10 can store monetary value(s) which is automatically deducted from, including any applicable foreign exchange rates, each time the user conducts a transaction such as to pay transportation fares, purchase merchandise, or access longdistance telephone services. PDC 10 can store security codes for access to restricted areas.

A typical transaction involves energizing the PDC, sending data to the PDC and receiving data from the PDC.

For example, for automatic fare debit in a public transportation system, the cardholder places PDC 10 in the vicinity (within about 10 cm) of PDC reader 12 located at the gate of the public transportation. PDC 10 is programmed with a monetary value or an authorization to debit an account. PDC reader 12 queries PDC 10 for the fare. PDC 10 acknowledges with authorization to debit the account or simply deducts the fare from the monetary value stored in its memory.

PDC 10 includes an IC with memory, I/O circuitry, and a microprocessor or other controller encased in a polymer package. PDC 10 does not have an internal power source for the IC, but rather receives operating power during the transaction from PDC reader 12. PDC reader 12 includes an inductive coil which, in one embodiment, is wound one turn with an effective inductance of about 0.5 microhenries and tuned to 13.56 MHz. The coil in PDC reader 12 is excited by an alternating current to transmit energy in an alternating magnetic field. PDC reader 12 transmits data to PDC 10 by amplitude modulating the alternating current in the coil.

Turning to FIG. 2, PDC 10 is shown with an antenna 14 implemented as an inductive coil wound four times around the perimeter of the PDC with an effective inductance of about 4 microhenries. When PDC 10 comes in vicinity of the magnetic field from PDC reader 12, an alternating voltage is induced across the coil in PDC 10. Power supply block 16 rectifies and conditions the alternating voltage to produce a DC power supply VDD as the operating potential for control circuit 18 and memory 20. Control circuit 18 provides control functions to read from or write to memory 20 based on the request from PDC reader 12. Memory 20 is typically implemented as EEPROM. Power supply block 16 also demodulates the data from PDC reader 12 for control circuit 18 and memory 20 as described below.

In FIG. 3, power supply block 16 includes inductor 22 and capacitor 24 coupled in parallel as an equivalent tuned circuit of antenna 14. Circuit 22-24 is tuned to about 19 MHz. The magnetic field induces a voltage in series with inductor 22 thereby producing an alternating sinusoidal voltage across tuned circuit 22-24 appearing at nodes 26 and 28. NMOS transistors 30, 32, 34 and 36 operate as a full-wave rectifier bridge. The bulk electrodes of transistors 30-36 are coupled to power supply conductor 38 operating at VSS (zero volts). The output of the rectifier bridge 30-36 is power supply conductor 40 operating at a DC voltage VDD which supplies power to control circuit 18 and memory 20. Capacitor 42 filters and smoothes the DC voltage on power supply conductor 40. When the voltage at node 26 is greater than node 28, then transistor 30 conducts and connects node 28 to power supply conductor 38 (VSS). Transistor 36 also conducts as a diode and produces a half-wave rectified signal at power supply conductor 40 with respect to VSS. During the portion of the cycle when the voltage at node 28 is greater than node 26, transistor 32 conducts and connects node 26 to power supply conductor 38. Transistor 34 conducts as a diode and produces a halfwave rectified signal at power supply conductor 40 with respect to VSS. The AC voltage on nodes 26 and 28 is thus full-wave rectified to produce the DC voltage on power supply conductor 40.

As one feature of the present invention, a clamping circuit is coupled across nodes 26 and 28, i.e. at the input of the rectifier bridge 30-34, and operates in response to the DC output voltage on power supply conductor 40. The clamping circuit controls the impedance of the tuned circuit to clamp or limit the amplitude of the alternating voltage and thereby limit the DC output voltage VDD. By placing the clamping circuit across the tuned circuit 22-24, the output of the rectifier is not loaded with the clamp which reduces ripple on the DC output voltage VDD.

The clamping circuit includes transconductance amplifier 46 having a non-inverting input coupled to power supply conductor 40 and an inverting input coupled for receiving a reference signal VREF operating at 3.6 volts.

The output of transconductance amplifier 46 provides a current to charge integrating capacitor 48. Capacitor 56 provides feed-forward compensation to stabilize the control loop. The voltage developed across capacitor 48 controls transistor 50 which has conduction terminals coupled across nodes 26 and 28. Capacitors 52 and 54 are coupled gatesource and gate-drain to transistor 50. Ordinarily, without capacitors 52 and 54, transistor 50 has a drainsource conduction determined by the applied gate-source voltage. In the arrangement shown in FIG. 3, transistor 50 operates as a constant current device drawing current proportional to the gate-source voltage but independent of drain-source voltage. Capacitors 52 and 54 form a voltage divider to add a portion of the drain-source voltage to the gate-source voltage. The conducting nodes of transistor 50 interchange their function according to the polarity of the voltage between them. The electrode connected to whichever of nodes 26 and 28 is positive acts as the drain while the other acts as the source. Thus, when node 28 is positive transistor 50 has negative feedback via the capacitance C52 of capacitor 52 and via a drain-source capacitance, C50.

When node 26 is positive it has negative feedback via the capacitance C54 of capacitor 54 and via a drain-source capacitance C51. The negative feedback produces an effective conductance across the tuned circuit of gm(C52+C50)/(C54+C48) when node 28 is positive, where gm is the transconductance of amplifier 46 and C48 is the value of capacitor 48. The effective capacitance across the tuned circuit is gm(C54+C51)/(C52+C48) when node 26 is positive. These conductances are preferably made equal.

Amplifier 46 monitors the DC output voltage and controls the gate of transistor 50 to provide a variable, controllable impedance across nodes 26 and 28. The clamping function is accomplished by placing a variable impedance across the tuned circuit 22-24. The variable impedance limits the amplitude of the alternating voltage signals between nodes 26 and 28. For example, assume the voltage across the tuned circuit 22-24 increases, possibly because PDC 10 is moved farther into the magnetic field, i.e. closer to PDC reader 12. The voltage at conductor 40 increases causing the output of transconductance amplifier 46 to source more current into capacitor 48. The gate voltage of transistor 50 increases which causes it to conduct more and decrease the effective impedance across nodes 26 and 28. The lower impedance modifies the tuned circuit 22-24 to decrease the alternating voltage applied to the full-wave rectifier bridge.

In a like manner, as the voltage at conductor 40 decreases the output of transconductance amplifier 46 sources less current into capacitor 48. The gate voltage of transistor 50 decreases which causes it to conduct less and increase the effective impedance across nodes 26 and 28. The higher impedance modifies the tuned circuit 22-24 to increase the alternating voltage applied to the fullwave rectifier bridge. Amplifier 46 thus regulates the DC output voltage on power supply conductor 40 to the reference voltage VREF = 3.6 volts. The time constant of the regulation loop is relatively slow and controlled by integrating capacitor 48 and the transconductance of amplifier 46. In one embodiment, the loop response time is 40 microseconds.

As shown in the forgoing description the clamp transistor 50 presents a variable conductance across the tuned circuit. Tuned circuit 22-24 has an integrating characteristic. The voltage across circuit 22-24 remains essentially sinusoidal while being adjusted by the clamp to that level which when rectified produces the desired supply voltage. The supply voltage ripple remains independent of the regulation and free of the excessive reductions between the peaks of the AC voltage waveform which tend to be produced by a clamp connected across the rectified supply.

The advantage of this modification is further apparent by considering that the clamp device may need to absorb perhaps 100 times the useful load current when the PDC is very close to the PDC reader.

As an additional feature, the slow time constant of the clamp regulation loop 46-50 aids in recovering the modulated data transmitted by PDC reader 12. There are situations where multiple PDCs are introduced as a group into the magnetic field of the PDC reader, e.g. several PDCs are adjacent to one another in a wallet, purse or briefcase. One PDC is the intended target and the other PDCs are non-targets. However, all of the PDCs will react to the magnetic field and typically all of the PDCs have power supply clamps. The power supply clamps in the nontarget PDCs, especially those with low voltage, fast response, hard clamps, will suppress the magnetic field and thereby reduce the amplitude modulation. Any suppression of the amplitude modulation interferes with the data recovery in the target PDC. A slow response voltage clamp, as provided by the present invention, has less suppression on the magnetic field and does not significantly reduce the amplitude modulation. The slow response voltage clamp in an unselected PDC reduces interference with an adjacent target PDC. Furthermore, it is advantageous to have a PDC equipped with a slow clamp in the presence of other PDCs with fast clamps, so as to not further aggravate the difficulties of demodulation.

One of the features of power supply block 16 is detection and recovery of the data which, in a preferred embodiment, is amplitude modulated by approximately +10% of the alternating current in the coil of PDC reader 12. The data is demodulated by detecting amplitude changes in PDC 10. Load 58 represents the loading of control circuit 18 and memory 20 on power supply conductor 40. The switching operation of control circuit 18 and memory 20 creates noise in the form of current spikes on power supply conductor 40.

In the prior art, the data is demodulated from the DC output voltage and therefore subject to the switching noise from load 58. It is desirable to isolate the data demodulation from the switching noise of load 58. The present invention detects the data directly from the tuning circuit 22-24. Any switching noise on power supply conductor 40 is attenuated by the diode bridge 30-36 and therefore does not appear to any significantly degree across the tuning circuit 22-24. The data appearing at nodes 26 and 28 is demodulated by diode-configured transistors 60 and 62 which full-wave rectify the alternating voltage developed across the tuning circuit 2224. Transistor 60 conducts when the voltage at node 28 is greater than the voltage at node 26. Likewise, transistor 62 conducts when the voltage at node 26 is greater than the voltage at node 28. Resistor 64 and capacitor 66 set the time constant of the rectifier 60-62. The envelope of the rectified signal is the demodulated data. Thus, the present invention allows data demodulation and recovery by directly monitoring the alternating voltage across the tuned circuit in the PDC.

An alternate embodiment of power supply block 16 is shown in FIG. 4. Components having the same reference number used in FIG. 3 provide a similar function as discussed above. The embodiment of power supply block 16 in FIG. 3 operates with a slow regulation loop 46-50. The regulation loop 46-50 performs properly in normal situations where PDC 10 is introduced into an existing magnetic field at a rate of less than 1 meter/second. In certain situations, the slow regulation loop 46-50 may not respond to rapid variations in alternating voltage across the tuning circuit 22-24. For example, if the magnetic field is suddenly applied after the PDC is in the proximity of the PDC reader, then excess voltages can develop across the tuned circuit of the PDC at a rate faster than the slow regulation loop response time.

In FIG. 4, a second regulation loop is added which has a much faster response than the regulation loop 46-50. The second regulation loop includes comparator 70 and transistors 72 and 74. The second regulation loop does not use an integrating capacitor and therefore responds very quickly to changes. Comparator 70 has a non-inverting input coupled to power supply conductor 40 and an inverting input coupled for receiving a reference voltage VREF2=6 volts. The output of comparator 70 is coupled to the gates of transistors 72 and 74.

The fast regulation loop monitors the DC output voltage VDD. The output of comparator 70 goes to a high level if the voltage on power supply conductor 40 exceeds the reference voltage VREF2. If node 28 is connected to ground via transistor 30 at the time that the output of comparator 70 goes to a high level, then transistor 72 conducts excessive current from power supply conductor 40 and thereby limits the voltage VDD. If node 26 is connected to ground via transistor 32 at the time that the output of comparator 70 goes to a high level, then transistor 74 conducts and discharges power supply conductor 40 to limit the voltage VDD. In either case, the DC output voltage VDD is limited to no more than VREF2.

The power supply clamp in FIG. 4 also supports contact mode where the PDC comes into direct physical contact with the PDC reader to receive its operating potential and transfer data. The slow regulation loop 46-50 is inoperative in contact mode because no energy is applied to tuned circuit 22-24. The fast regulation loop 70-74 operates in contact mode. Assume the voltage VDD from the external contact exceeds VREF2 and the output of comparator 70 goes to a high level. The sources of transistors 72 and 74 are not driven by the diode bridge 30-36 so they operate as source followers. With the high gate voltage on transistors 72 and 74, the voltages at nodes 26 and 28 both go to a high level. The high voltages at nodes 26 and 28 attempt to turn on transistors 30 and 32. However, transistors 30 and 32 cannot both turn on because their drains are connected to ground potential which would disable the gate voltage of the opposite transistor. One of the two transistors 30 and 32 will dominate based on device characteristics and parameters. If transistor 30 dominates, then node 28 is pulled to ground potential which allows transistor 72 to limit the DC voltage on power supply conductor 40. If transistor 32 dominates, then node 26 is pulled to ground potential which allows transistor 74 to limit the DC voltage on power supply conductor 40. It is possible that neither transistor 30 or 32 will completely dominate and the voltages at nodes 26 and 28 will settle to an intermediate value. Transistors 72 and 74 will together limit the DC voltage on power supply conductor 40.

Power supply block 16 provides electro-static discharge (ESD) protection. In an ESD event, assume a positive voltage is applied to node 26 with respect to power supply conductor 40. Transistor 36 conducts and discharges the current from the event voltage back to power supply conductor 40. If the positive voltage is applied to node 28 with respect to power supply conductor 40, transistor 34 conducts and discharges the current from the event voltage back to power supply conductor 40.

Now assume a negative voltage is applied to node 26 with respect to power supply conductor 38. Transistors 3036 are NMOS devices with n-type diffusion in the source/drain regions. The source/drain regions are formed in a p-well that is connected to VSS. There is a substrate diode formed between VSS (anode) and nodes 26 and 28 (cathode). With the more positive voltage on power supply conductor 38, the substrate diode of transistors 32 and 36 conduct and discharge the current from the event voltage back to node 26. If a negative voltage is applied to node 28 with respect to power supply conductor 38, the substrate diode of transistors 30 and 34 conduct and discharge the current from the event voltage back to node 28.

In another type of ESD event, a negative voltage is applied to node 26 with respect to power supply conductor 40. The voltage on power supply conductor 40 being greater than VREF2 triggers comparator 70 and turns on transistor 74 to discharge the current from the event voltage back to node 26. A small portion of the current flows through the substrate diodes of transistors 32 and 36. If the negative voltage is applied to node 28 with respect to power supply conductor 40, then comparator 70 turns on transistor 72 to discharge the current from the event voltage back to node 28. Again, a small portion of the current flows through the substrate diodes of transistors 30 and 34.

If a positive voltage is applied to node 26 with respect to power supply conductor 38, transistor 36 becomes forward biased and conducts to pull power supply conductor 40 to a high level greater than VREF2. The high voltage on node 26 also turns on transistor 30 which sets node 28 to ground potential. The output of comparator 70 goes high and turns transistor 72 to discharge the current from the event voltage back through transistor 30 to power supply conductor 38. If the positive voltage is applied to node 28 with respect to power supply conductor 38, transistor 34 becomes forward biased and conducts to pull power supply conductor 40 to a high level greater than VREF2. The high voltage on node 28 also turns on transistor 32 which sets node 26 to ground potential. The output of comparator 70 goes high and turns transistor 74 to discharge the current from the event voltage back through transistor 32 to power supply conductor 38.

In summary, the present invention provides a power supply clamp in a contactless PDC. The PDC includes a tuned circuit that receives a magnetic field from a PDC reader. When the tuned circuit in the PDC is brought in proximity to a magnetic field from a PDC reader, an alternating voltage is developed at first and second nodes of the tuned circuit. A rectification circuit is coupled to the first and second nodes and provides a rectified signal as a power supply to the PDC. The clamping circuit is coupled across the first and second nodes and operates in response to the rectified signal for limiting an amplitude of the alternating voltage. The clamping circuit controls the impedance of the tuned circuit to clamp or limit the amplitude of the alternating voltage and thereby limit the DC output voltage. By placing the clamping circuit across the tuned circuit, the output of the rectifier is not loaded with the clamp which avoids excessive ripple on the DC output voltage.

Claims

CLAIMS 1. A power supply clamp for a personal data carrier (PDC) (10), comprising: a tuned circuit (22-24) coupled for receiving a transmitted signal and developing an alternating voltage at first (26) and second (28) nodes of the tuned circuit; a first rectification circuit (30-36) having first and second inputs respectively coupled to the first and second nodes for providing a rectified signal as a power supply to the PDC; and a clamping circuit (46-50) coupled across the first and second nodes and operating in response to the rectified signal for limiting an amplitude of the alternating voltage.
2. The power supply clamp of claim 1 wherein the tuned circuit includes a coil.
3. The power supply clamp of claim 1 wherein the clamping circuit includes: an amplifier (46) having a first input coupled for receiving the rectified signal, and a second input coupled for receiving a reference signal; and a transistor (50) having a first conduction terminal coupled to the first node, a second conduction terminal coupled to the second node, and a control terminal coupled to an output of the amplifier.
4. The power supply clamp of claim 3 wherein the amplifier is a transconductance amplifier and the clamping circuit further includes a first capacitor (48) coupled between the output of the amplifier and a power supply conductor (38).
5. The power supply clamp of claim 3 wherein the clamping circuit includes: a first capacitor (52) coupled between the first conduction terminal and the control terminal of the transistor; and a second capacitor (54) coupled between the second conduction terminal and the control terminal of the transistor.
6. The power supply clamp of claim 1 further including a second rectification circuit (60-66) having first and second inputs coupled to the first and second nodes, respectively, and having an output for recovering data modulated on the transmitted signal.
7. The power supply clamp of claim 6 wherein the second rectification circuit includes: a first diode-configured transistor (60) having a first terminal coupled to the first node and having a second terminal coupled to the output of the second rectification circuit; a second diode-configured transistor (62) having a first terminal coupled to the second node and having a second terminal coupled to the output of the second rectification circuit; and a first capacitor (66) coupled between the output of the second rectification circuit and a power supply conductor (38).
8. The power supply clamp of claim 1 further including: an amplifier (70) having a first input coupled for receiving the rectified signal at an output of the power supply clamp, and a second input coupled for receiving a reference signal; a first transistor (72) having a first conduction terminal coupled to the output of the power supply clamp, a second conduction terminal coupled to the first node, and a control terminal coupled to an output of the amplifier; and a second transistor (74) having a first conduction terminal coupled to the output of the power supply clamp, a second conduction terminal coupled to the second node, and a control terminal coupled to an output of the amplifier.
9. The power supply clamp of claim 1 wherein the first rectification circuit includes: a first transistor (32) having a first conduction terminal coupled to a power supply conductor (38), a second conduction terminal coupled to the first node, and a control terminal coupled to the second node; a second transistor (36) having a first conduction terminal coupled together with a control terminal to the first node, and a second conduction terminal coupled to an output of the power supply clamp; a third transistor (30) having a first conduction terminal coupled to the power supply conductor, a second conduction terminal coupled to the second node, and a control terminal coupled to the first node; and a fourth transistor (34) having a first conduction terminal coupled together with a control terminal to the second node, and a second conduction terminal coupled to the output of the power supply clamp.
10. A method of limiting a power supply voltage to a personal data carrier (PDC), comprising: inducing an alternating voltage across a tuned circuit (22) at first (26) and second (28) nodes in response to a transmitted magnetic field; rectifying the alternating voltage and providing a rectified signal as the power supply voltage to the PDC; amplifying the rectified signal with respect to a reference signal to provide a control signal; and controlling a first transistor coupled across the first and second nodes with the control signal to alter an impedance of the tuned circuit to limit the alternating voltage.
11. The method of claim 10 further including the step of rectifying the alternating voltage to recover data modulated on the transmitted magnetic field.
12. A data communication system, comprising: a personal data carrier (PDC) reader (12) providing a transmitted signal; and a PDC (10) coupled for receiving the transmitted signal from the PDC reader, the PDC including, (a) a tuned circuit (22) coupled for receiving the transmitted signal and providing an alternating voltage at first (26) and second (28) nodes of the tuned circuit, (b) a first rectification circuit (30-36) having first and second inputs respectively coupled to the first and second nodes for providing a rectified signal as a power supply to the PDC, and (c) a clamping circuit (46-50) coupled across the first and second nodes and operating in response to the rectified signal for limiting an amplitude of the alternating voltage.
13. The data communication system of claim 12 wherein the clamping circuit includes: an amplifier (46) having a first input coupled for receiving the rectified signal, and a second input coupled for receiving a reference signal; and a transistor (50) having a first conduction terminal coupled to the first node, a second conduction terminal coupled to the second node, and a control terminal coupled to an output of the amplifier.
14. The data communication system of claim 13 wherein the clamping circuit further includes a first capacitor (48) coupled between the output of the amplifier and a power supply conductor (38).
15. The data communication system of claim 13 wherein the clamping circuit includes: a first capacitor (52) coupled between the first conduction terminal and the control terminal of the transistor; and a second capacitor (54) coupled between the second conduction terminal and the control terminal of the transistor.
16. The data communication system of claim 13 further including a second rectification circuit (60-66) having first and second inputs coupled to the first and second nodes, respectively, and having an output for recovering data modulated on the transmitted signal.
17. A power supply clamp for a personal data carrier (PDC) substantially as hereinbefore described with reference to the accompanying drawings.
18. A method of limiting a power supply voltage to a personal data carrier (PDC) substantially as hereinbefore described with reference to the accompanying drawings.
19. A data communication system substantially as hereinbefore described with reference to the accompanying drawings.