GB2329771A

GB2329771A - Detection and stopping of a blocked or overloaded permanently excited direct current motor

Info

Publication number: GB2329771A
Application number: GB9821142A
Authority: GB
Inventors: Tilmar Koenig
Original assignee: Siemens AG
Current assignee: Siemens AG
Priority date: 1997-09-30
Filing date: 1998-09-29
Publication date: 1999-03-31
Also published as: DE19743233A1; GB9821142D0; CA2248740A1

Abstract

The invention relates to a method and a circuit arrangement for the detection and stopping of a blocked or overloaded, permanently excited direct current motor. After the starting of the motor (M) by way of a motor relay (MR) the stopping of the motor (M) takes place by way of the motor relay (MR) after a defined starting time (Tr). At the terminals of the motor (M) a generator voltage (UG) or back EMF is measured and is compared with a defined threshold value (Uref). If the generator voltage (UG) exceeds the threshold value (Uref) the motor (M) is started again. A value above the threshold is indicative of the motor running above an expected speed.

Description

is 2329771 METHOD AND CIRCUIT ARRANGEMENT FOR THE DETECTION AND STOPPING

OF A BLOCKED OR OVERLOADED, PERMANENTLY EXCITED DIRECT CURRENT MOTOR.

The invention relates to a method and a circuit arrangement for the detection and stopping of a blocked or overloaded, permanently excited direct current motor.

With heavily braked or blocked direct current motors the motor operating current increases greatly. If, in the extreme case, the motor can no longer rotate at all unimpeded, the operating current increases up to a motor-dependent maximum current, the blocking current. In this respect, it is problematic that this blocking current usually greatly exceeds the dimensioning limit for associated supply cables. With larger motors there is therefore a danger that the cables will burn.

In hitherto-existing solutions have utilised a fuse with suitable inertia, which fuse interrupts the operating circuit. In this respect, it is a disadvantage that the fuse has to be replaced after the interruption of the circuit, signifying increased expenditure on maintenance. In order to prevent a melting of the fuse due to the increased motor current during the starting phase of the motor, a certain inertia is necessary for the fuse. With the occurrence cJ an operating current which exceeds the values of a specified fuse characteristic over a prolonged period, the fuse melts, with a corresponding protective function being initiated as a result.

The present invention seeks to develop a method for the detection and stopping of an overloaded or blocked direct current motor which makes a reduction of the maintenance expenditure possible. The method should be capable of being implemented in particular also in terms of hardware.

In accordance with the invention, there is provided a method for the detection and stopping of a blocked or overloaded, permanently excited direct current motor, comprising the following steps:

a) starting the motor by way of a motor relay, b) stopping the motor by way of the motor relay after a defined starting time, measuring a generator voltage at the terminals of the motor, comparing the generator voltage with a defined threshold value, restarting the motor if the generator voltage exceeds the threshold value.

With this method the direct current motor is therefore separated from the operating voltage after a starting time, and at the terminals of the idling direct current motor the generator voltage is measured.

In an advantageous development of this alternative method, after a predefined delay a measurement of the generator voltage is carried out once again.

If, with a preceding measurement, the generator voltage has fallen below the defined threshold value, after a waiting time the motor is started once again. one then begins with a renewed run-through of the procedural steps which were carried out previously. For this purpose, the motor is stopped after a defined starting time and the generator voltage is measured and evaluated once again.

For the case where the generator voltage has exceeded the defined threshold value in a previous measurement, the motdr is briefly stopped once again after a fixed waiting 'c-ime and the generator voltage-of the idling motor is measured and evaluated.

c) d) e)

Claims

Claim 3 describes a circuit arrangement for implementing the method in

accordance with the is invention. Advantageous developments of the circuit arrangement are indicated in claims 4 to 12.

For a better understanding of the present invention and to show how the same may be carried into effect, reference will now be made, by way of example, to the accompanying drawings, in which:- Figure 1 shows a flow chart for a discontinuous testing of a direct current motor, which mirrors a method in accordance with the invention.

Figure 2 shows a circuit for implementing the flow chart according to Figure 1 in terms of hardware.

Figure 1 shows a flow chart for the steps of a method for the detection and stopping of a blocked or overloaded direct current motor. The first step comprises switching on a motor switch MS. In the second step an additional motor relay MR is started, which is stopped again after a starting time Tr In the fifth procedural step, when the motor is separated from the operating-voltage source, the generator voltage UG at the terminals of the motor is measured. Subsequently, the measured value UG is compared with a reference value Uref Depending on the comparison, it is established that the speed w of the motor is either greater than zero or equal to zero. With a motor which rotates unimpeded, according to step 8a the motor relay MR is again closed. For the case where the motor is blc--::ked, the operating circuit remains interrupted by the motor relay MR.

Step 9a or 9b is optional. After a delay Td the operating circuit is once again-Interrupted by the motor relay MR and is once again cl.osed if a blocked motor was previously detected. Subsequently, the hitherto described procedural steps are run through once again in another loop. By selecting an appropriate delay Td an interval for the inquiry of the is operating state of the motor can be defined. The delays Td for the steps 9a and 9b can be of varying lengths.

In Figure 2 a hardware implementation of the method described by the flow chart according to Figure 1 is reproduced. A direct current motor M is arranged in the load circuit of a motor relay MR, between the terminals of which direct current motor M a voltage UG can be measured. A first terminal of the control circuit of the motor relay MR is connected to an operating voltage source UB The second terminal of the control circuit of the motor relay MR is connected to the collector of a first NPN switching transistor T1. The emitter of the switching transistor Ti is connected to earth. A series resistance Ri and a motor switch MS are arranged between the base terminal of the transistor T1 and the operating-voltage source UB.

The circuit for the discontinuous detection of a blocked or overloaded direct current motor has, moreover, a comparator K, a timer Z and an RS flipflop FF. The comparator K is connected by an input EK1 by way of a diode D1 to a point PG between a first terminal of the direct current motor M and the switching contact of the motor relay MR. When the switching contact is closed, the first terminal of the motor M is connected to the operating-voltage source UB, whereas the second te-Minal of the motor M is connected to earth. A resistance Ril is connected between the first input terminal EK1 of the comparator K and earth. An RC element, comprising a resistance R12 and-a capacitor Cl, is arranged parallel to the resistance R11. In this respect, the capacitor Cil is connected by a first terminal to a non-inverting input of a first operational amplifier OP1 of the comparator K and by its second terminal to earth. The inverting input of the operational amplifier OP1 is connected to is a voltage divider comprising a first resistance R13 and a second resistance R14, with a reference voltage Uref falling at the resistance R14 arranged between earth and the inverting input. On one side the resistance R13 is connected to the inverting input of the operational amplifier OP1 and on the other side to a point Ps of the circuit which is connected to the operating-voltage source U. by means of a diode DS. In addition, a capacitor C3 is connected between the point Ps and earth in order to stabilize the supply voltage. On the output side an NPN transistor T3 with its collector is connected to the operational amplifier OP1. The emitter terminal of the transistor T3 coincides with an output terminal AK of the comparator circuit K.

The timer Z is connected by an input terminal EZ by way of the diode D2 to the point PG between the motor M and the switching contact of the relay MR. timer Z has a first operational amplifier OP2 and a second operational amplifier OP3, the output of which is connected by way of a resistance Ris by the base of the transistor T3 to a second input EK2 of the comparator circuit K. On the input side the timer Z has an RC combination, comprising a resistance R21 and a capacitor C21. The operational amplifier OP2 is connected between the resistance R21 and the capacitor C21 by its inverting input, with the capacitor C21 being arranged between the inverting input and earth. The resistance R21 is arranged between the input terminal Ez of the timer Z and the inverting terminal of the operational amplifier OP2. The non-inverting input of the operational amplifier OP2 is connected to a voltage divider, comprising a resistance R22 and a resistance R23. The resistance R22 is connected between the point Ps and the non-inverting input of the operational amplifier OP2, whereas the resistance R23 is is arranged between the non-inverting input and earth. The second operational amplifier OP3 of the timer Z is connected at its non- inverting input in a similar way to a voltage divider, comprising a resistance R32 and a resistance R33, with the resistance R33 being connected between the non-inverting input and earth. The inverting input of the operational amplifier OP3 is connected to an RC combination, comprising a resistance R31 and a capacitor C31. In this respect, the resistance R31 is connected between the inverting input and the point PS' whereas the capacitor C31 is arranged between the inverting input and earth. A capacitor C22 is connected by a terminal between the resistance R31 and the capacitor C31 to the inverting input of the operational amplifier OP3. Its second terminal is connected to the output of the operational amplifier OP2. The output of the second operational amplifier OP3 of the timer Z forms an output terminal Az of the timer Z. A differential element is connected between the output terminal AZ and a set input S of the flipflop FF, the differential element comprising a capacitor Cl and a resistance RS In this respect, the resistance RS is connected between the set input S and earth.

The reset terminal R of the flipflop FF is connected to the output AK of the comparator and is connected to -.-^n RC element comprising a capacitor C2 and a resistance RR A power-on-reset device is formed by the RC element. In this respect, the capacitor C2 is arranged with its terminals between the reset input R and the point PS, whereas the resistance RR is connected between.L:he reset input R and earth. The non- inverting output Q of the flipflop FF is connected to the second input terminal EK2 of the comparator K by way of a diode D4. In addition, a diode D3 is connected between the second input terminal EK2 of the -7 comparator K and the output terminal Az of the timer Z. The two diodes D3 and D4 provide an electrical isolation function.

The collector terminal of an additional switching transistor T2 is connected to the base terminal of the transistor T1. The emitter terminal of the transistor T2 is connected to earth. Moreover, the transistor T2 is connected on the base side to a series resistance R2, On the one hand this resistance R2 is connected by way of the diode D3 to the output Az of the timer Z and on the other hand by way of the diode D4 to the noninverting output Q of the flipflop FF.

An optional component ARF for the periodical detection of the motor state is connected on the input side to the output AZ of the timer Z and on the output side to the inverting input of the first operational amplifier OP2 of the timer Z. The optional switching unit ARF essentially contains a delay element and a level converter.

The operational amplifiers OP1, OP2 and OP3 contained in the circuit according to Figure 2 have, in all, a unipolar voltage supply. In this respect, a first supply terminal is connected to the supply voltage UB and a second current supply terminal is connected to earth.

The starting of the motor M takes place by closIng the motor switch MS. At-the instant at which the motor switch MS is closed, the transistor T2 is in the nonconducting state, and so the control circuit of the motor relay MR is closed by way of the transistor T1. This eú."fects a starting of the motor M. The outputs of the oper,.7tional.ari-,plifiers OPI: and OP2 first of all have high potential, whereas low potential is present at the output of the operational amplifier OP3. The capacitor C22 at the output of the operational amplifier OP2 is first of all discharged. The set is input S of the flipflop FP has a low potential. The transistor T3 is in the blocked state.

During the motor start-up the capacitor C 21 is charged by way of the resistance R21. After a starting time which is determined by the values of the resistance R21 and the capacitor C21, the voltage falling at the capacitor C21 exceeds the value of the voltage falling at the resistance R2,, with the result that the operational amplifier OP2 changes over and its output assumes low potential. This leads to the capacitor C22 being connected parallel to the capacitor C.1, with a temporary voltage drop at the inverting input of the operational amplifier OP3 being generated as a result. For a certain duration which depends on the values of the resistance R31 and the two capacitors C22 and C31, the voltage at the inverting input of the operational amplifier OP3 falls below the voltage present at the non-inverting input of the operational amplifier OP3. For this period the output of the operational amplifier OP3 assumes high potential. In this way, the output Az of the timer likewise assumes high potential. By way of the differential element at the output Az of the timer Z the flipflop FP changes its storage state by means of a short pulse. The transistor T3 conducts. Furthermore, the transistor T2 also enters into the conducting state, whereas the t-.;-,-ansistor T1 blocks and the control circuit, and therefore the load circuit of the motor relay MR, are opened.

While the transistor T2 is in the conducting state, the motor is separated from the suppll voltage U.. The generator voltage UG at the terminals-of the motor M can therefore be measured. In this respect, the diodes D1 and D2 prevent the discharge of the capacitors Cil and C21 over undesirable current paths, whereby, in particular, an increased voltage drop, is caused by the discharge, is prevented at the motor resistance.

If the voltage at the capacitor Cil exceeds the value of the voltage Uref which is present at the inverting input of the operational amplifier OP1 of the comparator K, the output of the operational amplifier OP1 assumes high potential. Because of the conducting transistor T3, this level is also present at the reset terminal R of the flipflop FF. At the noninverting output Q of the flipflop FF there is low potential, with the transistor T2 blocking and the transistor Tl entering into the conducting state as a result. This leads to the motor M being connected to the supply voltage UB again by way of the motor relay MR.

If, however, the voltage at the capacitor Cl. is less than the voltage Uref at the inverting input of the operational amplifier OP1, the output of the operational amplifier OP1 assumes low potential. The reset terminal R of the flipflop FF is also provided with this level. At the non-inverting output Q of the flipflop FF a high level continues to remain stored, with the transistor T2 remaining in the conducting state as a result. The transistor Tl therefore continues to remain blocked and the motor M continues to remain separated from the supply voltage UB by means of the switching contacts of the motor relay MR.

By means.if the optional switching unit ARF a voltage pulse, which is formed by the high level which is briefly present at the output of the operational amplifier OP3, is delayed by a dead time. At the same time the logical levels are reversed, whereby, with a skew, a negative vultage pulse is present at the inverting input of the operational amplifier OP2. At its output the operational amplifier OP2 briefly changes over to high level, with the operational amplifier OP3 changing over to low potential as a result. Moreover, the capacitor C22 begins to discharge itself. The starting state of the circuit is thus re-established immediately after the closing of the motor switch MS, whereby the detection method can be started anew.

CLAIMS 1. Method for the detection and stopping of a blocked or overloaded, permanently excited direct current a) b) c) d) motor, comprising the following steps: starting the motor by way of a motor relay, stopping the motor by way of the motor relay after a defined starting time, measuring a generator voltage at the terminals of the motor, comparing the generator voltage with a defined threshold value, restarting the motor if the generator voltage exceeds the threshold value. Method according to claim 1, wherein if the generator voltage falls below the defined threshold value, the motor is started once again after a certain delay, is stopped after the defined starting time, and the generator voltage is measured and evaluated once again, and in that, if the generator voltage exceeds the defined threshold value, the motor is stopped once again after a certain delay, and the generator voltage is measured and evaluated once again. 3. Circuit arrangement for implementing a method according to claim 1 or claim 2, comprising a motor control unit with a motor switch and a motor relay; a direct current motor which can be connected by a first terminal by way of switching contacts of the motor relay to a supply- voltage source and is connected by a second terminal to earth; a comparator for comparing a voltage falling biatween the terminals of the direct curren- motor with a reference voltage, with a first input terminal of the comparator being connected to the first terminal of the direct current motor; a timer, with an input terminal of the timer being connected to the first terminal of the direct current motor, and an output terminal of the timer being connected to a second input terminal of the comparator; and a memory unit which has a set terminal and a reset terminal, with an output terminal of the comparator being connected to the reset terminal of the memory unit, and the output terminal of the timer being connected to the set terminal by way of a differential element. 4. Circuit arrangement according to claim 3, further comprising means for stabilizing the supply voltage with a diode which is connected by its anode to the supply-voltage source and by its cathode to a voltagestabilized point of the circuit, and with a capacitor which is connected between the voltagestabilized point and earth. 5. Circuit arrangement according to claim 4, wherein the motor control unit has a first NPN switching transistor, the base of which can be connected by way of a first series resistance and the motor switch to the supply-voltage source, and the collector of which is connected by way of the exciter winding of the motor relay (MR) to the supply-voltage source, and the emitter of which is connected to earth, and in that the motor control unit has a second NPN switching transistor, the base of wh'-ch is connected by way of a second series resistance to the output terminal of the timer and to a non-inverting output terminal of the memory unit, and the collector of which is connected to tha base of the first switching transistor, and the ---m-'L-;_ter of which is c--nnected to earth. 6. Circuit arrangement according to claim 5, wherein the second series resistance of the motor control unit is connected by way of a first diode to is the output terminal of the timer and by way of a second diode to the non- inverting output terminal of the memory unit, with the diodes being connected by their cathodes to the second series resistance.

7. Circuit arrangement according to one of claims 4 to 6, wherein the comparator has an operational amplifier, the inverting input of which is connected to a voltage divider formed from two resistances, which voltage divider is connected between the voltage-stabilized point and earth, and the noninverting input of which is connected to an RC element formed from a resistance and a capacitor, with the capacitor being connected between earth and the noninverting input and the resistance being connected between the first input terminal and the non-inverting input, and in that an additional input resistance is connected between the first input terminal of the comparator and earth, and in that the comparator has an NPN transistor which is connected by its collector terminal to the output of the operational amplifier of the comparator, is connected by its base terminal by way of a series resistance to the second input terminal of the comparator and forms with its emitter terminal the output terminal of the comparator.

8. Circuit arrangement according to one of claims A to 7, wherein the timer has a first operational amplifier and a second operational amplifier which are respectively connected at their non-inverting input to a voltage divider formed from two resistances, which voltage divider is connected between the voltage-stabilized,point and earth, and which are respectively connected.-..it their inverting input to a capacitor, with the capacitors being connected between earth and the inverting inputs, and wherein an input resistance is connected between the input terminal of the timer and the inverting input of the first operational amplifier of the timer, and in that an output capacitor is connected between the output of the first operational amplifier of the timer and the inverting input of the second operational amplifier of the timer, and in that an input resistance is connected between the voltage-stabilized point of the circuit and the inverting input of the second operational amplifier of the timer.

9. Circuit arrangement according to one of claims 4 to 8, wherein the memory unit has an RS flipflop, the set input of which forms the set terminal of the memory unit, and the reset input of which forms the reset terminal of the memory unit, and the noninverting output of which forms the output terminal of the memory unit, and in that the reset terminal of the memory unit is connected by way of a capacitor to the voltagestabilized point, and in that the reset terminal of the memory unit is connected to earth by way of a resistance.

10. Circuit arrangement according to one of claims 4 to 9, wherein the first input terminal of the comparator is connected by way of a diode to the first terminal of the direct current motor, with the anode of the diode being connected to the first terminal of the direct current motor.

11. Circuit arrangement according to one of claims 4 to 10, wherein. the input terminal of the timer is connected by way of a diode to the first terminal of the direct current motor, with the anode of the diode being connected to the first terminal of the direct current motor.

12- Circuit arrangemei.t according to one of claims 4 to 11, wherein that means for signal delay and for level conversion are connected between the output terminal of the timer and the inverting input of the first operational amplifier of the timer.

-15 13. A method substantially as herein described, with reference to the accompanying drawings.

14. A circuit arrangement substantially as herein described, with reference to the accompanying drawings.