GB2329045A

GB2329045A - Control of flash memory devices

Info

Publication number: GB2329045A
Application number: GB9718812A
Authority: GB
Inventors: David Michael Bush; Stephen Joseph Peter Mckinley
Original assignee: Ericsson OMC Ltd
Current assignee: Ericsson OMC Ltd
Priority date: 1997-09-04
Filing date: 1997-09-04
Publication date: 1999-03-10
Anticipated expiration: 2017-09-04
Also published as: GB9718812D0; GB2329045B

Abstract

A number of data bits in a flash memory device 5 are allocated as validation bits 51, initially set at a high logic level, for a software image stored in the flash memory device and each time the stored software image experiences an error during execution one of the validation bits is set to a low logic level; execution of the stored software image is prevented if all the validation bits are at a low level. Preferably a device may store a plurality of software images, each with its own validation bits. If all the validation bits of the software image which it is desired to run are at a low level, a default software image stored in a default memory 7 may be executed instead.

Description

CONTROL OF FLASH MEMORY DEVICES The present invention relates to control of flash memory devices.

DESCRIPTION OF THE RELATED ART Flash memory devices are being increasingly used in telecommunications systems because they give the advantage of in-system reprogrammability which increases functionality and reduces the price of handsets. Flash memory devices allow system software updates to be stored in the handset. This enables hardware changes to be kept to a minimum, but allows development of system functionality.

However, with current flash memory devices and controllers, the system can suffer from repeated crashrun-crash cycles if the new software update is faulty.

SUMMARY OF THE PRESENT INVENTION It is therefore an object of the present invention to provide a flash memory device controller which enables reliable return to a default or original software version if the updated software version is faulty.

According a first aspect of the present invention there is provided a method of operating a flash memory device comprising allocating a predetermined number of data bite in the flash memory device to be validation bits, the number of validation bits which are at a high logic level equalling the number of execution attempts remaining for a software image stored in the flash memory device, setting one of the validation bits to a low logic level whenever the stored software image experiences an error, and preventing execution of the stored software image if all the validation bits are at a low logic level.

According to a second aspect of the present invention there is provided a flash memory device controller for controlling a flash memory device having a predetermined number of data bits therein allocated as validation bits, the number of validation bits which are at a high logic level equalling the number of execution attempts remaining for a software image stored in the flash memory device, the controller comprising validation means for setting one of the validation bits in the flash memory device to a low logic level whenever the stored software image experiences an error, and control means for preventing execution of the stored software image if all the validation bits are at a low logic level.

BRIEF DESCRIPTION OF THE DRAWINGS Figure 1 shows schematically a system employing an embodiment of the present invention; Figure 2 is a flowchart illustrating steps in a method embodying the present invention; Figure 3 is a chart showing validation bit updates in a method embodying the present invention; and Figure 4 shows schematically a practical system employing an embodiment of the present invention suitable for use in a mobile telephone.

DETAILED DESCRIPTION OF THE DRAWINGS A system employing an embodiment of the present invention is shown in Figure 1 and comprises a memory controller 3, a flash memory device 5, and a default memory device 7. The memory controller communicates with the flash memory device 5 by way of a control link 6, and with the default memory device 7 by way of a control link 8.

The default memory device 7 is used to store a default software image, and the flash memory device 5 is used to store an update software image.

The flash memory 5 includes a validation area 51 and a software image area 52. The validation area 51 is used to store information concerning the number of execution attempts remaining for a software image stored in the software image area 52, as will be explained in more detail below.

The memory controller 3 includes validation means 31 and control means 32.

When the flash memory device 5 is reset, all of the data storage bits are set to a high logic level ("1"). A software image is written into the software image area 52 by causing selected data bits to be set to a low logic level ("0"). A predetermined number of bits in the flash memory device 5 are allocated as validation bits and define the validation area 51.

These validation bits indicate the number of execution attempts available for the software image stored in the device.

When the software image stored in the image area 52 is executed and experiences an error, the validation means 31 of the memory controller 3 sets one of the high logic level validation bits in the flash memory device 5 to zero. If all of the validation bits in the validation area 51 are equal to zero then the control means of the memory controller 3 operates to prevent the update software image stored in the flash memory device 5 from being executed. In that case, the default software image is executed.

The number of bits allocated for the validation area 51 can be adjusted as necessary.

Operation of the system will now be explained in more detail with reference to Figure 2. The process starts at step 101 and proceeds to step 102 where the validation bits stored in the validation area 51 of the flash memory device 52 are checked. If all of these validation bits are logical zero, then the software image stored in the flash memory device 5 has no remaining execution attempts, and so the default eoftware image stored in the default memory device 7 is executed (step 106).

However, if one or more of the validation bits is logical 1, then the process proceeds to step 103 where the update software image stored in the flash memory device 5 is executed.

At step 104 execution of the update software image is checked for the occurrence of errors. While no errors occur, execution of the update software image continues.

However, if an error occurs, a validation bit which is at logical 1 (a high logic level) is reset to logical zero (a low logic level) at step 105. This effectively decrements the number of execution attempts remaining for the update software image. The process returns to step 102 where a check of the validation bits is carried out.

It will be readily appreciated that the number of attempts available for execution of the update software image is defined by the number of allocated validation bits. When the predetermined attempts have been made, then the default software image is executed in place of the update software image stored in the flash memory device 5, thereby enabling the system to continue operation.

Figure 3 illustrates the cycle of steps, together with the validation bit values. In Figure 3, only four validation bits are used, although naturally any number of bits could be specified.

The default memory device 7 can be provided by any suitable device. For example, it could be a read only memory device (ROM), or another flash memory device.

The default memory device and the flash memory device 5 could be provided by different respective areas of a single flash memory device. Alternatively, the default memory device could be provided by a memory area of the memory controller 3. The illustrations shown in Figures 1 and 2 are merely schematic and are intended only to show the functional capability of embodiments of the invention.

Figure 4 shows a practical system employing an embodiment of the present invention which is suitable for use in a mobile telephone. The Figure 4 system includes a memory controller 3, a flash memory device 5, a default memory device 7, as before, and a function software image storage device 9. The device 9 is preferably a flash memory device, although could be provided by any appropriate memory storage device. As before, the memory devices 5 and 7 could be provided separately, or by a single flash device.

The device 9 stores a number of function software images 91, 92 ... 9n, which can provide the system with different functions. For example, different functions could be provided for different countries, such as various language options etc.. Alternatively, different revisions of a software version could be stored in the device 9, to provide a back up capability.

Each of the storage areas 91...9n includes a software image storage area and a validation storage area. As in the previous system, each software image has a validation area associated with it, the bits in the validation area setting the number of execution attempts remaining for the software image concerned.

In use, the memory controller 3 searches the memory store 9 to find the correct new software image.

The validation bits for that particular software image can then be checked, and if a non-zero result is achieved the new software image can be loaded into the flash memory device 5 for execution. If the new software image then experiences an error, the validation bits relating to that software image are adjusted as in the previous system, and the results stored in the memory device 9.

When a software image stored in the memory device 9 has all zero-value validation bits, then a different new software image could be found in the storage device 9 and executed. Alternatively, a default software image could be executed from the default memory device 7.

Thus, it will be readily appreciated that embodiments of the present invention can avoid crashrun-crash cycles associated with faulty new software images. By adjusting the validation bits on each occasion that the update software image experiences an error.

Claims

CLANS

1. A method of operating a flash memory device comprising: allocating a predetermined number of data bits in the flash memory device to be validation bits, the number of validation bits which are at a high logic level equalling the number of execution attempts remaining for a software image stored in the flash memory device; setting one of the validation bits to a low logic level whenever the stored software image experiences an error during execution; and preventing execution of the stored software image if all the validation bits are at a low logic level.

2. A method as claimed in claim 1, wherein the flash memory device is operable to store a plurality of software images, each such software image having a predetermined number of validation bits allocated to it.

3. A method as claimed in claim 1 or 2, wherein a default software image is executed if all the validation bits are at a low logic level.

4. A flash memory controller for controlling a flash memory device having a predetermined number of data bits therein allocated as validation bits, the number of validation bits which are at a high logic level equalling the number of execution attempts remaining for a software image stored in the flash memory device, the controller comprising: validation means for setting a validation bit in the flash memory device to a low logic level whenever the stored software image experiences an error; and control means for preventing execution of the stored software image if all the validation bits are at a low logic level.

5. A controller as claimed in claim 4, wherein the control means is operable to executed a default software image if all the validation bits for the stored software image are at a low logic level.

6. A controller as claimed in claim 4 or 5, wherein the flash memory device is operable to store a plurality of software images, each of which stored software images has a corresponding predetermined number of validation bits allocated to it.

7. A software storage device comprising a flash memory device controller as claimed in any one of claims 4 to 6, a flash memory device connected to the memory controller and operable to store a software image and validation bits associated therewith; and a default memory device for storing a default software image.

8. A system as claimed in claim 7, further comprising an update software storage device which is operable to store a plurality of software images, each of which has an associated validation area, the stored software images being selectively transferable to the flash memory device and executable therein.