GB2325082A - Thermal via arrangement - Google Patents
Thermal via arrangement Download PDFInfo
- Publication number
- GB2325082A GB2325082A GB9709273A GB9709273A GB2325082A GB 2325082 A GB2325082 A GB 2325082A GB 9709273 A GB9709273 A GB 9709273A GB 9709273 A GB9709273 A GB 9709273A GB 2325082 A GB2325082 A GB 2325082A
- Authority
- GB
- United Kingdom
- Prior art keywords
- vias
- substrate
- arrangement
- conductive material
- thermally conductive
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Withdrawn
Links
Classifications
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K1/00—Printed circuits
- H05K1/02—Details
- H05K1/0201—Thermal arrangements, e.g. for cooling, heating or preventing overheating
- H05K1/0203—Cooling of mounted components
- H05K1/0204—Cooling of mounted components using means for thermal conduction connection in the thickness direction of the substrate
- H05K1/0206—Cooling of mounted components using means for thermal conduction connection in the thickness direction of the substrate by printed thermal vias
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/34—Arrangements for cooling, heating, ventilating or temperature compensation ; Temperature sensing arrangements
- H01L23/36—Selection of materials, or shaping, to facilitate cooling or heating, e.g. heatsinks
- H01L23/367—Cooling facilitated by shape of device
- H01L23/3677—Wire-like or pin-like cooling fins or heat sinks
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
- H01L2224/321—Disposition
- H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
- H05K2201/09—Shape and layout
- H05K2201/09209—Shape and layout details of conductors
- H05K2201/09372—Pads and lands
- H05K2201/09418—Special orientation of pads, lands or terminals of component, e.g. radial or polygonal orientation
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
- H05K2201/10—Details of components or other objects attached to or integrated in a printed circuit board
- H05K2201/10007—Types of components
- H05K2201/10166—Transistor
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/0058—Laminating printed circuit boards onto other substrates, e.g. metallic substrates
- H05K3/0061—Laminating printed circuit boards onto other substrates, e.g. metallic substrates onto a metallic substrate, e.g. a heat sink
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/40—Forming printed elements for providing electric connections to or between printed circuits
- H05K3/42—Plated through-holes or plated via connections
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Chemical & Material Sciences (AREA)
- Materials Engineering (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Power Engineering (AREA)
- Cooling Or The Like Of Semiconductors Or Solid State Devices (AREA)
- Structure Of Printed Boards (AREA)
Abstract
An electronic component, such as a power transistor 20 is mounted on a substrate 38. A number of thermal vias 60 are formed in the top surface of the substrate which extend to the bottom surface. The thermal vias are arranged in a hexagonal array so that each via not located at an edge of the array is located in a position equidistant from the six closest neighbouring thermal vias.
Description
Electronic Component Arrangement and Method
Field of the Invention
This invention relates to electronic component arrangements and particularly but not exclusively to heat dissipation in electronic component arrangements.
Background of the Invention
Electronic components, particularly those used in power applications such as amplifiers, generate heat as current is drawn. Technological advances have led to the power ratings of such components increasing, while their dimensions are decreasing. This means that more heat is generated and heat dissipation becomes an increasing problem. Heat must be transferred away from the component (such as a power transistor) through a mounting to the environment.
A typical component arrangement consists of a substrate to which the component is mounted, the substrate also being coupled to a heat sink or externally cooled member of the assembly (such as an attached base plate or rigidiser).
A typical technique for aiding heat transfer through a substrate is the use of thermal vias or channels. Copper pads are formed on the top surface of the substrate where the power device will be located, and a hole or via is drilled through the copper pad and the substrate, to the bottom surface.
The hole is then typically lined with copper. Copper is used for the pad and the lining because of its thermal properties.
A problem with this arrangements is that the vias only conduct a limited amount of heat away from the component. This invention seeks to provide an electronic component arrangement and method which mitigate the above mentioned disadvantages.
Summarv of the Invention
According to a first aspect of the present invention there is provided a method of fabricating an electronic component arrangement, comprising the steps of: providing a substrate having top and bottom surfaces; forming first and second thermal vias on first and second portions of the substrate respectively which extend vertically between the top and bottom surfaces, the second portion being substantially adjacent the first portion; mounting an electronic component on the top surface of the first portion.
Preferably the step of forming the first and second vias includes the step of forming pads of thermally conductive material on the top surface corresponding to desired locations of the vias. Alternatively the step of forming the first and second vias includes the step of forming an area of thermally conductive material on the top surface corresponding to desired locations of the vias.
Preferably the step of forming the first and second vias includes the step of drilling holes at the desired locations which extend from the thermally conductive material to the bottom surface of the substrate.
According to a second aspect of the present invention there is provided an electronic component arrangement comprising: a substrate having top and bottom surfaces; first and second thermal vias in first and second portions of the substrate respectively which extend vertically between the top and bottom surfaces, the second portion being substantially adjacent the first portion; an electronic component on the top surface of the first portion.
Preferably the arrangement further comprises pads of thermally conductive material on the top surface of the substrate corresponding to locations of the vias. The arrangement preferably also further comprising an area of thermally conductive material on the top surface of the substrate corresponding to locations of the vias.
The vias preferably extend from the thermally conductive material to the bottom surface of the substrate. Preferably the vias are arranged in an array such that each via not at an edge of the array is located in a position equidistant from the six closest surrounding vias. Preferably the thermally conductive material is copper.
In this way an electronic component arrangement and method are provided which improve heat transfer away from the component.
Brief Description of the Drawing(s)
An exemplary embodiment of the invention will now be described with reference to the drawing in which: FIG. 1 shows a preferred embodiment of an electronic component arrangement in accordance with the invention.
FIGS. 2 and 3 show detailed cross sections of preferred features of the invention.
FIG.4 shows an alternative embodiment of an electronic component arrangement in accordance with the invention.
Detailed Description of a Preferred Embodiment
Referring to FIG. 1, there is shown an electronic component arrangement 10, comprising a power transistor 20, a substrate 30 and a rigidiser 40.
The substrate comprises a top surface 32 and a bottom surface 34. The power transistor is arranged to be mounted on the top surface 32 of the substrate, as further described below. A first portion 35 of the substrate 30 corresponds to an area underneath the power transistor 20 when mounted on the top surface 32 of the substrate 30. Second portions 37 and 38 of the substrate 30 are adjacent the first portion 35, but do not underlie the power transistor 20 when mounted.
Referring now also to FIGs.2 and 3, a number of copper pads 50 are formed on the top surface 32 of the substrate 30 before the power transistor 20 is mounted, on both the first and second portions 35, 37 and 38. The copper pads are preferably arranged as shown in FIG.3, in a regular array, with each pad 50 equidistant from its six closest neighbouring pads.
Each pad has an optimum radius p, to be further described below. The minimum pitch (distance) between the pads is thus equal to p. Considering the arrangement of FIG.3, the pad to pad minimum pitch is p horizontally, but 43/2 (-0.87p) vertically. In a conventional row-column grid of pads, each pad has a minimum pitch of p both vertically and horizontally, and so the above array provides approximately 15% more vias and thus a 15% improvement in heat transfer capability.
The vias 60 are formed by drilling a hole through the substrate 30, at the centre of each copper pad 50. The inside of the formed holes are then electroplated with copper to form a copper ring 65, which extends from the top surface 32 to the bottom surface 34 of the substrate 30, inside the formed hole.
The optimal dimensions for the via 60 and pad 50 arrangement are given
as follows. Each via 60 has a radius r, which includes the copper ring of
thickness Vc (Vc < =r) and is surrounded with the copper pad 50 of minimum width x (where x=(p/2)-r).
The vias are assumed to be "thermally small", close to one another forming a cluster with a very large dimension. The vias are also assumed to be located in an infinite domain. Therefore each individual via will function separately and an adiabatic boundary condition can be applied around each via, i.e., there is no heat exchange among vias.
Area of conductor in via =::r2-it(r-Vc)2=it(2rVc-Vc2) So the thermal resistance of the vias is: Rvia=t/(Kv*2*scrVc*N) where N is the number of vias, thus Rvia=4t(r2+x2+2rx)/(7cKvAsVc(2r-Vc)) To obtain the optimum value the above equation is differentiated and set equal to zero, giving: ((2r-Vc)Kv(2r+2x)-Kv(r2+x2+2rx)*2)/(2r-Vc)2=0 Apart from the trivial result of r=OO, the optimal values for r is given by: r=Vc~H(Vc2+4x(x+Vc))/2 When Vc is very small (an electroplated but unfilled via), this expression approximates to r-x (the via radius r should be the same as the width x of the pad around the via). This arrangement further improves the thermal transfer.
The substrate 30 is mounted on the rigidiser 40 by conventional means such as a pressure sensitive adhesive. In a similar way the power transistor 20 is typically soldered on the first portion 35 of the substrate 30. The ridigiser 40 may incorporate heat sink features, such as fins, or it may be bonded to an externally cooled member (not shown).
The provision of vias 60 in the second portion 37 of the substrate 30 augment the heat transfer capability of the vias 60 in the first portion 35 of the substrate, because the thermal conductivity of the substrate 30 in a horizontal plane is much higher than its conductivity in a vertical plane, and therefore heat propagating horizontally away from the power transistor 20 is drawn towards the rigidiser 40 by these additional vias.
The thermal conduction benefit of the vias in the second portion 37 decreases with distance from the first portion 35. A first via is a small distance Xviam away from an edge of the power transistor 20. A second via is a distance Xvian ( > > Xviam) from an edge of the power transistor 20.
If the thermal resistance in the plane of the board (assuming full heat spreading) is equal to Rnvia, then Xvianl(Kx*Hy*t )=Rnvia =t((KvVa) giving the result: Xvian =t2KxHy/(KvVa) Xviam is obtained in an identical way, but assuming no heat spreading:
Xviam/(KxVdt)=Rvian Xviam=2*Kx*tl(n;Kv) where Kx is the in plane conductivity of the substrate, Kv is the conductivity of the material used to plate the via, t is the thickness of the substrate, Hy is the length of the heat source perpendicular to direction of Xvia, Va = 1c*r*t.
If Kx=Kv (i.e. the same material is used for the pads and via lining), then: Xviam=2t/X=0.64t Xvian=tHy/(itr) if not this gives
Xvian-Hy
Heat without the aid of vias will spread between 0.5t and t from a side (close to 0.5t when t < =Hy) so the above extra vias will fill the heat spreading area.
Thus the plane is optimally extended on each side of the heat source by a distance of between 0.64t and Hy. For small surface mounted packages this can dramatically reduce the effective board resistance.
Referring now also to FIG.4 there is shown a High Density Interconnect (HDI) substrate 100 which comprises a standard core layer 130 and includes fine feature HDI layers 230 and 330 on lower and upper surfaces.
This arrangement can be considered as 3 substrates stacked as an alternative to a single substrate. The upper layer 330 has a first portion 335 directly underneath the heat source (power transistor) 20, and second portions 337 and 338 either side of the first portion 335. Vias 360 are formed in the first and second portions 335, 337 and 338, in the same manner as described above. The standard core layer 130 has a first portion 135 which extends to cover the area encompassing the vias 360 of the upper layer 330, and second portions 137, 138, either side of the first portion 135. The core layer 130 has vias 160 arranged in the same manner as described above. In this way the area of the vias 360 of the upper layer 330 is taken to be the effective heat source for the core layer 130.
In a similar way the lower layer 230 has a first portion 235 which extends to cover the area encompassing the vias 160 of the core layer 130, and second portions 237, 238, either side of the first portion 235. The lower layer 230 has vias 260 arranged in the same manner as described above. In this way the area of the vias 160 of the core layer 130 is taken to be the effective heat source for the lower layer 230.
This results in a stepped triangular shape to the via structure, which allows further spreading of the heat with each successive layer. If the base of the power transistor 20 cannot be connected directly to ground, then the the vias 360 in the upper layer 330 may be removed, such that the upper layer 330 is effectively an electrical insulator.
It will be appreciated that alternative embodiments to the one described above are possible. For example, the semiconductor device 20 could be replaced by any passive or active electronic component, such as a resistor or an integrated circuit.
Furthermore, the copper pads coupled be replaced by a single plating of copper. The copper in the pads, plating and via linings could be replaced by an alternative thermally conductive material or number of materials.
Claims (13)
1. A method of fabricating an electronic component arrangement, comprising the steps of: providing a substrate having top and bottom surfaces; forming first and second thermal vias on first and second portions of the substrate respectively which extend vertically between the top and bottom surfaces, the second portion being substantially adjacent the first portion; mounting an electronic component on the top surface of the first portion.
2. The method of claim 1 wherein the step of forming the first and second vias includes the step of forming pads of thermally conductive material on the top surface corresponding to desired locations of the vias.
3. The method of claim 1 wherein the step of forming the first and second vias includes the step of forming an area of thermally conductive material on the top surface corresponding to desired locations of the vias.
4. The method of claim 2 or 3 wherein the step of forming the first and second vias includes the step of drilling holes at the desired locations which extend from the thermally conductive material to the bottom surface of the substrate.
5. An electronic component arrangement comprising:
a substrate having top and bottom surfaces; first and second thermal vias in first and second portions of the substrate respectively which extend vertically between the top and bottom surfaces, the second portion being substantially adjacent the first portion; an electronic component on the top surface of the first portion.
6. The arrangement of claim 5 further comprising pads of thermally conductive material on the top surface of the substrate corresponding to locations of the vias.
7. The arrangement of claim 5 further comprising an area of thermally conductive material on the top surface of the substrate corresponding to locations of the vias.
8. The arrangement of claim 6 or 7 wherein the vias extend from the thermally conductive material to the bottom surface of the substrate.
9. The method or arrangement of any preceding claim wherein the vias are arranged in an array such that each via not at an edge of the array is located in a position equidistant from the six closest surrounding vias.
10. The method or arrangement of any preceding claim wherein the substrate comprises a plurality of horizontal layers, each layer having first and second portions and first and second vias.
11. The method or arrangement of any preceding claim wherein the thermally conductive material is copper.
12. A method substantially as hereinbefore described and with reference to the drawings.
13. An arrangement substantially as hereinbefore described and with reference to the drawings.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| GB9709273A GB2325082A (en) | 1997-05-08 | 1997-05-08 | Thermal via arrangement |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| GB9709273A GB2325082A (en) | 1997-05-08 | 1997-05-08 | Thermal via arrangement |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| GB9709273D0 GB9709273D0 (en) | 1997-06-25 |
| GB2325082A true GB2325082A (en) | 1998-11-11 |
Family
ID=10811943
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| GB9709273A Withdrawn GB2325082A (en) | 1997-05-08 | 1997-05-08 | Thermal via arrangement |
Country Status (1)
| Country | Link |
|---|---|
| GB (1) | GB2325082A (en) |
Cited By (10)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| WO2006119756A1 (en) * | 2005-05-12 | 2006-11-16 | Conti Temic Microelectronic Gmbh | Printed circuit board |
| EP2276329A1 (en) | 2009-07-16 | 2011-01-19 | ABB Research Ltd. | Electronic circuit board with a thermal capacitor |
| US8067840B2 (en) | 2006-06-20 | 2011-11-29 | Nxp B.V. | Power amplifier assembly |
| WO2014179516A1 (en) * | 2013-05-01 | 2014-11-06 | Microsoft Corporation | Cooling integrated circuit packages from below |
| CN106061099A (en) * | 2016-06-28 | 2016-10-26 | 广东欧珀移动通信有限公司 | Printed circuit board and mobile terminal having the same |
| US9589865B2 (en) * | 2015-07-28 | 2017-03-07 | Avago Technologies General Ip (Singapore) Pte. Ltd. | Power amplifier die having multiple amplifiers |
| US9601405B2 (en) | 2015-07-22 | 2017-03-21 | Avago Technologies General Ip (Singapore) Pte. Ltd. | Semiconductor package with an enhanced thermal pad |
| US9997428B2 (en) | 2015-07-14 | 2018-06-12 | Avago Technologies General Ip (Singapore) Pte. Ltd. | Via structures for thermal dissipation |
| US10129972B2 (en) | 2015-10-30 | 2018-11-13 | Avago Technologies International Sales Pte. Limited | Frame elements for package structures comprising printed circuit boards (PCBs) |
| US10236239B2 (en) | 2015-01-29 | 2019-03-19 | Avago Technologies International Sales Pte. Limited | Apparatus and semiconductor structure including a multilayer package substrate |
Citations (8)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| WO1981003734A1 (en) * | 1980-06-19 | 1981-12-24 | Digital Equipment Corp | Heat pin integrated circuit packaging |
| US4535385A (en) * | 1983-04-22 | 1985-08-13 | Cray Research, Inc. | Circuit module with enhanced heat transfer and distribution |
| US4729061A (en) * | 1985-04-29 | 1988-03-01 | Advanced Micro Devices, Inc. | Chip on board package for integrated circuit devices using printed circuit boards and means for conveying the heat to the opposite side of the package from the chip mounting side to permit the heat to dissipate therefrom |
| US4942076A (en) * | 1988-11-03 | 1990-07-17 | Micro Substrates, Inc. | Ceramic substrate with metal filled via holes for hybrid microcircuits and method of making the same |
| WO1992003034A1 (en) * | 1990-08-07 | 1992-02-20 | Cirqon Technologies Corporation | Heat-conductive metal ceramic composite material panel system for improved heat dissipation |
| US5258887A (en) * | 1992-06-15 | 1993-11-02 | Eaton Corporation | Electrical device cooling system using a heat sink attached to a circuit board containing heat conductive layers and channels |
| WO1994029900A1 (en) * | 1993-06-09 | 1994-12-22 | Lykat Corporation | Heat dissipative means for integrated circuit chip package |
| US5467251A (en) * | 1993-10-08 | 1995-11-14 | Northern Telecom Limited | Printed circuit boards and heat sink structures |
-
1997
- 1997-05-08 GB GB9709273A patent/GB2325082A/en not_active Withdrawn
Patent Citations (8)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| WO1981003734A1 (en) * | 1980-06-19 | 1981-12-24 | Digital Equipment Corp | Heat pin integrated circuit packaging |
| US4535385A (en) * | 1983-04-22 | 1985-08-13 | Cray Research, Inc. | Circuit module with enhanced heat transfer and distribution |
| US4729061A (en) * | 1985-04-29 | 1988-03-01 | Advanced Micro Devices, Inc. | Chip on board package for integrated circuit devices using printed circuit boards and means for conveying the heat to the opposite side of the package from the chip mounting side to permit the heat to dissipate therefrom |
| US4942076A (en) * | 1988-11-03 | 1990-07-17 | Micro Substrates, Inc. | Ceramic substrate with metal filled via holes for hybrid microcircuits and method of making the same |
| WO1992003034A1 (en) * | 1990-08-07 | 1992-02-20 | Cirqon Technologies Corporation | Heat-conductive metal ceramic composite material panel system for improved heat dissipation |
| US5258887A (en) * | 1992-06-15 | 1993-11-02 | Eaton Corporation | Electrical device cooling system using a heat sink attached to a circuit board containing heat conductive layers and channels |
| WO1994029900A1 (en) * | 1993-06-09 | 1994-12-22 | Lykat Corporation | Heat dissipative means for integrated circuit chip package |
| US5467251A (en) * | 1993-10-08 | 1995-11-14 | Northern Telecom Limited | Printed circuit boards and heat sink structures |
Cited By (11)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| WO2006119756A1 (en) * | 2005-05-12 | 2006-11-16 | Conti Temic Microelectronic Gmbh | Printed circuit board |
| US7804030B2 (en) | 2005-05-12 | 2010-09-28 | Conti Temic Microelectronics Gmbh | Printed circuit board |
| US8067840B2 (en) | 2006-06-20 | 2011-11-29 | Nxp B.V. | Power amplifier assembly |
| EP2276329A1 (en) | 2009-07-16 | 2011-01-19 | ABB Research Ltd. | Electronic circuit board with a thermal capacitor |
| WO2014179516A1 (en) * | 2013-05-01 | 2014-11-06 | Microsoft Corporation | Cooling integrated circuit packages from below |
| US10236239B2 (en) | 2015-01-29 | 2019-03-19 | Avago Technologies International Sales Pte. Limited | Apparatus and semiconductor structure including a multilayer package substrate |
| US9997428B2 (en) | 2015-07-14 | 2018-06-12 | Avago Technologies General Ip (Singapore) Pte. Ltd. | Via structures for thermal dissipation |
| US9601405B2 (en) | 2015-07-22 | 2017-03-21 | Avago Technologies General Ip (Singapore) Pte. Ltd. | Semiconductor package with an enhanced thermal pad |
| US9589865B2 (en) * | 2015-07-28 | 2017-03-07 | Avago Technologies General Ip (Singapore) Pte. Ltd. | Power amplifier die having multiple amplifiers |
| US10129972B2 (en) | 2015-10-30 | 2018-11-13 | Avago Technologies International Sales Pte. Limited | Frame elements for package structures comprising printed circuit boards (PCBs) |
| CN106061099A (en) * | 2016-06-28 | 2016-10-26 | 广东欧珀移动通信有限公司 | Printed circuit board and mobile terminal having the same |
Also Published As
| Publication number | Publication date |
|---|---|
| GB9709273D0 (en) | 1997-06-25 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| US6580611B1 (en) | Dual-sided heat removal system | |
| US7180745B2 (en) | Flip chip heat sink package and method | |
| US5552633A (en) | Three-dimensional multimodule HDI arrays with heat spreading | |
| US5646373A (en) | Apparatus for improving the power dissipation of a semiconductor device | |
| US5172301A (en) | Heatsink for board-mounted semiconductor devices and semiconductor device assembly employing same | |
| JP3241639B2 (en) | Multi-chip module cooling structure and method of manufacturing the same | |
| US6670699B2 (en) | Semiconductor device packaging structure | |
| TW560229B (en) | Power converter package with enhanced thermal management | |
| US6156980A (en) | Flip chip on circuit board with enhanced heat dissipation and method therefor | |
| KR100523498B1 (en) | Parallel-plate/pin-fin hybrid copper heat sink for cooling high-powered microprocessor | |
| US6243269B1 (en) | Centralized cooling interconnect for electronic packages | |
| US5982630A (en) | Printed circuit board that provides improved thermal dissipation | |
| JPS62123747A (en) | Mounting of semiconductor chip and electrical contact device | |
| US7602618B2 (en) | Methods and apparatuses for transferring heat from stacked microfeature devices | |
| US6657864B1 (en) | High density thermal solution for direct attach modules | |
| JP2006210892A (en) | Semiconductor device | |
| US6101094A (en) | Printed circuit board with integrated cooling mechanism | |
| US20080017402A1 (en) | Substrate module with high thermal conductivity and its fabrication method of same | |
| GB2325082A (en) | Thermal via arrangement | |
| US6014314A (en) | Package structure of a multi-chip module | |
| KR101008772B1 (en) | Thermal-conductive substrate package | |
| US6115255A (en) | Hybrid high-power integrated circuit | |
| CA2075593A1 (en) | Semiconductor chip module and method for manufacturing the same | |
| US6836409B1 (en) | Component cooling in electronic devices | |
| JPH1093250A (en) | Heat-dissipating structure of printed wiring board |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| WAP | Application withdrawn, taken to be withdrawn or refused ** after publication under section 16(1) |