GB2322965A - Bipolar transistors - Google Patents

Bipolar transistors Download PDF

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Publication number
GB2322965A
GB2322965A GB9714859A GB9714859A GB2322965A GB 2322965 A GB2322965 A GB 2322965A GB 9714859 A GB9714859 A GB 9714859A GB 9714859 A GB9714859 A GB 9714859A GB 2322965 A GB2322965 A GB 2322965A
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emitter
substrate
epitaxial layer
emitter contact
contact area
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GB2322965B (en
GB9714859D0 (en
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Hideki Suzuki
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NEC Corp
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NEC Corp
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66234—Bipolar junction transistors [BJT]
    • H01L29/66272—Silicon vertical transistors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/04—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their crystalline structure, e.g. polycrystalline, cubic or particular orientation of crystalline planes
    • H01L29/045—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their crystalline structure, e.g. polycrystalline, cubic or particular orientation of crystalline planes by their particular orientation of crystalline planes
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/70—Bipolar devices
    • H01L29/72—Transistor-type devices, i.e. able to continuously respond to applied control signals
    • H01L29/73—Bipolar junction transistors
    • H01L29/732—Vertical transistors
    • H01L29/7322—Vertical transistors having emitter-base and base-collector junctions leaving at the same surface of the body, e.g. planar transistor

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  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • General Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Ceramic Engineering (AREA)
  • Manufacturing & Machinery (AREA)
  • Chemical & Material Sciences (AREA)
  • Crystallography & Structural Chemistry (AREA)
  • Bipolar Transistors (AREA)
  • Drying Of Semiconductors (AREA)

Abstract

The transistor comprises a semiconductor substrate 1 with a major surface 1A and an epitaxial layer 4 formed on the major surface of the substrate. The major surface of the substrate is tilted by a tilt angle ?with respect to a specific crystal plane of the substrate around a tilt axis. The tilt axis is located in the major surface. The epitaxial layer has a tendency to be etched along the specific crystal plane of the substrate. The transistor has an emitter region 18, a base region 15, and an emitter contact 17. The emitter and base regions are formed in the epitaxial layer. The emitter contact is formed to be contacted with the emitter region at an emitter contact area 3a of the epitaxial layer. The emitter contact area has an elongated plan shape. The longitudinal axis of the emitter contact area is directed along the tilt axis. The specific crystal plane of the substrate is typically the (111)-plane of a single-crystal silicon.

Description

2322965 SEMICONDUCTOR DEVICE AND FABRICATION METHOD THEREOF The present
invention relates to a semiconductor device and more particularly, to a semiconductor device with a bipolar transistor or bipolar transistors the emitter and base regions of which are formed in an epitaxial layer by the self-aligned process technology, and a fabrication method of the device.
Typically, as arae-scale intearated shown in Fig. 3, a lot of identical circuit (LSI) chips 120 are fabricated on a single-crystal silicon substrate or wafer 101. The rectangular chips 120 are then separated by cutting the wafer 101 along scribing lines 119. The scribing lines 119 are drawn in parallel or perpendicular to a primary orientation flat 102 of the wafer 101.
For bipolar LSIs, generally, it is said that the wafer 101 has a chief surface 101A directed along the direction of (1111; in other words, the chief surface 101A off the wafer 101 has a crystal plane of (111) - This is because the etch rate along the (Ill]-direction is the smallest among -I- those along any other directions in silicon material.
Practically, however, as shown in Figs. 1 and 2, the chief surface 101A of the wafer 101 is tilted by a small angle e with respect to the (Ill)plane 130 around a tilt axis 131- Here, the axis 131 is defined as a straight line that is perpendicular to the orientation flat 102, parallel to the chief surface 101A, and penetrates the center of the flat 102. Although the tilt angle 0 is designed as necessary, it is typically 4'.
The reference character N indicates a normal of the chief surface 101A.
The tilting of the chief surface 101A with respect to the (Ill)-plane 130 is necessary due to the following reason.
Specifically, for bipolar LSIs, an epitaxial layer (not shown) is grown on the chief surface 101A of the wafer 101, and emitter and base regions of bipolar transistors are formed in this epitaxial layer. A patterned buried layer serving as a sub-collector region is formed in the vicinity of the interface of the substrate 101 and the epitaxial layer To place or overlay necessa ry masks onto the substrate 101 with high accuracy during subsequent processes, the patterns formed on the chief surface 101A of the substrate 101 need to be identically reflected on the surface of the epitaxial layer. However, the resultant patterns on the surface of the epitaxial layer tend to be shifted or distorted with respect to the patterns on the surface 101A of the substrate 101 due to the crystal orientation difference, which is termed the "'pattern shift" or "pattern distortion". The above tilting of the chief surface 101A solves this problem.
Fig. 4 shows a partial cross-section of a conventional npn-type bipolar transistor formed in a conventional bipolar LSI. In Fig. 4, the chief surface 101A of the single-crystal silicon substrate or wafer 101 has a crystal plane tilted by 4" with respect to the (111)-plane 130 around the tilt axis 131, which is described above. As shown in Fig. 4, an n-type buried layer 121 serving as a sub-collector region is selectively formed in the surface region of the substrate 101. An n-type epitaxial layer 104 is formed on the chief surface 101A of the substrate 101 to cover the n'-type buried layer 121In the epitaxial layer 104, an n-tYPe emitter region 20 118, a p- type base region 115, and a p-type graft base region 113 are formed. The emitter region 118 is surrounded by the base region 115 and is entirely overlapped with the base region 115. The inner end of the graft base region 113 is connected to the outer end of the base region 11S.
A silicon dioxide (Si02) layer 105 is selectively formed on the exposed area of the epitaxial layer 104. A ptype base contact 112 is formed on the p-type graft base region 113, which is located in a window of the layer 105.
-h boron The base contact 12 is made of polysilicon doped Wit.
(S).
A p-type base contact 106 is formed on the SiO2 layer to be contacted with the underlying base contact 112. The base contact 106 is made of polysilicon doped with boron.
An interlayer dielectric layer 107 is formed on the exposed area of the SiO2 layer 105 to cover the base contact 106.
A window 108 is formed on the base region 115 by the interlayer dielectric layer 107 and the base contact 106. In the window 108, a sidewall spacer 109, Which is made of silicon nitride (Si3N4), is formed an the side faces of the base contact 106 and the interlayer dielectric layer 107.
Another sidewall spacer 116, which is made of SiAl is formed on the side and bottom faces of the sidewall spacer 109. A SiO2 layer 114 is formed on the periphery of the base region 105 to be contacted with the graft base region 113 and the base contact 112.
An n-type emitter contact 117, which is made of polysilicon doped with arsenic (As), is formed on the emitter region 118 in the window 108- The emitter contact 117 is contacted with the emitter region 118, the SiO2 layer 114, the sidewall spacers 109 and 116, and the interlayer dielectric layer 107.
The reference numeral 103a in Fig- 4 indicates the contact area of the emitter contact 117 with the emitter region 118 or epitaxial layer 104. The contact area 103a typically has a rectangular plan shape.
The npn-type bipolar transistor shown in Fig. 4 is laid out on the wafer 101 in such a way that the rectangular emitter contact area 103a of the bipolar transistor in each chip 120 is directed in parallel 'or -perpendicular to the orientation flat 102 (or, the tilt axis 131), as schematically shown in Fig. 2. The emitter contact area 103a has a length L and a width W. This layout is adopted for the purpose of increasing the packing density on the chip 120 as high as possible.
In the fabrication process sequence of the npn-type bipolar transistor in Fig. 4, the SiO2 layer 114 is formed on the epitaxial layer 104 and then, it is selectively etched in the window 108 to uncover the surface of the epitaxial layer 104. During this etching process, the surface 104A of the epitaxial layer 104 tends to be etched along the (iii)-plane, i.e., along the direction perpendicular to the (111]- direction due to the orientation dependency of the etch rate. As a result, the surface 104A tends to have irregularity like saw-teeth in cross section, as schematically shown in Figs. 5 and 6.
Fig. 5 corresponds to the transistor the rectangular contact area 103a of which is directed along the orientation flat 102. Fig. 6 corresponds to the transistor the rectangular contact area 103a of which is directed perpendicular to the orientation flat 102.
If the surface 104A of the epitaxial layer 104 is overetched, the surface 104A tends to be inclined with respect to its original surface, as shown in Figs. 7 and B. The resultant inclined surface is directed along the (111)plane. The maximum depth of the resultant inclined surface will be d, for the rectangular contact area 103a which is parallel to the orientation flat 102, as shown in Fig. 7. The resultant maximum depth will be d, for therectangular contact area 103a which is perpendicular to the orientation flat 102, where di > d,-, as shown in Fig- 8.
In other words, the resultant max imum depth of the epitaxial layer 104 increases as the length of the rectangular contact area 103a along the orientation flat 102 becomes longer.
With the conventional bipolar transistor shown in Fig 4, as described above, the active base region 115 and the emitter region 118 are formed by doping impurities into the epitaxial layer 104 through the etched surface 104A of the layer 104. Therefore, if the rectangular contact area 103a is laid out on the wafer or substrate 101 in such a way that the longitudinal axis of the area 103a is directed along the orientation flat 102, the bipolar transistor tends to have a greater surface irregularity than the bipolar transistor where the longitudinal axis of the contact area 103a is directed perpendicular to the orientation flat 102.
This surface irregularity on the surface 104A leads to the thickness fluctuation or variation of the base region 115, thereby degrading the collector-to-emitter withstand voltage and/or increasing the dc current gain factor hFr-.
Also, due to the different surface irregularities on the etched surfaces 104A as shown in Figs. 5 and 6, the transistors on the wafer 101 tend to have different characteristics dependent upon the layout direction.
Further, if the maximum etched depth of the surface 104A of the epitaxial laver 104 becomes large, the level of the base region 115 will be lower with respect to the original surface of the layer 104. This means that the base region 115 is shifted toward the underlying buried layer 121 with respect to the original surface of the epitaxial layer 104, resulting in increase in collector-to-base capacitance.
Alternately, since the contact area of the graft base region 113 and the base region 115 is decreased due to the shift of the base region 115, the base resistance will be raised. Consequently, the operation speed of the transistors will be reduced.
Accordingly, 'an object of at least the preferred embodiments of the present invention is to provide a semiconductor device and a fabrication method thereof' in which the degradation in collector-to-emitter withstand voltage of a bipolar transistor and the increase in dc current gain factor o.f the transistor is suppressed.
Another such object.. is to provide a semiconductor device and a fabrication method thereof that improve the reliability in operation.
Still another such object is to provide a semiconductor device and a fabrication method thereof that raise the operation speed of a bipolar transistor.
A further.such object is to provide a semiconductor device and a fabrication method thereof that suppresses the fluctuation in bipolar transistor characteristics independent of the layout orientation on a semiconductor substrate and enhances the circuit design margin.
In a first aspect, the present invention provides a semiconductor device comprising a semiconductor substrate, a surface of said substrate being tilted about a tilt axis by a tilt angle with respect to a specific crystal plane of said substrate, said tilt axis being located in the plane of said surface, an epitaxial layer formed on said surface of said substrate, said epitaxial layer having preferred etching direction aligned along said specific crystal plane of said substrate, and a bipolar transistor, said transistor having an emitter region, a base region, and an emitter contact, said emitter and base regions being formed in said epitaxial layer, said emitter contact being formed to contact said emitter region on an emitter contact area of said epitaxial layer, said emitter contact area having an elongated shape, the longitudinal axis thereof being aligned substantially parallel to said tilt axis.
According to a preferred embodiment of the first aspect of the present invention, a semiconductor device is provided. This device includes a semiconductor substrate with a chief surface, an epitaxial layer formed on the chief surface of the substrate, and a bipolar transistor formed at the epitaxial layer.
The chief surface of the substrate is tilted by a tilt angle with respect to a specific crystal plane of the substrate around a tilt axis. The tilt axis is located in the chief surface.
The epitaxial layer has a tendency to be etched along the specific crystal plane of the substrate.
The transistor has an emitter region, a base region, and an emitter contact.
The emitter and base regions are formed in the epitaxial layer. The emitter contact is formed to be contacted with the emitter region at an emitter contact area of the epitaxial layer. The emitter contact area has an elongated plan shape.
The longitudinal axis of the emitter contact area is directed along the tilt axis.
With the semiconductor device according to the f irst aspect of the present invention, the epitaxial layer has a tendency to be etched along the specific crystal plane which is tilted with respect to the chief surface of the substrateTherefore, the etched surface in the emitter contact area of the epitaxial layer tends to be directed along the specific crystal plane of the substrate which is tilted with respect to the chief surface of the substrate- on the other hand, since the longitudinal axis of the elongated emitter contact area, of the bipolar transistor is directed along the tilt axis, the lateral axis of the emitter contact area is directed perpendicular to the tilt axis. This means that the resultant etched depth in the emitter contact area is minimized.
As a result, the degradation in col lector-to- emitter withstand voltage of the bipolar transistor and the increase in dc current gain factor thereof are suppressed. Th.Ls improves the reliability in operation of the semi-conductor device.
Also, since the resultant etched depth in the emitter contact area is minimized, the level of the base region i not lowered with respect to its designed position. There-fore the increase in both collector-to-base capacitance and base resistance is suppressed, which raises the operation speed of the transistor.
In a preferred embodiment of the semiconductor device according to the first aspect, the specific crystal plane of the substrate is selected in such a way that the etch rate of the substrate is minimized. Typically, the specific crystal plane is the (Ill)-plane of a single-crystal silicon.
In this case, the advantages of the device according to the first aspect are more effectively realized.
In a second aspect, the present invention provides a semiconductor device comprising a semiconductor substrate, a surface of said substrate being tilted about a tilt axis by a tilt angle with respect to a specific crystal plane of said substrate, said tilt axis being located in the plane of said surface, an epitaxial layer formed on said surface of said substrate, said epitaxial layer having a preferred etching direction aligned along said specific crystal plane of said substrate, a first bipolar transistor, said first transistor having a first emitter region, a first base region, and a first emitter contact, said first emitter region and said first base region being formed in said epitaxial layer, said first emitter contact being formed to contact said first emitter region on a first emitter contact area of said epitaxial layer, said first emitter contact area having an elongated shape, the longitudinal axis thereof being aligned in a first 20 direction, said first direction forming an angle in the range from 35' to 550 with respect to said tilt axis, and a second bipolar transistor, said second transistor having a second emitter region, a second base region, and a second emitter contact, said second emitter region and said second base region being formed in said epitaxial layer, said second emitter contact being formed to contact said second emitter region on a second emitter contact area of said epitaxial layer, said second emitter contact area having an elongated shape; the longitudinal axis of said second emitter contact area being aligned in a second direction, said second direction forming an angle in the range from 1250 to 145' or from -35' to -55' with respect to said tilt axis.
According to a preferred embodiment of the second aspect of the present invention, a semiconductor device is provided including a semiconductor substrate with a chief surface, an epitaxial layer formed on the chief surface of the substrate, and first and second bipolar transistors formed at the epitaxial layer.
The chief surface of the substrate is tilted by a tilt angle with respect to a specific crystal plane of the substrate around a tilt axis. The tilt axis is located in the chief surface.
The epitaxial layer has a tendency to be etched along the specific crystal plane of the substrate.
The first transistor has a first emitter region, a first base region, and a first emitter contact. The first emitter region and the first base region are formed in the epitaxial layer. The first emitter contact is formed to be contacted with the first emitter region at a first emitter contact area of the epitaxial layer. The first emitter contact area has an elongated plan shape.
The second transistor has a second emitter region, a second base region, and a second emitter contact. The second emitter region and the second base region are formed in the epitaxial layer. The second emitter contact is formed to be contacted with the second emitter region at a second emitter contact area orE the epitaxial layer. The second emitter contact area has an elongated plan shape.
The longitudinal axis of the first emitter contact area is directed in a first direction. The first direction forms an angle ranging from 35" to 55" with respect to the tilt axis.
The longitudinal axis of the second emitter contact area is directed in a second direction. The second direction forms an angle ranging from 1250 to 145' or from -35' to -55 with respect to the tilt axis.
With the semiconductor device according to the second aspect of the present invention, the longitudinal axis of the elongated first eraitter contact area of the first bipolar transistor is directed in the first direction. The first -13- direction forms an angle ranging from 350 to 55" with respect to the tilt axis.
The longitudinal axis of the elongated second emitter contact area of the second bipolar transistor is directed in the second direction. The second direction forms an angle ranging from 125' to 145' or from -35 to -550 with respect to the tilt axis.
Therefore, the lengths of the first and second emitter contact areas along a direction perpendicular to the 10 tilt axis are approximately equal.
Consequently, the fluctuation in transistor characteristics is suppressed between the first and second bipolar transistors, which is independent of the layout orientation of the first and second transistors on the substrate. This enhances the circuit design margin- At the same time, because none of the first and second emitter contact areas of the first and second transistors is excessively etched, the reliability in operation is improved.
The reason that the angle of the first direction ranges from 35' to 55' with respect to the tilt axis and that the angle of the second direction ranges from 125 to 145 or from -35 to -55 with respect to the tilt axis is as follows.
14 If the angle of the first direction is not in the range from 35 to 55' and the angle of the second direction is not in the range from 1250 to 145' nor from -35" to -,550 with respect to the tilt axis, the above advantages of the device according to the first second aspect are not sufficiently obtained.
In a preferred embodiment of the semiconductor device according to the second aspect, the specific crystal plane of the substrate is selected in such a way that the etch rate of the substrate is minimized. Typically, the specific crystal plane is the (Ill)-plane of a single-crystal silicon.
In this case, the advantages of the device according to the second aspect are more effectively realized.
In another preferred embodiment of the semiconductor device according to the second aspect, the first direction forms an angle of approximately 45' with respect to the tilt axis. The second direction forms an angle of approxiMately 1350 or -450 with respect to the tilt axis.
In this case, the advantages of the device according to the second aspect are most effectively realized.
In a third aspect, the present invention provides A method of fabricating a semiconductor device, said method comprising the steps of preparing a semiconductor substrate, a surface of said substrate being tilted about a tilt axis by a tilt angle with respect to a specific crystal plane of said substrate, said tilt axis being located in the plane of said surface, forming an epitaxial layer on said surface of said substrate, said epitaxial layer having a preferred etching direction aligned along said specific crystal plane of said substrate, and forming a bipolar transistor on said epitaxial layer, said transistor having an emitter region, a base region, and an emitter contact, said emitter and base regions being formed in said epitaxial layer, said emitter contact contacting said emitter region on an emitter contact area of said epitaxial layer, and said emitter contact area having an elongated shape, the longitudinal axis thereof being aligned substantially parallel to said tilt axis.
According to a preferred embodiment of the third aspect of the present invention, a fabrication method of a semiconductor device is provided.
In this method, as a first step, a semiconductor substrate with a chief surface is prepared. The chief surface of the substrate is tilted by a tilt angle with respect to a specific crystal plane of the substrate around a tilt axis. The tilt axis is located in the chief surface.
As a second step, an epitaxial layer is formed on the chief surface of the substrate. The epitaxial layer has a tendency to be etched along the specific crystal plane of the 10 substrate.
As a third step, a bipolar transistor is formed at the epitaxial layer. The transistor has an emitter region, a base region, and an emitter contact. The emitter and base regions are formed in the epitaxial layer. The emitter contact is formed to be contacted with the emitter region at an emitter contact area of the epitaxial layer. The emitter contact area has an elongated plan shape.
The longitudinal axis of the emitter contact area is directed along the tilt axis.
1 7- In a fourth aspect the present invention provides a method of fabricating a semiconductor device comprising the steps of preparing a semiconductor substrate, a surface of said substrate being tilted about a tilt axis by a tilt angle with respect to a specific crystal plane of said substrate, said tilt axis being located in the plane of said surface, forming an epitaxial layer on said surface of said substrate, said epitaxial layer having a preferred etching direction aligned along said specific crystal plane of said substrate, and forming a first bipolar transistor and a second bipolar transistor on the epitaxial layer, said first transistor having a first emitter region, a first base region, and a first emitter contact, said first emitter region and said first base region being formed in said epitaxial layer, said first emitter contact contacting said first emitter region on a first emitter contact area of said epitaxial layer, said first emitter contact area having an elongated shape, said second transistor having a second emitter region, a second base region, and a second emitter contact, said second emitter region and said second base region being formed in said epitaxial layer, and said second emitter contact contacting said second emitter region on a second emitter contact area of said epitaxial layer, said second emitter contact area having an elongated shape, wherein the longitudinal axis of said first emitter contact area is aligned in a first direction which forms an angle in the range from 350 to 55' with respect to said tilt axis, and the longitudinal axis of said second emitter contact area is aligned in a second direction, where said second direction forms an angle in the range from 125' to 145' or from -35' to -55" with respect to said tilt axis.
According to a preferred embodiment of the fourth aspect of the present invention, another fabrication method of a semiconductor device is provided.
In this method, as a first step, a semiconductor substrate with a chief surface is prepared. The chief surface of the substrate is tilted by a tilt angle with respect to a specific crystal plane of the substrate around a tilt axis.
The tilt axis is located in the chief surface.
As a second step, an epitaxiial layer is formed on the chief surface of the substrate. The epitaxial layer has a tendency to be etched along the specific crystal plane of the substrate.
As a third step, first and second bipolar transistors are formed at the epitaxial layer.
The first transistor has a first emitter region, a base region, and a first emitter contact. The first emitter region and the first base region are formed in the epitaxial layer. The first emitter contact is formed to be contacted with the first emitter region at a first emitter contact area of the epitaxial layer. The first emitter contact area has an elongated plan shape.
The second transistor has a second emitter region, a second base region, and a second emitter contact. The second emitter region and the second base region. are formed in the epitaxial layer. The second emitter contact is formed to be contacted with the second emitter region at a second emitter contact area of the epitaxiial layer. The second emitter contact area has an elongated plan shape.
The longitudinal axis of the first emitter contact area is directed in a first direction. The first direction forms an angle ranging from 35 to 550 with respect to the tilt axis.
The longitudinal axis of the second emitter contact area is directed in a second direction. The second direction forms an angle ranging from 125' to 145' or from -35' to -55' with respect to the tilt axis.
Preferred features of the present invention will now be described, purely by way of example only, with reference to the accompanying drawings, in which:- Fig. 1 is a schematic side view of a semiconductor substrate or wafer an which conventional bipolar transistors are fo=ed, which shows the relationship among -the chief surface, 'the crystal plane, and the tilt axis. of the substrate.
Fig. 2 is a schematic plan view of the semiconductor substrate or wafer in Fig. 1, which show5 the relationship among the emitter contact areas of the bipolar transistors formed on the substrate or wafer, and the tilt axis and the orientation flat of the substrate.
Fig. 3 is a schematic plan view of the semiconductor substrate or wafer in Fig. 1, which shows the layout of the LS1 chips on the walfer.
Fig. 4 is a schematic, partial cross-sectional view of one of the conventional bipolar transistors along the line IV-IV in Fig. 2.
Fig. 5 is a schematic, enlarged, partial crosssectional view of the conventional bipolar transistor in Fig. 4, which shows the state of the etched surface of the 10 epitaxial layer Fig. 6 sectional 4, which is a schematic, enlarged, partial crossview of the conventional bipolar transistor in Fig. shows the state of the etched surface of theepitaxial layer.
Fig. 7 is a schematic, enlarged, partial crosssectional view of the conventional bipolar transistor in Fig. 4, which shows the state of the overetched surface of the epitaxial layer.
Fig- 8 is a schematic, enlarged, partial cross sectional view of the conventional bipolar transistor in Fig.
4, which shows the state of the overetched surface of the epitaxial layer.
Fig. 9 is a schematic side view of a semiconductor substrate or wafer on which bipolar transistors according to a first embodiment are formed, which shows the relationship among the chief surface, the crystal plane, and the tilt axis of the substrate.
Fig. 10 is a schematic plan view of the seiniconductor substrate or walffer in Fig. 9, which shows the relationship among the emitter contact areas of the bipolar transistors according to the first embodiment formed on the substrate or wafer, and the tilt axis and the orientation flat of the substrate.
Fig. 11 is a schematic, partial cross-sectional view of one of the bipolar transistors along the line XI-XI in Fig. 10.
Figs. 12A to 12K are schematic, partial crosssectional views of the bipolar transistor according to the first embodiment, which show its fabrication method, respectively.
Fig. 13 is a schematic plan view of a semiconductor substrate or wafer, which shows the relationship among the emitter contact areas of the bipolar transistors according to a second embodiment, and the tilt axis and the orientation flat of the substrate. Figs. 9 and 10 schematically show a P-type single- crystal silicon
substrate or wafer 1, on which a plurality of semiconductor devices according to a first embodiment are formed. The wafer 1 has a primary orientation flat 2.
A chief surface 1A of the wafer I is tilted by a small angle 0 with respect to the (111)-Plane 30 around a tilt axis 31. Here, the axis 31 is defined as a straight line that is perpendicular to the orientation flat 2, parallel to the chief surface 1A, and penetrates the center of the flat 2. The tilt angle 6 is set as 40. The reference character N indicates a normal of the chief surface 1A.
Each of the semiconductor devices according to the first embodiment has an npn-type bipolar transistor as shown in Fig. 11. The transistor is substantially the same in configuration as the transistor in Fig. 4.
In Fig. 11, the chief surface 1A of the single crystal silicon substrate or wafer 1 has a crystal plane tilted by 4" with respect to the (111)-plane 30 around the tilt axis 31, which is described above.
An n-type buried layer 21 serving as a sub-collector region is selectively formed in the surface region of the substrate 1. An n-type epitaxial layer 4 is formed on the chief surface JA of the substrate 1 to cover the n-type buried layer 21.
In the epitaxial layer 4, an n-type emitter region 18, a p-type base region 15, and a p-type graft base region 13 are formed. The emitter region 18 is surrounded by the base region 15 and is entirely overlapped with the base region 15.
The inner end of the graft base region 13 is connected to the outer end of the base region 15.
A Si0_, layer 5 is selectively formed an the exposed area of the epitaxial layer 4. A p-type base contact 12 is formed on the p-type graft base region 13, which is located in a window of the layer 5. The base contact 12 is made of polysilicon doped with boron.
A p-type base contact 6 is formed on the Si02 layer 5 to be contacted with the underlying base contact 12. The base contact 6 is made of polysilicon doped with boron.
An interlayer dielectric layer 7 is formed on the exposed area of %the SiO2 layer S to cover the base contact 6.
A window 8 is formed on the base region 15 by the interlayer dielectric layer 7 and the base contact 6. In the window 8, a sidewall spacer 9, which is made Of SiAl iS formed on the side faces of the base contact 6 and the interlayer dielectric layer 7. Another sidewall spacer 16, which is made of Si3N4, is formed on the side and bottom faces of the sidewall spacer 9. A SiO2 layer 14 is formed on the periphery of the base region 5 to be contacted with the graft base region 13 and the base contact 122.
An n-type emitter contact 17, which is made of polysilicon doped with arsenic, is formed on the emitter region 18 in the window 8. The emitter contact 17 is contacted with the emitter region 18, the SiO2 layer 14, the sidewall spacers 9 and 16, and the -interlayer dielectric layer 7.
The reference numeral 3a in Fig- 11 indicates t-he contact area of the emitter contact 17 with the emitter region 18 or epitaxial layer 4. Here, the contact area 3a has a rectangular plan shape.
The npn-type bipolar transistors shown in Fig. 11 are laid out on the wafer 1 in such a way that the longitudinal axis of the rectangular emitter contact areas 3a of the transistor in each chip is directed perperidicular to the orientation flat 102 (or, in parallel to the tilt axis 31), as schematically shown in Fig. 10. The emitter contact area 3a has a length L and a width W.
The bipolar transistor shown in Fig. 11 is fabricated by the following process steps.
First, as shown in Fig. 12A, the n-type buried layer 21 serving as a subcollector region is selectively formed in the surface region of the substrate I. The n-type epitaxial layer 4 is formed on the chief surface 1A of the substrate 1 to cover the buried layer 21.
Next, the SiO2 layer 5 is formed on the epitaxial laver 4 by thermal oxidation or Chemical Vapor Deposition (CVD) over the whole substrate 1. A polysilicon layer (not shown) is deposited on the SiO2 layer 5 by CVD and then, boron is doped into the polysilicon layer thus deposited, thereby forming the p-type polysilicon layer 6 on the SiO,. layer 5. The p-type polysilican layer 6 is then patterned by photolithography and etching, as shown in Fig. 12A.
The interlayer dielectric layer 7 is formed on the exposed SiO,, layer 5 to cover the p-type polysilicon base contact 6 for the purpose of surface planarization. The interlayer dielectric layer 7 may be formed by a SiOz layer, Si3N4 layer, or the combination of the stacked SiC:! and S-'31V4 sublayers. The state at this stage is shown in Fig. 12A.
Subsequently, the interlayer dielectric layer 7 and the p-type polysilicon layer 6 are selectively removed by dry etching, thereby forming a rectangular window 8. The window 8 uncovers the central part of the Si02 layer 5. The state at this stage is shown in Fig. 12B.
A Si3N4 layer (not shown) is deposited by CVD on the interlayer dielectric layer 7 to cover the window 8. The Si3N4 layer thus deposited is then etched back to thereby form the sidewall 9, as shown in Fig. 12C. The 5i3N4 sidewall 9 is located on the Sioz layer 5 and contacted with the side faces of the p-type polysilicon layer 6 and the interlayer dielectric layer 7.
Then, the 5i02 layer 5 and the Si3N4 sidewall 9 are selectively removed by wet etching using buffered hydrogen fluoride (HF) until the inner end 10 of the remaining Si02 layer 5 approximately accords with the outer end position of the p-type graft base region 13. Thus, the surface 4a of the epitaxial layer 4 is exposed in the window 8. The state at this stage is shown in Fig. 12D.
Following this, the non-doped polysilicon layer 11 is deposited by CVD on the interlayer dielectric layer 7 to cover the window 8. As shown in Fig. 12E, the layer 11 is contacted with the exposed surface 4A of the epitaxial layer 4, the inner end 10 of the remaining SiOz layer 5, the bottom face of the p-type polysilicon layer 6, and the exposed areas of the sidewall 9.
The assembly shown in Fig. 12E is then subjected to a heat treatment at a temperature of 800 C to 1000 C, thereby diffusing the boron atoms contained in the P-type polysilicon layer 6 into the non- doped polysilicon layer 11 and the epitaxial layer 4. Thus, the p-type Polysilican base contact 12 and the p-type graft base region 13 are famed. The state at this stage is shown in Fig. 12F.
Using the etch rate difference between non-doped polysilicon and borondoped polysilicon, the remaining nondoped polysilicon layer 11 is selectively removed by alkali etching using hydrazine while leaving the boron-doped polysilicon layer 12, as shown in Fig. 12G.
The Assembly shown in Fig. 12G is then subjected to thermal oxidation, thereby forming the Si02 layer 14 on the uncovered surface 4A of the epitaxial layer 4 and the uncovered inner end 10 of the p-type polysilican layer 12, as shown in Fig. 12H.
Boron is selectively ion-implanted into the epitaxial layer 4 through the SiOz layer 14 in the window 8. The implanted boron atoms into the layer 4 are then diffused vertically and laterally within the layer 4 by heat treatment at a temperature of 800 "C to 100 "C, thereby forming the ptype base region 15 in the layer 4. The state at this stage is shown in Fig. 12H.
29" A 5i3N4 layer (not shown) is 'deposited on the interlayer dielectric layer 7 by M to cover the window 8 and is then etched back, resulting in the Si3N4 sidewall 16 on the 5i02 layer 14, as shown in Fig. 121.
The Si02 layer 14 is then removed selectively by etching to have an opening uncovering the underlying surface 4A of the epitaxial layer 4. The opening has a width equal to the distance between the opposing bottom ends of the sidewall 16. The state at this stage is shown in Fig. 121.
The polysilicon layer 17 is deposited on the interlayer dielectric layer 7 by M to cover the window 8. The layer 17 is then doped with arsenic and patterned, thereby forming the n-type polysilicon emitter contact 17 on the uncovered surface 4A of the epitaxial layer 4. The state at this stage is shown in Fig. 12J.
The assembly in Fig. 12J is then subjected to heat treatment at a temperature of 800 "C to 1000 OC to thereby diffuse the arsenic atoms contained in the n-type polysilican emitter contact 17 into the underlying p-type base region 15.
Thus, the n-type emitter region 18 is formed in the p-type base region 15. The state at this stage is shown in Fig. 12K.
with the semiconductor device according to the first embodiment as shown in Fig. 11, the epitaxial layer 4 has a tendency to be etched along the specific crystal plane (i.e., the (Ill)-plane) which is tilted by 4'0 with respect to the chief surface IA of the substrate 1. Therefore, the etched surface in the emitter contact area 3a of the epitaxial layer 4 tends to be directed along the (111)-plane of the substrate 5 1.
On the other hand, since the longitudinal axis of the elongated emitter contact area 3a of the bipolar transistor is directed along the tilt axis 31, the lateral axis of the emitter contact area 3a is directed perpendicular to the tilt axis 31. This means that the resultant etched depth in the emitter contact area 3a is minimized (see Figs. 4 and 6).
As a result, the degradation in collector-toemitter withstand voltage of the bipolar transistor and the increase in dc current gain factor thereof are suppressed. This improves the reliability in operation of the semiconductor device.
Also, since the resultant etched depth in the emitter contact area 3a is minimized, the level of the base region 15 is not lowered toward the buried layer 21 with respect to its designed position. Therefore, the increase in both collectorto -base capacitance and base resistance is suppressed, which raises the operation speed of the transistor- For example, the collector-toemitter withstand voltage is raised from 4 to 5 v in the conventional one in Fig. 2 to 7 to 8V. The operation speed of the bipolar transistor is increased by approximately 5 to 30% with respect to the conventional one in Fig. 2.
Fig. 13 shows the layout of semiconductor devices with bipolar transistors according to a second embodiment.
In the second embodiment, unlike the first embodiment, the tilt axis 31 of the single-crystal silicon wafer or substrate 1 is set as shown in Fig. 13. Specifically, the tilt axis 31 forms an angle of 45' with respect to a straight line 32 perpendicular to the orientation flat 2 of -the wafer 1. The line 32 penetrates the center of the flat 2 and the center of the wafer 1 itself in the chief surface of the waf er 1 - Unlike the first embodiment, the chief surface 1A of the wafer I is tilted by the same angle of 40 as in the first embodiment around the tilt axis 31 with respect to the (111)plane.
As schematically shown in Fig. 13, a f irst npn-ty pe bipolar transistor is laid out on the wafer or substrate 1 in such a way that the longitudinal axis of a rectangular emitter contact area 3b of the first transistor is directed perpendicular to the orientation flat 2. The longitudinal axis of the emitter contact area 3b has an angle of 450 with respect to the tilt axis 31.
A second npn-type bipolar transistor is laid out an the wafer or substrate 1A in such a way that the longitudinal axis of a rectangular emitter contact area 3c of the second transistor is directed in parallel to the orientation flat 2. The longitudinal axis of the emitter contact area 3c has an angle of 135' with respect to the tilt axis 31.
The first and second transistors has the sa-me configuration as shown in Fig. 11.
With the semiconductor device according to the second embodiment, the longitudinal axis of the elongated emitt er contact area 3a of the first bipolar transistor is directed in the direction tilted by 450 with respect to the tilt axis 31, and the longitudinal axis of the elongated second emitter contact area 3b of the second bipolar transistor is directed in the direction tilted by 135' with respect to the tilt axis 31.
Therefore, the lengths Sb and Sc of the first and second emitter contact areas 3a and 3b along the direction perpendicular to the tilt axis 31 are equal to each other- Consequently, the fluctuation in transistor characteristics is suppressed between the first and second bipolar transistors, which is independent of the layout orientation of the first and second transistors On the substrate 1. This enhances the circuit design margin.
At, the same time, because none of the f irst and second emitter contact areas 3b and 3c of the first and second transistors is excessively etched, the reliability in operation is improved.
The angle of the longitudinal axis of the emitter contact area 3a may be any value ranging f rom 350 to 55 with respect to the tilt axis 31. The angle of the longitudinal axis of the emitter contact area 3b may be any value ranging from 125' to 145" or from -35 to -55" with respect to the tilt axis 31.
The angle between the tilt axis 31 and the str aight line 32 may be any value in the range of 45' 10 or 135 1011.
While the preferred forms of the present invention has been described, it is to be understood that modifications will be apparent to those skilled in the art without depart- ing f rom the scope of the invention as determined solely by the following claims.
-33 Each feature disclosed in this specification (which term includes the claims) and/or shown in the drawings may be incorporated in the invention independently of other disclosed and/or illustrated features.
The text of the abstract filed herewith is repeated here as part of the specification.
A semiconductor device is provided, in which the reliability in operation is improved. This device includes a semiconductor substrate with a chief surface, an epitaxial layer formed on the chief surface of the substrate, and a bipolar transistor formed at the epitaxial layer. The chief surface of the substrate is tilted by a tilt angle with respect to a specific crystal plane of the substrate around a tilt axis. The tilt axis is located in the chief surface. The epitaxial layer has a tendency to be etched along the specific crystal plane of the substrate. The transistor has an emitter region, a base region, and an emitter contact. The emitter and base regions are formed in the epitaxial layer. The emitter contact is formed to be contacted with the emitter region at an emitter contact area of the epitaxial layer. The emitter contact area has an elongated plan shape. The longitudinal axis of the emitter contact area is directed along the tilt axis. The specific crystal plane of the substrate is typically the (11 l)-plane of a single-crystal silicon.

Claims (12)

1. A semiconductor device comprising: (a) a semiconductor substrate; a surface of said substrate being tilted about a tilt axis by a tilt angle with 5 respect to a specific crystal plane of said substrate, said tilt axis being located in the plane of said surface; (b) an epitaxial layer formed on said surface of said substrate; said epitaxial layer having preferred etching direction aligned along said specific crystal plane of said substrate; and 3.
(a) (c) a bipolar transistor; said transistor having an emitter region, a base region, and an emitter contact; said emitter and base regions being formed in said epitaxiaI layer; said emitter contact being formed to contact said emitter region on an emitter contact area of said epitaxial layer; said emitter contact area having an elongated shape, the longitudinal axis thereof being aligned substantially parallel to said tilt axis.
2. A device as claimed in Claim 1, wherein said specific crystal plane of said substrate is selected to minimise the etch rate of said emitter contact area.
A semiconductor device comprising: a semiconductor substrate; a surface of said substrate being tilted about a tilt axis by a tilt angle with respect to a specific crystal plane of said substrate, said tilt axis being located in the plane of said surface; (b) an epitaxial layer formed on said surface of said substrate; said epitaxial layer having a preferred etching direction aligned along said specific crystal plane of said substrate; (c) a first bipolar transistor; said first transistor having a first emitter region, a first base region, and a first emitter contact; epitaxial layer; said first emitter region and said first base region being formed in said said first emitter contact being formed to contact said first emitter region on a first emitter contact area of said epitaxial layer; said first emitter contact area having an elongated shape, the longitudinal axis thereof being aligned in a first direction; said first direction forming an angle in the range from 351' to 551 with respect to said tilt axis; and (d) a second bipolar transistor; said second transistor having a second emitter region, a second base region, and a second emitter contact; said second emitter region and said second base region being formed in said epitaxial layer; said second emitter contact being formed to contact said second emitter region on a second emitter contact area of said epitaxial layer; said second emitter contact area having an elongated shape, the longitudinal axis of said second emitter contact area being aligned in a second direction; said second direction forming an angle in the range from 125' to 1451 or from - 35' to -55' with respect to said tilt axis.
4. A device as claimed in Claim 3, wherein said first direction forms an angle of approximately 451 with respect to said tilt axis, and said second direction forms an angle of approximately 1351 or -45 with respect to said tilt axis.
5. A device as claimed in any preceding claim, wherein said specific crystal plane is the (11 1)-plane of a single-crystal silicon.
6. A method of fabricating a semiconductor device, said method comprising the steps of:
preparing a semiconductor substrate, a surface of said substrate being tilted about a tilt axis by a tilt angle with respect to a specific crystal plane of said substrate, said tilt axis being located in the plane of said surface; forming an epitaxial layer on said surface of said substrate, said epitaxial layer having a preferred etching direction aligned along said specific crystal plane of said substrate; and forming a bipolar transistor on said epitaxial layer, said transistor having an emitter region, a base region, and an emitter contact, said emitter and base regions being formed in said epitaxial layer, said emitter contact contacting said emitter region on an emitter contact area of said epitaxial layer, and said emitter contact area having an elongated shape, the longitudinal axis thereof being aligned substantially parallel to said tilt axis.
7. A method as claimed in Claim 6, wherein said specific crystal plane of said substrate is selected to minimise the etch rate of said emitter contact area.
8. A method of fabricating a semiconductor device comprising the steps of: preparing a semiconductor substrate, a surface of said substrate being tilted about a tilt axis by a tilt angle with respect to a specific crystal plane of said substrate, said tilt axis being located in the plane of said surface; forming an epitaxial layer on said surface of said substrate, said epitaxial layer having a preferred etching direction aligned along said specific crystal plane of said 15 substrate; and forming a first bipolar transistor and a second bipolar transistor on the epitaxial layer, said first transistor having a first emitter region, a first base region, and a first emitter contact, said first emitter region and said first base region being formed in said epitaxial layer, said first emitter contact contacting said first emitter 20 region on a first emitter contact area of said epitaxial layer, said first emitter contact area having an elongated shape, said second transistor having a second emitter region, a second base region, and a second emitter contact, said second emitter region and said second base region being formed in said epitaxial layer, and said second emitter contact contacting said second emitter region on a second emitter contact area of said epitaxial layer, said second emitter contact area having an elongated shape, wherein the longitudinal axis of said first emitter contact area is aligned in a first direction which forms an angle in the range from 35' to 55' with respect to said tilt axis, and the longitudinal axis of said second emitter contact area is aligned in a second direction, where said second direction forms an angle in the range from 1250 to 1450 or from -351 to -55' with respect to said tilt axis.
9. A method as claimed in Claim 8, wherein said first direction forms an angle of approximately 451 with respect to said tilt axis, and said second direction forms an angle of approximately 1350 or -45' with respect to said tilt axis.
10. A method as claimed in any of Claims 6 to 9, wherein said specific crystal plane is the (11 1)-plane of a single-crystal silicon.
11. A semiconductor device substantially as herein described with reference to and as shown in Figure 11 of the accompanying drawings.
12. A method of fabricating a semiconductor device substantially as herein described with reference to Figure 12 of the accompg drawings.
GB9714859A 1996-07-15 1997-07-15 Semiconductor device and fabrication method thereof Expired - Fee Related GB2322965B (en)

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