GB2357901A - Semiconductor Devices and Fabrication Method - Google Patents

Semiconductor Devices and Fabrication Method Download PDF

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Publication number
GB2357901A
GB2357901A GB0106775A GB0106775A GB2357901A GB 2357901 A GB2357901 A GB 2357901A GB 0106775 A GB0106775 A GB 0106775A GB 0106775 A GB0106775 A GB 0106775A GB 2357901 A GB2357901 A GB 2357901A
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emitter
region
emitter contact
contact area
layer
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GB0106775D0 (en
GB2357901B (en
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Hideki Suzuki
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NEC Corp
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NEC Corp
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66234—Bipolar junction transistors [BJT]
    • H01L29/66272—Silicon vertical transistors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/04—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their crystalline structure, e.g. polycrystalline, cubic or particular orientation of crystalline planes
    • H01L29/045—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their crystalline structure, e.g. polycrystalline, cubic or particular orientation of crystalline planes by their particular orientation of crystalline planes
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/70—Bipolar devices
    • H01L29/72—Transistor-type devices, i.e. able to continuously respond to applied control signals
    • H01L29/73—Bipolar junction transistors
    • H01L29/732—Vertical transistors
    • H01L29/7322—Vertical transistors having emitter-base and base-collector junctions leaving at the same surface of the body, e.g. planar transistor

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  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Ceramic Engineering (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Manufacturing & Machinery (AREA)
  • Chemical & Material Sciences (AREA)
  • Crystallography & Structural Chemistry (AREA)
  • Bipolar Transistors (AREA)

Abstract

A semiconductor device has a substrate tilted about a tilt axis 31 by a tilt angle with respect to a specific crystal plane of the substrate. The tilt axis 31 is located in the plane of the surface. An epitaxial layer is formed on the surface of the substrate. The epitaxial layer has a preferred etching direction aligned along the specific crystal plane of the substrate. A first bipolar transistor has a first base region, a first emitter region, and a first emitter contact 3b. The first emitter region and the first base region are formed in the epitaxial layer. The first emitter contact is formed to contact the first emitter region on a first emitter contact area of the epitaxial layer. The first emitter contact area 3b has an elongated shape, the longitudinal axis being aligned in a first direction. The first direction forms an angle in the range from 35{ to 55{ with respect to the tilt axis 31. A second bipolar transistor has a second emitter region, a second base region, and a second emitter contact. The second emitter region and the second base region are formed in the epitaxial layer. The second emitter contact is formed to contact the second emitter region on the second emitter contact area 3c of the epitaxial layer. The second emitter contact area has an elongated shape and the longitudinal axis of the second emitter contact area is aligned in a second direction. The second direction forms an angle in the range from 125{ to 145{ or from -35{ to -55{ with respect to the tilt axis.

Description

2357901 SEMICONDUCTOR DEVICE AND FABRICATION METHOD THEREOF The present
invention relates to a semiconductor device and more particularly, to a semiconductor device with a bipolar transistor or bipolar transistors the emitter and base regions of which are formed in an epitaxial layer by the self-aligned process technology, and a fabridation method of the device.
Typically, as shown in Fig. 3, a lot of identical large-scale integrated circuit (LSI) chips 120 are fabricated on a single-crystal silicon substrate or wafer 1.01. The rectangular chips 120 are then separated by cutting the wafer 101 along scribing lines 119. The scribing lines 119 are drawn in parallel or perpendicular to a primary orientation flat 102 of the wafer 101.
For bipolar LSIs, generally, it is said that the wafer 101 has a chief surface 101A directed along the direction of (1111; in other words, the chief surface 101A of the wafer 101 has a crystal plane of (111). This is because the etch rate along the [1111-direction is the smallest among these along any other directions in silicon material.
Practically, however, as shown in Figs. 1 and 2,the chief surface 101A of the wafer 101 is tilted by a small angle E) with respect to the (111)-plane 130 around a tijt axis 131. Here, the axis 131 is defined as a straight line that is perpendicular to the orientation flat 102, parallel to the chief surface 101A, and penetrates the center oE tAe flat 102. Although the tilt angle 6 is designed as neces ary., it is typically C.
The reference character N indicates a normal of the chief surface 101A.
The tilting of the chief surface 101A with respect to the (111)-plane 130 is necessary due to the following reason.
Specifically, for bipolar LSIs, an epitaxial layTir is (not shown) is grown on the chief surface 101A of the wafr 101, and emitter and base regions of bipolar transistors ae formed in this epitaxial layer. A patterned buried layer serving as a sub-collector region is formed in the vicinity of the interface of the substrate 101 and the epitaxial layer To place or overlay necessary masks onto te su.bstrate 101 with high accuracy during subsequent processes, the patterns formed on the chief surface 101A of the substrate 101 need to be identically reflected on the sxirfa,ce of the epitaxial layer. However, the resultant patterns on the surface of the epitaxial layer tend to be shifted or distorted with respect to the patterns an the surface 101A of the substrate 101 due to the crystal orientation difference, -5 which is termed the ""pattern shift" or -pattern distortion-. The above tilting of the chief surface 101A solves this Problein.
Fig. 4 shows a partial cross-section of a conventional npn-type bipolar transistor formed in a conventional bipolar LSI. In Fig. 4, the chief surface 101A of the single- crystal silicon substrate or wafer 101 has a crystal plane tilted by 40 with respect to the (111)-plane 130 around the tilt axis 131, which is described above.
As shown in Fig. 4, an n-type buried layer 121 1-5 serving as a sub-collector region is s-electively formed in the surface region of the substrate 101. An n-type epitaxial layer 104 is formed on the chief surface 101A ofthe substrate 101 to cover the n-type buried layer 121.
In the epitaxial layer 104, an n-type emitter region 118, a p-type base region 115. and a p-type graft base region 113 are formed. The einitter region 118 is surrounded by the base region 115 and is entirely overlapped with the base region 115. The inner end of the graf t base region 113 is connected to the outer end of the base region 115.
A silicon dioxide (Si02) layer 105 is selectively formed on the exposed area of the epitaxial layer 104. p: type base contact 112 is formed on the p-type graft aso region 113, which is located in a window of the layer 105,.
The base contact 12 is made of polysilicon doped with toran (B) A p-type base contact 106 is formed on the Si02 layer loS to be contacted with the underlying base contact.112. The base contact 106 is made of polysilicon doped with boron.
An interlayer dielectric layer 107 is formed on thb exposed area of the 5i02 layer 105 to cover the base cortact 106.
A window 108 is formed on the base region 115 b the interlayer dielectric layer 107 and the base contact 10( the window 108, a sidewall spacer 109, which is mad 0: r silicon nitride (5i3Nt), is formed on the side faces oi the base contact 106 and the interlayer dielectric layer 10i.
Another sidewall spacer 116, which is made of Si3N4, is formed on the side and bottom faces of the sidewall s acer log. A 5i02 layer 114 is formed on the periphery of the bafe region 105 to be contacted with the graft base region 113 ahd the base contact 112.
An n-type emitter contact 117, which is ma(e bf polysilicon doped with arsenic (As), is formed on the em tter region 118 in the window 108. The emitter contact 117 is contacted with the emitter region 118, the Si02 layer 114, the sidewall spacers 109 and 116, and the interlayer dielectric layer 107.
The reference numeral 103a in Fig. 4 indicates the contact area of the emitter contact 117 with the emitter region 118 or epitaxial layer 104. The contact area 103a typically has a rectangular plan shape.
The npn-type bipolar transistor shown in Fig. 4 is laid out on the wafer 101 in such a way that the rectangular emitter contact area 103a, of the bipolar transistor in each chip 120 is directed in parallel or perpendicular to the orientation flat 102 (or, the tilt axis 131), as schematically shown in Fig. 2. The emitter contact area 103a has a length L and a width W. This layout is adopted for the purpose of increasing the packing density on the chip 120 as high as possible.
In the fabrication process sequence of the npn-type bipolar transistor in Fig. 4, the 5i02 layer 114 is formed on theepitaxial layer 104 and then.. it is selectively etched in the window 10e to uncover the surface of the epitaxial layer 104. During this etching process, the surface 104A of the epitaxial layer 104 tends to be etched along the (111)-plane,, i,e., along the direction perpendicular to the [1111- direction due to the orientation dependency of the etch rite.!.As a result, the surface 104A tends to have irregularity. ike; saw-teeth in cross section, as schernatically shown in Fig, and 6.
Fig.5 corresponds to the transistor the rectang. lat contact area 103a of which is directed along the crienta ion' f lat 102. Fi g. 6 corresponds to the transistor th(; rectangular contact area 103a of which is dire ted perpendicular to the orientation flat 102.
If the surface 104A of the epitaxial layer 10 is overetched, the surface 104A tends to be inclined ith respect to its original surface, as shown in Figs 7 an 8.
The resultant inclined surface is directed along the (111)4_ plane. The inaximum depth of the resultant inclined surface:
will be d, for the rectangular contact area 103a whicl ip' parallel to the orientation flat 102, as shown in Fig. 7. The resultant tnaximum depth will be d2 for the rectanttula'r contact area 103a which is perpendicular to the orientitiol!n flat 102/ where d, > d2, as shown in Fig. 8.
In other words the resultant maximum depth of the epitaxial layer 104 increases as the length of te rectangular contact area 103a along the orientation flal 192 becomes longer.
With the conventional bipolar transistor shown in Fig 4, as described above, the active base region 115 and the emitter region 118 are formed by doping impurities into the epitaxial layer 104 through the etched surface 104A of the layer 104. Therefore, if the rectangular contact area 103a is laid out on the wafer or substrate 101 in such a way that the longitudinal axis of the area 103a is directed along the orientation flat 102, the bipolar transistor tends to have a greater surface irregularity than the bipolar transistor where the longitudinal axis of the contact area 103a is directed perpendicular to the orientation flat 102.
This surface irregularity on the surface 104A leads to the thickness fluctuation or variation of the base region 115, thereby degrading the collector-to-emitter withstand voltage and/or increasing the dc: current gain factor hre.
Also, due to the different surface irregularities on the etched surfaces 104A as shown in Figs. 5 and 6, the transistors on the wafer 101 tend to have different characteristics dependent upon the layout direction.
Further if the maximum etched depth of the surface 104A of the epitaxial layer 104 becomes large, the level of the base region 115 will be lower with respect to the original surface of the layer 104. This means that the base region 115 is shifted toward the underlying buried layer 121 With respect to the original surface of the epitaxial ayeir 104, resulting in increase in collector-to-base capacital ce.:
Alternately, since the contact area of the graft bade region 113 and the base region 115 is decreased due tc the shift of the base region 115, the base resistance will be raised. Consequently, the operation speed of the transi t 0 will be reduced.
Accordingly, an object of at least the preferred embadimer ts Of io the present Invention Is to provide a semiconductor device and a fabrication m th6d thereof in which the degradation in collector-to-em- litttr withstand voltage of a bipolar transistor and the increase in dc current gain factor o.f the transistor is suppressed.
Another such object is to plovi'e' a semiconductor device and a. fabrication inethod thereof tht improve the reliability in operation.
Still another such object is:to provide a semiconductor device and a fabrication iethod thereof that raise the operation speed of a b., Polar transistor.
A further.such object is ito provide a semiconductor device and a fabrication etod 1 thereof that suppresses the fluctuation in bipolar tran isor characteristics independent of the layout orientation on a semiconductor substrate and enhances the circuit design margin.
In a first aspect, the' present invention provides.. a semiconductor device comprising a semiconductor substrate, a surface of said substrate being tilted about a tilt axis by a tilt angle with respect to a specific crystal plane of said substrate, said tilt axis being located in the plane of said surface, an epitaxial layer formed on said surface of said substrate, said epitaxial layer having a preferred etching direction aligned along said specific crystal plane of said substrate, a first bipolar transistor, said first transistor having a first emitter region, a first base region, and a first emitter contact, said first. emitter region and said first base region being formed in said epitaxial layer, said first emitter contact being formed to contact said first emitter region on a first emitter contact area of said epitaxial layer, said first emitter contact area having an elongated shape, the longitudinal axis thereof being aligned in a first direction, said first direction forming an angle in the range from 350 to 550 with respect to said tilt axis, and a second bipolar trans-istor, said second transistor having a second emitter region, a second base region, and a second emitter contact, said second ernitter region and said second base region being formed in said epitadal layer, said second emitter contact being formed to contact said second emitter region on a second emitter contact area of said epitaxial layer, said second emitter coIltact area having an elongated shape; the longitudinal axis of said second emitter cortact area being aligned in a second direction, said second direction forniing an an& in the range from 1250 to 145' or from -35' to -551 with respect to said tilt axis.
According to a preferred embodiment of the first.aspecit of the present invention, a semiconductor device is provided including a semiconductor subsirate with a chief surface, an epitaxial layer formed on the chief surface ofthe substiate, and first and second bipolar transistors formed at the epitaxial layer.
The chief surface of the substrate is tilted by a tilt angle with respect to a specific crystal plane of the substrate: around a tilt axis. The tilt axis is located the chief surface.
The epitaxial layer has a tendency to be etched along the specific crystal plane of the substrate.
The first transistor has a first emitter region, a first base region, and a first ernitter contact. The first -10 emitter region and the first base region are formed in the epitaxial layer. The first emitter contact is formed to be contacted with the first emitter region at a first emitter contact area of the epitaxial layer. The first emitter contact area has an elongated plan shape.
The second transistor has a second emitter region, a second base region, and a second emitter contact. The second emitter region and the second base region are formed in the epitaxial layer. The second emitter contact is formed to be contacted with the second emitter region at a second emitter contact area of the epitaxial layer. The second emitter contact area has an elongated plan shape.
The longitudinal axis of the first emitter contact area is directed in a first direction. The first direction f orm.5 an angle ranging from 35 to 55 with respect to the tilt axis.
The lon gitudinal axis of the second emitter contact area is directed in a second direction. The second direction forms an angle ranging from 1250 to 145' or from 351 to -550 with respect to the tilt axis.
With the semiconductor device according to the first aspect of the present invention/ the longitudinal axis of the elongated first emitter contact area of the first bipolar transistor is directed in the first direction. The first direction forms an angle ranging froin 351 to 550 with res11 ecti: to the tilt axis.
The longitudinal axis of the elongated second emi tet contact area of the second bipolar transistor is directef In the second direction. The second direction forms an a gig ranging from 12- 5 to 145' or from 35 to -55 with respec to the tilt axis- Therefore, the lengths of the first and second emitter contact areas along a direction perpendicular to/ the 10 tilt axis are approximately equal.
Consequently, the fluctuation in t rans j s to;:
characteristics is suppressed between the first and slecond,' bipolar transistors, which is independent of the 1 yot orientation of the first and second transistors on th e 15 substrate. This enhances the circuit design margin.
At the same time, because none of the first ad second emitter contact areas of the first and s con'd transistors is excessively etched, the reliabilit: Ln, operation is improved.
The reason that the angle of the. first dir ction ranges from 35 to 550 with respect to the tilt axis an' that the angle of the second direction ranges from 1250 to 1 50!or fron -35 to -550 with respect to the tilt axis is as fo loV'S.
If the angle of the first direction is not in the range from 3.5 to 55" and the angle of the second direction is not in the range from 125' to 145' nor from -351 to -550 w.ith respect to the tilt axis, the above advantages of the device are not sufficiently obtained.
in a preferred embodiment of the semiconductor device according to the first aspect, the specific crystal plane of the substrate is selected in such a way that the etch rate of the substrate is minimized- Typically, the specific cryst-al plane is the (111)-plane of a single-crystal silicon.
In this case, the advantages of the device according to the first aspect. are more effectively realized In another preferred embodiment of the semiconductor device according to the first aspect, the first direction forms an angle. of approximately 45 with respect to the tilt axis. The second direction forms an angle of approximately 1350 or -45 with respect to the tilt axis.
in this case, the advantages of the device according to. the first aspect are most effectively realized - In a second aspect the present invention provides a method of fabricatim a g semiconductor device comprising the steps of preparing a semiconductor substnte, a surface of said substrate being tilted about a tilt axis by a tilt angle with respeci to a specific crystal plane of said substrate, said tilt axis being located in the plane of said surface, forming an epitaxial layer on said surface of said substrate, said epitaiial layer having a preferred etching direction aligned along said specific crystal pland of said substrate, and forming a first bipolar transistor and a second bipolar transiAtor on the epitaxial layer, said first transistor having a first emitter region, a first tase region, and a first emitter contact, said first emitter region and said first base region being formed in said epitaxial layer, said first emitter contact contacting said first emitter region on a first emitter contact area of said epitaxial layer, said first emitter contact area having an elongated shape, said second transistor having a second emitter region, a second base region, and a second emitter contact, said second emitter regi ion and said second base region being formed in said epitaxial layer, and said second ernitter contact contacting said second emitter region on a second emitter contact area of said epitaxial layer, said second emitter contact area having an elongated shape, wherein the longitudinal axis of said first emitter contact area is aligned in a first direction which forms an angle in the range from 35' to 55 with respect to said tilt axis, and the longitudinal axis of said second emitter contact area is aligned in a::
second direction, where said second direction forms an angle in the range from 1251':
to 1450 or from -350 to -55 with respect to said tilt axis.
According to a preferred embodiment of the second aspect of the pres ant invention, another fabrication method of a semiconductor device is provided.
In this method, as a first step, a semiconductor substrate with a chief surface is prepared. The chief surface of the substrate is tilted by a tilt angle with respect to a specific crystal plane of the substrate around a tilt axis.
The tilt axis is located in the chief surface.
As a second step, an epitaxial layer is formed on the chief surface of the substrate. The epitaxial layer has a tendency to 'be etched along the specific crystal plane of the substrate.
As a third step, first and second bipolar transistors are formed at the epitaxial layer.
The first transistor has a first emitter region, a first base region, and a first emitter contact- The first emitter region and the first base region are formed in the epitaxial layer. The first emitter contact is formed to be contacted with the first emitter region at a first emitter contact area of the epitaxi- al layer. The first emitter contact area has, an elongated plan shape.
The second transistor has a second emitter region, a 20 second base region, and a second eraitter contact. The second emitter region and the second base region are formed in the epitaxial layer. The second emitter contact is formed to be contacted with the second emitter region at a second emitter contact area of the epitaxial layer. The second emitter contact area has an elongated plan shape.
The longitudinal axis of the first emitter contact area is directed in a first direction- The first direction forms an angle ranging from 35' to 55' with respect to the tilt axis- The longitudinal axis of the second emitter contact area is directed in a second direction- The second direction forms an angle ranging from 1250 to 1450 or from -35' tc -550 with respect to the tilt axis.
Preferred features of the present invention will now be described, purell, by way of example only, with reference to the accompanying drawings, in which:-::
Fig. 1 is a schematic side view of a semiconductor 15 substrate or wafer on which conventional bipolar transistos are formed, which shows the relationshipamong the chielf surface, the crystal plane, and the tilt axis.. of tl 1 e substrate.
Fig. 2 is a schematic plan view of the se,micontuctpr substrate or wafer in Fig. 1, which shows the relaticnshi p among the emitter contact areas of the bipolar transisto S formed on the substrate or wafer, and the tilt axis and the orientation flat of the substrate.
16 E19. 3 is a schematic plan view of the semiconductor substrate or wafer in Fig. 1, which shows the layout of the LSI chips on the wafer.
Fig. 4 is a schematic, partial cross-sectional view of one of the conventional bipolar transistors along the line Iv-1V in Fig. 2.
Fig. 5 is a schematic, enlarged, partial cross sectional view of the conventional bipolar transistor in Fig.
4, which shows the state of the etched surface of the epitaxial layer.
Fig. 6 is a schematic, enlarged, partial crosssectional view of the conventional bipolar transistor in Fi'g. 4,. which shows the state of the etched surface of 'theepitaxial layer.
Fig. 7 is a schematic, enlarged, partial crosssectional view of the conventional bipolar transistor in Fig. 4. which shows the state of the overetched surface of the epitaxial layer.
Fig. 8 is a schematic, enlarged,. partial cross20 sectional view of the conventional bipolar transistor in Fig.
4, which shows the state of the overetched surface of the epitaxial layer.
Fig. 9 is a schematic side view of a semiconductor substrate or wafer on which bipolar transistors 17 are formed, which shows the relationship among the chief surface, t" e crystal plane, and the tilt axis of the substrate.
Fig. 10 is a schematic plan view of the semiconductor substrate or wafer in Fig. 9, which shows the relationship among the emitter contE ct areas of the bipolar transistors formed on the substrate or wafer, and t e tilt wds and the orientation flat of the substrate.
Fig. 11 is a schematic, partial cross-sectional view of one of the bipolar transistors along the line M-M in Fig. 10 Fig. 12A to 12K are schematic, partial cross-sectional views of the bipolar transistor which show its fabrication method, respectively.
Fig. 13 is a schematic plan view of a semiconductor substrate or wafer, which shows the relationship among the emitter contact area of the bipolar transistors according to an embodiment of the pres( nt invention, and the tilt aids and the orientation flat of the substrate.
18 Figs. 9 and 10 schematically show a p-type single-crystal silicon substrate or wafer 1, on which a plurality of semiconductor devices are forined. The wafer 1 has a primary orientation flat 2.
A chief surface 1A of the wafer 1 is tilted by a small angle E) with respect to the (111) - plane 30 around a tilt axis 3 1. Here, the wds 31 is defined as a straight line that is perpendicular to the orientation flat 2, parallel to the chief surface 1A, and penetrates the center of the flat 2.
The tilt angle E) is set as 4'. The reference character N indicates a normal of the chief surface 1A.
Each of the semiconductor devices has an npn-type bipolar transistor as shown in Fig. 11. The transistor is substantially the same in configuration as the transistor in Fig.4.
In Fig. 11, the chief surface 1A of the single-crystal silicon, substrate or wafer 1 has a crystal plane tilted by 4' with respect to the (111)plane 30 around the tilt axis 3 1, which described above.
19 if An n'-type buried layer 21 serving as a Sub-colle( tot, region is selectively formed in the surface region o:E the substrate 1. An n-type epitaxial layer 4 is formed on the chief surface IA of the substrate 1 to cover the n+type buried layer 21 in the epitaxial layer 4, an n-type emitter regio 18, a p-type base region 15, and a p-type graft base regio 13 are formed. The emitter region 18 is surrounded by the bas region 15 and is entirely overlapped with the base regio 151.
The:inner end of the graft'base region 13 is connected t th,' outer end of the base region 15.
A Si02 layer 5 is selectively forined on the ex Osect area of the epitaxial layer 4. A p-type base contact 12 r b formed on the p-type graft base region 13, which is lo atd 15 In a window of the layer 5. The base contact 12 is ma e of polysilicon doped with boron.
A p-type base contact 6 is formed on the Si02 laYer!S.
to be contacted with the underlying base contact 12. Tht bae contact 6 is made of polysilicon doped with boron.
An interlayer dielectric layer 7 is formed o t'he exposed area of the 5i02 layer 5 to cover the base cont ct 16.
A window 8 is formed on the base region 15 ly C interlayer dielectric layer 7 and the base contact 6. n 'he r window 8, a sidewall spacer 9, which is made Of Si31 4f is forined on the side faces of the base contact 6 and the interlayer dielectric layer 7. Another sidewall spacer 16, which is made of 5i3N,, is formed on the side and bottorn fares of the sidewall spacer 9. A 5i02 layer 14 is formed on the periphery of the base region 5 to be contacted with the graft base region 13 and the base contact 12.
An n-type emitter contact 17, which is made of polysilicon doped with arsenic, is formed on the emitter region 18 in the window 8. The emitter contact 17 is lo contacted with the emitter region 18, the SiO2 layer 14, the sidewall spacers 9 and 16, and the interlayer dielectric layer 7.
The reference numeral 3a. in Fig. 11 indicates the contact area of the emitter contact 17 with the emitter region 18 or epitaxial layer 4. Here, the contact area 3a has a rectangular plan shape.
The npn-type bipolar transistors shown in Fig. 11 are laid out on the wafer 1 in such a way that the longitudinal axis of the rectangular ezaitter 'contact areas 3a of the 20 transistor in each chip is directed perpendicular to the orientation flat 102 (or, in parallel to the tilt axis 31), as schematically shown in Fig. 10. The emitter contact area 3a has a length L and a width W.
21 The bipolar transistor shown in Fig- 11 is fabricated by the following process steps.
First, as shown in Fig. 12A, the n'-type buried layer; 21 serving as a sub-collector region is selectively forME;d ih 5 the surface region of the substrate 1. The n-type epitaxiall layer 4 is formed on the chief surface 1A of the substrzte 1 to cover the buried layer 21.
Next, the SiO2 layer 5 is formed on the epitaxia:l layer 4 by thermal oxidation or Chemical Vapor Depos'. tioIn over the whole substrate 1. A polysilicon layer (n t shown) is. deposited on the Si02 layer 5 by CVD and.--hen, boron is doped into the polysilicon layer thus deposite thereby forming 1 the p-type polysilicon layer 6 on the Sipl:
layer 5. The p-type polysilicon layer 6 is then pattern d y photolithography and etching, as shown in Fig. 12A.
The interlayer dielectric layer 7 is. formed on the exposed SiO,, layer 5 to cover the p-type polysilicon basle I contact 6 for the purpose of surface planarization, The interlayer dielectric layer 7 may be formed by a SiO2 laye;,, SiIN4 layer/ or the combination of the stacked Si02 and Si4IN4 sublayers. The state at this stage is shown in Fig. 12A Subsequently, the interlayer dielectric layer 7 and the p-type polysilicon layer 6 are selectively removed by dr y etching, thereby forming a rectangular window 8. The W111COV1 a 22 uncove-rs the central part of the Si02 layer 5. The state at this stage is shown in Fig. 12B.
A Si3N4 layer (not shown) is deposited by CVD on the interlayer dielectric layer 7 to cover the window 8. The 5i3N4 layer thus deposited is then etched back to thereby form the sidewall 9, as shown in Fig.. 12C. The Si3N4 sidewall 9 is located on the 5i02 layer 5 and contacted with the side faces of the p-type polysilicon layer 6 and the interlayer dielectric layer 7.
Then, the Si02 layer 5 and the Si3N4 sidewall 9 are selectively removed by wet etching using buffered hydrogen:Eluc)i:ide (HF) until the inner end 10 of the remaining Sio,. layer 5 approximately accords with the outer end position of the p-type graft base region 13. Thus, the surface 4a, of the epitaxial layer 4 is exposed in the window 8. The state at this stage Is shown in Fig. 12D.
Following this, the non-doped polysilicon layer 11 is deposited by M onthe interlayer dielectric layer 7 to cover the window 8. As shown in Fig. 12E, the layer 11 is contacted with the exposed surface 4A of the epitaxial layer 4, the inner end 10 of the remaining SiOz layer 5, the bottom face of the p-type polysilicon layer 6, and the exposed areas of the.. 5idewall 9.
The assembly shown in Fig. 12E is then subjected to a heat treatment at a temperature of 800 OC to loOO oC, thereb:y di:Efusing the boron atoms contained in the P-type polysilicon layer 6 into the non-doped polysilicon layer 11 and the epitaxial layer 4. Thus, the p-type PO1Y5ilicon base ccntac_t 12 and the p-type graft base region 13 are formed. The state at this stage is shown in Fig. 12F.
Using. the etch rate difference between non-dopi.-d polysilicon and boron-doped polysilicon, the remaining non doped polysilican layer 11 is selectively removed by alkali etching using hydrazine while leaving the boron- ope'd polysilicon layer 12, as shown in Fig. 12G.
The Assembly shown in Fig- 12G is then subj ected to thermal oxidation, thereby forming the 5i02 layer - 14 on te uncovered surface 4A of the epitaxial layer 4 and te uncovered. inner end 10 of the p-type.polysilicon layer 12, 'as shown in Fig. 12H.
Boron is selectivtly ion-implanted into the epitaxi1 layer 4 through the S102 layer 14 in the window 8, T e implanted boron atoms into the layer 4 are then diffus d Vertically and laterally within the layer 4 by heat treatmebt at a temperature of 800 C to 100 OC, thereby forming the type base region 15 in the layer 4. The state at this stage is sho" in Fig. 12H.
24- A Si3N4 layer (not shown) is deposited on the interlayer dielectric layer 7 by CVD to cover the window 8 and is then etched back, resulting in the Si3N4 sidewall 16 on the siO2 layer 24, as shown in Fig. 121.
The Sio,. layer 14 is then removed selectively by etching to have an opening uncovering the underlying surface 4A of the epitaxial layer 4. The opening has a width equal to the distance between the opposing bottom ends of the.sidewall 16. The state at this stage is shown in Fig.. 121.
The polysilicon layer 17 is deposited on the interlayer dielectric layer 7 by CVD to cover the window 8.
The layer 17 is then doped with arsenic and patterned, thereby forming the n-type polysilicon emitter contact 17 on the uncovered surface 4A of the epitaxial layer 4_ The state at this stage is shown in Fig. I2J.
The assembly in Fig. 12J is then subjected to heat treatment at a temperature of 800 C to 1000 'C to thereby diffuse the arsenic atoms contained in the n-type. polysil icon emitter contact 17 into the underlying p-type base region 15.
Thus, the n-type emitter region 18 is formed in the p-type base region 15. The state at this stage is shown in Fig. 12K.
With the serniconductor device as shown in Fig. 11, the epitaidal layer 4 has a tendency to be etched along the specific crystal plane (i.e., the (111)plane) which is tilted by 4' with respect tC the chief surface 1A of the substrate 1. Therefore, the e.--chd surface in the einitter contact area 3a of the epitaxial layr 4 tends to be directed along the (111)-plane of the subs.:.rae 5 1.
on the other hand, since the longitudinal axis of the elongated emitter contact area 3a of the bipolar transistdr is directed along the tilt axis 31, the lateral axis ot ttie emitter contact area 3a is directed perpendicular to the tii,,t axis -31. This means that the resultant etched depth in the emitter contact area 3a is minimized (see Figs. 4 and 6) As a result, the degradation in collector-to-emittl withstand voltage of the bipolar transistor and the increal se in dc: current gain factor thereof are. suppressed- This improves the reliability in operation of the semicondicto'r device.
Also, since the resultant etched depth in the emitttr contact area 3a is minimized, the level of the base region 5 is not lowered toward the buried layer 21 with respect to i Its designed position. Therefore, the increase in both collectoto-base capacitance and base resistance is suppressed, which raises the operation speed of the transistor.
For exampleo the collector-to-emitter wi tts t ahd voltage is raised from 4 to 5 V in the conventional one i in Figs. 2 to 7 to 8V. The operation speed of the bipolar transistor is increased by approximately 5 to 30 % with respect to the conventional one in Fig. 2.
Fig. 13 shows the layout of semiconductor devices with bipolar transistors according to an embodiment of the present invention.
In this enibodiment, the tilt wds 31 of the single-crystal silicon wafer or substrate 1 is set as shown in Fig. 13. Specifically, the tilt a)ds 31 forms an angle of 450 with respect to a straight line 32 perpendicular to the orientation flat 2 of the wafer 1. The line 32 penetrates the center of the flat 2 and the center of the wafer 1 itself in the chief surface of the wafer 1.
Similar to the above layout, the chief surface 1A of the wafer 1 is tilted by the same angle of 4' around the tilt aids 31 with respect to the (111)-plane.
As schernatically shown in Fig. 13, a first npn-type bipolar transistor is laid out on the wafer or substrate 1 in such a way that the longitudinal a)ds of a retangular emitter contact area 3b of the first transistor is directed perpendicular to the orientation flat 2. The longitudinal axis of the emitter contact area 3b has an angle of 450 with respect to the tilt axis 31.
A second npn-type bipolar transistor is laid out the wafer Or substrate 1A in such a way that the longitudinail axis of a rectangular emitter contact area 3c of the 5co d trarlsistor is directed in parallel to the orientation flat 2. The longitudinal axis of the emitter contact area 3c hs A n angle of 135' with respect to the tilt axis 31.
The first and second transistors has the same 10 configuration as shown in Fig. 11.
With the sen-iiconductor device according to this embodiment, the longitudinal axis of the elongated emitter contact area 3a of the first bipolar transistor is directe:d in the direction tilted by 45 with respect to the tilt axis 31, and the longitudinal axis of the elongated second enitter contact area. 3b of the second bipolar transistor is direct6d in the direction tilted by 1350 with respect to the tilt axis 31.
Therefore, the lengths Sb and Sc of the first Ind second emitter contact areas 3a and 3b, along the direction perpendicular to the tilt axis 31 are equal to each othar.
Consequently the fluctuation in transistor characteristics is suppressed between the first and econd bipolar transistors, which is independent of the layout orientation of the first and second transistors On the substrate 1. This enhances the circuit design margin.
At the same time, because none of the first and 5 second emitter contact areas 3b and 3c of the first and second transistors is excessively etched, the reliability in operation is improved.
The angle of the longitudinal axis of'the emitter contact area 3a may be any value ranging from 35 to 55 with respect to the tilt axis 31. The angle of the longitudinal axis of the emitter contact area 3b may be any value ranging from 125' to 145 or from -35' to -55 with respect to the tilt axis 31.
The angle between the tilt axis 31 and the straight line 32 may be any value in the range of 45 10 or 135 +_ loo.
While the preferred forms of the preserit' invention has been described, it is to be understood that modifications will be apparent to those skilled in the art withou.t depart- ing f rom the scope of the invention as determined solely by the following claims.
-29 The text of the abstract filed herewith is repeate d here as part of the specification.
A semiconductor device is provided, in which tle reliability in operation is improved. This device includ, s a semiconductor substrate with a chief surface, n epitaxial layer formed on the chief surface of t e substrate, and a bipolar transistor formed at the epitaxi 1 layer. The chief surface of the substrate is tilted by a tilt angle with respect to a specific crystal plane of the substrate around a tilt axis. The tilt axis is located in the chief surface. The epitaxial layer has a tendency to be etched along the specific crystal plane of the substrate. The transistor has an emitter region, a b se region, and an emitter contact. The emitter and bi se regions are formed in the epitaxial layer. The emit er,l contact is formed to be contacted with the emitter region: at an emitter contact area of the epitaxial layer. hL:1; emitter contact area has an elongated plan shape. hel longitudinal axis of the emitter contact area is directed! 20 along the tilt axis. The specific crystal plane of th& substrate is typically the (111) -plane of a single-cry.. tall silicon.

Claims (6)

  1. A semiconductor device comprising:
    (a) a semiconductor substrate; a surface of said substrate being tilted about a tilt axis by a tilt angle with respect to a specific crystal 5 plane of said substrate, said tilt axis being located in the plane of said surface; (b) an epitaxial layer formed on said surface of said substrate; said epitaxial layer having a preferred etching direction aligned along said specific crystal plane of said substrate; (c) a first bipolar transistor; said first transistor having a first emitter region, a first base region, and a first emitter contact; said first emitter region and said first base region being.formed in said.epitaxial layer; said first emitter contact being formed to contact said first emitter region on a first emitter contact area of said epitaxial layer; said first emitter contact area having an elongated shape, the longitudinal axis thereof being aligned in a first direction; said first direction forming an angle in the range from 35 to 551 with respect to said tilt axis; and (d) a second bipolar transistor; said second transistor having a second emitter region, a second base region, and a second emitter contact; said second emitter region and said second base region bei 9 forrned in said epitaxial layer; said second emitter contact being formed to contact said seccnd emitter region on a second emitter contact area of said epitaxial layE,.r; said second emitter contact area having an elongated shape, I he longitudinal axis of said second emitter contact area being aligned in a second direction; said second direction forming an angle in the range from 125' to 145' or from 35' to -55' with respect to said tilt wds.
  2. 2. A device as claimed in Claim 1, wherein said first direction for -ns an angle of 450 with respect to said tilt wds, and said second direct. on forms an angle of 135' or -45' with respect to said tilt a--ds.
  3. 3. A device as claimed in Claim 1 or 2, wherein said specific cryE tal plane is the (111) -plane of a single-crystal silicon.
  4. 4. A method of fabricating a semiconductor device comprisingthe steps of:
    preparing a semiconductor substrate, a surface of said substr te being tilted about a tilt a)ds by a tilt angle with respect to a specific crystal plane of said substrate, said tilt wds being located in the plane of said surface; forming an epitaxial layer on said surface of said substrate, said epita.>dal layer having a preferred etching direction aligned along said specific crystal plane of said substrate; and forming a first bipolar transistor and a second bipolar transistor on the epita,>dal layer, said first transistor having a first emitter region, a first base region, and a first emitter contact, said first emitter region and said first base region being formed in said epita)dal layer, said first emitter contact contacting said first emitter region on a first emitter contact area of said epita3dal layer, said first emitter contact area having an elongated shape, said second transistor having a second emitter region, a second base region, and a second emitter contact, said second emitter region and said second base region being formed in said epita3dal layer, and said second emitter contact contacting said second emitter region on a second emitter contact area of said epita3dal layer, said second emitter contact area having an elongated shape, wherein the longitudinal aids of said first emitter contact area is aligned in a first direction which forms an angle in the range from Wto 55'with. respect to said tilt a3ds, and the longitudinal a3ds of said second emitter contact area is aligned in a second direction, where said second direction forms an angle in the range from 125 to 145 or from -35' to -55 with respect to said tilt ayis.
  5. 5. A method as claimed in Claim 4, wherein said first direction forms an angle of 45' with respect to said tilt axis, and said second direct forms an angle of 135' or -45' with respect to said tilt axis.
  6. 6. A method as claimed in Claim 4 or 5, wherein said specific crys al plane is the (111) -plane of a single-crystal silicon.
GB0106775A 1996-07-15 1997-07-15 Semiconductor device and fabrication method thereof Expired - Fee Related GB2357901B (en)

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JP18482996A JP3156592B2 (en) 1996-07-15 1996-07-15 Semiconductor device and manufacturing method thereof
GB9714859A GB2322965B (en) 1996-07-15 1997-07-15 Semiconductor device and fabrication method thereof

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