GB2320806A

GB2320806A - Dynamic random access memory cell array

Info

Publication number: GB2320806A
Application number: GB9726854A
Authority: GB
Inventors: Woo Bong Lee
Original assignee: Hyundai Electronics Industries Co Ltd
Current assignee: SK Hynix Inc
Priority date: 1996-12-24
Filing date: 1997-12-22
Publication date: 1998-07-01
Anticipated expiration: 2017-12-22
Also published as: KR100227640B1; GB9726854D0; JPH10189892A; GB2320806B; DE19757878A1; JP3247862B2; KR19980052492A; GB2320806A8

Abstract

A DRAM array comprises a plurality of active regions 1 of X-shape, each region comprising four transistors 20A,20B,20C,20D with a common drain 22 at the centre of the X connected to a bit line. The source 21A,21B,21C,21D of each transistor is connected to an electrode of a respective capacitor, the other electrode of which covers the whole array apart from areas where word line contacts are connected to branches 3C of isolated patterns 3 which provide gate electrodes 3A,3B for two adjacent transistors. Such a layout allows reduction of power consumption with higher integration.

Description

2320806 DYNAMIC RANDOM ACCESS MEMORY CELL ARRAY

BACKGROUND OF THE INVENTION Field of the invention

The present invention relates to a dynamic random access memory (DRAM) cell array in which four (4) transistors that can operate individually are formed in an active region so that a power consumption can be reduced.

Description of the prior art

Recently, as the semiconductor device becomes highly integrated, a method for reducing power consumption and increasing an integration of device has been developed. A way for increasing the integration is to reduce a width of a pattern, however, it is difficult to form a pattern having a width of 0.25 and less due to a limitation of resolution of the exposure equipment. Also, the integration is decided by arrangement of cells.

In a conventional DRAM cell array, active regions are formed with "T" shape or 1711 shape, two transistors operated individually are formed in the each active region. Each of the two transistors is consisted of a gate electrode, a source electrode and a drain electrode, the drain electrode is used for the two transistors in common. A voltage of a half of Vcc (Vcc/2) is applied to each of two transistors using the drain electrode in common as described above. The two transistors operated by the half of Wc, respectively, has an advantage in that the power consumption is less than the transistor operated by a voltage of Wc.

As the power consumption is greater, a life time of device is shorter. Also, since two transistors are formed in an active region, a surface of cell increases when the integration becomes high.

1 In the conventional transistor, a word line including a gate is formed as a line. As integration of device becomes higher, a width of gate (length of channel) is decreased so that a resistance of the word line is increased. To solve this problem, a polycide structure Wh 11 consisted of polysilicon and tungsten silicide in stack is used. en the polycide is used, the.resistance is improved, however, a characteristic of threshold voltage in thetransistor becomes lower.

SUMMARY OF THE INVENTION

Therefore, it is an object of the present invention to a dynamic random access memory cell array in which four transistors are formed in an active region so that a power consumption can be minimized.

A dynamic random access memory cell array according to the present invention is characterized in that a field region and a plurality of active regions having a X shape are formed, four transistors are formed at upper end of left side, upper end of right side, lower end of left side and lower end of right side of the each active region, respectively, each four transistors hold a drain electrode connected to a bit line, in common, a source of the each transistor is connected to a lower electrode of a capacitor, a upper electrode of the capacitor is formed on the entire cell array, a gate electrode of the each transistor is formed of an isolated pattern which acts as the gate electrode of a adjacent transistor formed on neighboning active region, the isolated pattern is connected to a word line.

Brief description of the drawings

For fuller understanding of the nature and objects of the present invention, reference should be had to the following detailed description taken in conjunction with the accompanying drawings in which:

2 FIG. 1 is a lay-out showing active regions according to the present invention; FIG. 2 is a lay-out showing transistors according to the present invention; FIG. 3 is a lay-out showing bit lines according to the present invention; FIG. 4 is a lay out showing lower electrodes of capacitor according of the present.invention; invention; FIG. 5 is a lay-out showing upper electrode of capacitor according to the present FIG. 6 is a lay out showing word lines according to the present invention; FIG. 7 is a lay out showing another type word lines according to the present invention.

Detailed description of the invention

FIG. 1 is a lay-out showing a plurality of active regions 1 and a field region 2 defined at region other than the active regions 1. Each active region 1 is formed with 'W' shape. As shown in FIG. 1, enough spaces for forming word line contacts exist between the active regions 1, respectively.

FIG. 2 is lay-out showing the transistors formed on the active regions. Each of a plurality of the isolated patterns 3 is formed between the pair of the active regions 1. That is, the two (2) isolated patterns 3 are located on the field region 1 between the two active regions 1, and both ends of the each isolated pattern 3 are overlapped to the adjacent active regions 1.

Four (4) transistors 20A, 20B, 20C and 20D are formed on each active region 1 as shown in FIG. 2. For the sake of convenience, a transistor formed at upper end of left side of each active region 1 is defined as the first transistor 20A, a transistor formed at upper end of right side of each active region 1 is defined as the second transistor 20B, a transistor formed at lower end of left side of each active region 1 is defined as the third transistor 20C 3 and a transistor formed at lower end of right side of each active region 1 is defined as the fourth transistor 20D, respectively, and the only four transistors 20A, 20B, 20C and 20D formed on the one active region 1 are explained as an example.

The first transistor 20A is consisted of a gate electrode 3A, a source electrode 21A.and a drain electrode 22, the second transistor 20B is consisted of a gate electrode 3B, a source electrode 21B and the drain electrode 22. And, the third transistor 20C is consisted of the gate electrode 3A, a source electrode 21C and the drain electrode 22, the fourth transistor 20D is consisted of the gate electrode 3B, a source electrode 21D and the drain electrode 22. Here, the drain electrode 22 is used to the four transistors 20A, 20B, 20C and 20D in common, and the each gate electrode 3A or 3B is used as the gate electrode of an adjacent transistor.

In the each pattern 3, a branch 3C is extended from the center of the pattern 3 so that the branch 3C and the each pattern 3 are at right angles to each other. as shown in FIG. 2. Also, the branches 3C of the patterns 3 of certain row and the branches 3C of the patterns of adjacent rows are extended to opposite direction to each other.

On the other hand, in a conventional transistor, a gate electrode which acts as a word line is formed as a line. As an integration of device becomes higher, width of the gate electrode (length of channel) is decreased so that resistance of the word line is increased. To improve this disadvantage, a polycide structure consisted of a polysilicon and tungsten silicide in stack is used. Mlen the polycide structure is used, although the resistance can be reduced, a characteristic of a threshold voltage of transistor is degraded. In the present invention, however, a gate electrode is formed of the isolated pattern and one (1) isolated pattern is used as the gate electrode of the two (2) transistors. Therefore, even though the integration of device become higher, the gate electrode according to the present invention has not influence on the resistance.

4 FIG. 3 is a lay-out showing bit lines according to the present invention, bit line contacts 5 are formed on centers of the active regions 1 having a X shape, respectively. Each bit line contact 5 supplies a power supply voltage to the drain electrode 22 of the four transistors 20A, 20B, 20C and 20D formed at the one (1) active region 1. A quarter of the.power supply voltage Vcc is applied to the each transistor through the drain electrode 22 so that the power consumption can be reduced.

A plurality of bit lines 4-1 to 4-7 are connected to a sense amplifier/decoder 6. Each bit line connects the bit line contacts 5 of the active regions 1 of each row. The each bit line has a polycide structure so as to reduce a resistance and improve a operation charactenistic of device.

FIG. 4 is a lay out showing lower electrodes of capacitors according of the present invention, lower electrodes 7 of a capacitors are connected to the source electrodes 21A, 21B, 21C and 21D of the transistors 20A, 20B, 20C and 20D formed at the one active region 1 through capacitor contacts 8, respectively. Edge portions of the each lower electrode 7 is formed with an oblique line to ensure regions on which a word line contact will be formed.

FIG. 5 is a lay-out showing upper electrode of capacitors according to the present invention. In a process of manufacturing a semiconductor device, a conventional upper electrode of the capacitor covers the entire cell. In the present invention, however, a plurality of openings 10 are formed on the upper electrode 9 of the capacitor so as to expose regions on which word line contacts will be formed.

FIG. 6 is a lay out showing word lines according to the present invention, word line contacts 11 are formed on the branches (3C in FIG. 1) of the patterns 3, respectively. Word lines 12-1 to 12-12 to which a decoder 13 is connected are connected to the gate electrodes of the transistors through the word line contacts 11, respectively. Branches extended from the both outer word lines 12-1 and 12-12 are connected to the each gate electrode, and other word lines 12-2 to 12-11 are connected to the each gate electrode in zigzag shape.

Meanwhile, The word lines 12-1 to 12-12 are formed of one of titanium (Ti), titanium nitride (TIN), aluminum (AI), tungsten (W) or copper (Cu).

FIG. 7 is a lay out showing another type word lines according to the present invention. Word lines 14-1 to 14-12 to which a decoder 13 is connected are connected to the gate electrodes of the transistors through the bit line contacts 11, respectively. Branches extended from the both outer word lines 14-1 and 14-12 are connected to the gate electrode, respectively. Also, branches extended from the other word lines 14-2 to 14-11 are connected to the gate electrodes, respectively.

In the present invention as described above, the four (4) transistors are formed on the one (1) active region, the four transistors hold one (1) drain electrode in common. Therefore, the power supply voltage is supplied to the four transistors through the drain electrode and one (1) bit line, a gate bias voltage is supplied to the four transistors through the each word line so that the four transistors are operated individually.

The operation of the four transistors formed in the one active region indicated by a heavy line in FIG. 6 is as follow. The power supply voltage is supplied to the four transistors through the common drain electrode connected to the sixth bit line 4-6. The transistor formed at upper end of left side of the active region is operated in response a signal input through the seventh word line 12-7 and the transistor formed at upper end of right side of the active region is operated in response a signal input through the eighth word line 12-8. Also, the transistor formed at lower end of left side of the active region is operated in response a signal input through the fifth word line 12-5, and a transistor formed at lower end of right side of the active region is operated in response a signal input through the sixth word line 126. Consequently, the four transistors formed on the one active region are operated individually.

6 In the present invention as described above, the four transistors are formed on the one (1) active region formed with 'W' shape and the four transistors are operated individually so that an area of DRAM cell can be decreased and it is possible to manufacture a high integration device. Also, as the four transistors hold the one drain electrode in common, only.a quarter of power supply voltage is required to operate each transistor, therefore, the power consumption can be minimized. In the present invention, as the gate electrodes are connected frorn each other by the metal lines, a resistance of word line is decrease without forming a polycide structure of the gate electrode so that an operation speed of device can be enhanced and it is possible to prevent a lowering a characteristic of threshold voltage of the transistor.

Many modifications and variations may be made in the techniques and structures described and illustrated herein without departing from the spirit and scope of the present invention. Accordingly, it should be understood that the techniques and structures described and illustrated herein are illustrative only and are not to be considered as limitations upon the scope and spirit of the present invention.

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Claims

What is claimed is:

1. A dynamic random access memory cell array characterized in that a field region and a plurality of active regions having a X shape are formed, four transistors are formed at upper end of left side, upper end of right side, lower end of left side and lower end of right.side of said each active region, respectively, each four transistors hold a drain electrode connected to a bit line, in common, each source of the each transistor is connected to lower electrode of a capacitor, a upper electrode of the capacitor is formed on the entire cell array, each gate electrode of the each transistor is formed of an isolated pattern, said isolated pattern acts as a gate electrode of a adjacent transistor formed on neighboning active region, said isolated pattern is connected to a word line.

2. The DRAM cell array of claim 1, wherein said each isolated pattern acting as the gate electrode of two transistors has a branch extending to a portion on which a word line contact be formed.

3.. The DRAM cell array of claim 2, wherein said branch and said each pattern are at right angles to each other.

4. The DRAM cell array of claim 1, wherein said bit line is connected to said drain electrode through a bit line contact formed on central portion of said active region having a X shape and connected to a sense amplifier/decoder.

5. The DRAM cell array of claim 1, wherein each lower electrode has edge portions formed with an oblique line to ensure a region on which a word line contact will be formed.

6. The DRAM cell array of claim 1, wherein said upper electrode of said capacitor has 8 a plurality of openings to expose portions on which word line contacts will be formed.

7 The DRAM cell array of claim 1, wherein said word line is connected to said drain electrode through a word line contact formed on a branch of said isolated pattern and connected to a decoder.

8. The DRAM cell array of claim 1, wherein said gate electrodes of said four transistors formed on said one active region are connected to word lines, respectively, whereby said four transistors are operated individually.

9. The DRAM cell array of claim 1, wherein said word lines formed at both ends of cell are connected to said gate electrodes through branches extending from a side thereof, and said word lines formed at inner side of cell are connected to said gate electrodes in zigzag manner.

10. The DRAM cell array of claim 1, wherein said word lines formed at both ends of cell are connected to said gate electrodes through branches extending therefrom, and said word lines formed at inner side of cell are connected to said gate electrodes through branches extending alternatively from both sides thereof.

11. The DRAM cell array of claim 1, wherein said each word line is formed of at least one of titanium, titanium nitride, alurninum, tungsten and copper.

12. The DRAM cell array of claim 1, wherein said each bit line is formed in horizontal direction and said each word line is formed in vertical direction.

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