GB2320128A - Process for fabricationg low leakage current electrode for LPCVD titanium oxidefilms - Google Patents
Process for fabricationg low leakage current electrode for LPCVD titanium oxidefilms Download PDFInfo
- Publication number
- GB2320128A GB2320128A GB9625144A GB9625144A GB2320128A GB 2320128 A GB2320128 A GB 2320128A GB 9625144 A GB9625144 A GB 9625144A GB 9625144 A GB9625144 A GB 9625144A GB 2320128 A GB2320128 A GB 2320128A
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- deposited
- tio
- film
- top electrode
- electrode layer
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- Granted
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- 238000000034 method Methods 0.000 title claims abstract description 61
- 230000008569 process Effects 0.000 title claims abstract description 42
- 239000010936 titanium Substances 0.000 title claims abstract description 4
- 238000004518 low pressure chemical vapour deposition Methods 0.000 title claims description 4
- 229910052719 titanium Inorganic materials 0.000 title abstract description 3
- RTAQQCXQSZGOHL-UHFFFAOYSA-N Titanium Chemical compound [Ti] RTAQQCXQSZGOHL-UHFFFAOYSA-N 0.000 title description 2
- 239000003990 capacitor Substances 0.000 claims abstract description 29
- 238000000137 annealing Methods 0.000 claims abstract description 24
- 239000004065 semiconductor Substances 0.000 claims abstract description 20
- 239000000758 substrate Substances 0.000 claims abstract description 18
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims abstract description 13
- GWEVSGVZZGPLCZ-UHFFFAOYSA-N Titan oxide Chemical compound O=[Ti]=O GWEVSGVZZGPLCZ-UHFFFAOYSA-N 0.000 claims abstract description 13
- 229910052710 silicon Inorganic materials 0.000 claims abstract description 13
- 239000010703 silicon Substances 0.000 claims abstract description 13
- OGIDPMRJRNCKJF-UHFFFAOYSA-N titanium oxide Inorganic materials [Ti]=O OGIDPMRJRNCKJF-UHFFFAOYSA-N 0.000 claims abstract description 12
- 150000004767 nitrides Chemical class 0.000 claims abstract description 10
- 229910052721 tungsten Inorganic materials 0.000 claims abstract description 10
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims abstract description 5
- 229920005591 polysilicon Polymers 0.000 claims abstract description 3
- 229910010413 TiO 2 Inorganic materials 0.000 claims description 23
- 239000000463 material Substances 0.000 claims description 13
- 229910052751 metal Inorganic materials 0.000 claims description 13
- 239000002184 metal Substances 0.000 claims description 13
- 239000003989 dielectric material Substances 0.000 claims description 12
- 238000000151 deposition Methods 0.000 claims description 7
- 238000005229 chemical vapour deposition Methods 0.000 claims description 6
- 239000010937 tungsten Substances 0.000 claims description 6
- 239000012298 atmosphere Substances 0.000 claims description 4
- VXUYXOFXAQZZMF-UHFFFAOYSA-N titanium(IV) isopropoxide Chemical compound CC(C)O[Ti](OC(C)C)(OC(C)C)OC(C)C VXUYXOFXAQZZMF-UHFFFAOYSA-N 0.000 claims description 4
- 238000005546 reactive sputtering Methods 0.000 claims description 3
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 claims description 2
- 229910052760 oxygen Inorganic materials 0.000 claims description 2
- 239000001301 oxygen Substances 0.000 claims description 2
- -1 tungsten nitride Chemical class 0.000 claims 4
- 239000012299 nitrogen atmosphere Substances 0.000 claims 1
- 229910052750 molybdenum Inorganic materials 0.000 abstract description 3
- 239000007772 electrode material Substances 0.000 description 11
- 238000003860 storage Methods 0.000 description 8
- MZLGASXMSKOWSE-UHFFFAOYSA-N tantalum nitride Chemical compound [Ta]#N MZLGASXMSKOWSE-UHFFFAOYSA-N 0.000 description 7
- 230000006870 function Effects 0.000 description 6
- 238000005245 sintering Methods 0.000 description 6
- 238000004519 manufacturing process Methods 0.000 description 5
- 230000000694 effects Effects 0.000 description 4
- ATJFFYVFTNAWJD-UHFFFAOYSA-N Tin Chemical compound [Sn] ATJFFYVFTNAWJD-UHFFFAOYSA-N 0.000 description 2
- 238000006243 chemical reaction Methods 0.000 description 2
- 238000000280 densification Methods 0.000 description 2
- 230000008021 deposition Effects 0.000 description 2
- 230000003292 diminished effect Effects 0.000 description 2
- 238000005516 engineering process Methods 0.000 description 2
- 239000011521 glass Substances 0.000 description 2
- 150000002739 metals Chemical class 0.000 description 2
- 238000012986 modification Methods 0.000 description 2
- 230000004048 modification Effects 0.000 description 2
- 238000001004 secondary ion mass spectrometry Methods 0.000 description 2
- 239000011232 storage material Substances 0.000 description 2
- 239000000126 substance Substances 0.000 description 2
- WFKWXMTUELFFGS-UHFFFAOYSA-N tungsten Chemical compound [W] WFKWXMTUELFFGS-UHFFFAOYSA-N 0.000 description 2
- ZOKXTWBITQBERF-UHFFFAOYSA-N Molybdenum Chemical compound [Mo] ZOKXTWBITQBERF-UHFFFAOYSA-N 0.000 description 1
- IVHJCRXBQPGLOV-UHFFFAOYSA-N azanylidynetungsten Chemical compound [W]#N IVHJCRXBQPGLOV-UHFFFAOYSA-N 0.000 description 1
- 230000004888 barrier function Effects 0.000 description 1
- 238000012512 characterization method Methods 0.000 description 1
- 230000007423 decrease Effects 0.000 description 1
- 238000009792 diffusion process Methods 0.000 description 1
- 238000010494 dissociation reaction Methods 0.000 description 1
- 230000005593 dissociations Effects 0.000 description 1
- 238000000313 electron-beam-induced deposition Methods 0.000 description 1
- 238000005259 measurement Methods 0.000 description 1
- 230000007246 mechanism Effects 0.000 description 1
- 239000011733 molybdenum Substances 0.000 description 1
- 230000009897 systematic effect Effects 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L28/00—Passive two-terminal components without a potential-jump or surface barrier for integrated circuits; Details thereof; Multistep manufacturing processes therefor
- H01L28/40—Capacitors
- H01L28/60—Electrodes
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66083—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by variation of the electric current supplied or the electric potential applied, to one or more of the electrodes carrying the current to be rectified, amplified, oscillated or switched, e.g. two-terminal devices
- H01L29/66181—Conductor-insulator-semiconductor capacitors, e.g. trench capacitors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
- H01L21/283—Deposition of conductive or insulating materials for electrodes conducting electric current
- H01L21/285—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation
- H01L21/28506—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers
- H01L21/28512—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers on semiconductor bodies comprising elements of Group IV of the Periodic Table
- H01L21/28568—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers on semiconductor bodies comprising elements of Group IV of the Periodic Table the conductive layers comprising transition metals
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- Engineering & Computer Science (AREA)
- Power Engineering (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Computer Hardware Design (AREA)
- Manufacturing & Machinery (AREA)
- Physics & Mathematics (AREA)
- Ceramic Engineering (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Semiconductor Memories (AREA)
- Semiconductor Integrated Circuits (AREA)
Abstract
In a process for fabricating electrodes for capacitor devices of semiconductor memory having low leakage, a titanium oxide film is deposited over a silicon substrate and the oxide annealed, a layer of top electrode is deposited over the annealed film and annealed. The electrode may be W, Mo or a nitride of W, Ta or Ti. The substrate may be n<SP>+</SP> silicon or polysilicon, the first annealing step conducted in dry O 2 at 800C, and the second in N 2 at 400-800C.
Description
2320128 PROCESS FOR FABRICATING LOW LEAKAGE CURRENT ELECTRODE FOR LPCV1)
TITANIUM OXIDE FILMS
BACKGROUND OF THE INVENTION
Field of the Invention
The present invention relates in general to a process for fabricating electrodes for the capacitor dielectric of senuiconductor memory devices, and in particular, to a process for fabricating low leakage current electrodes for capacitor storage dielectric of high-density semiconductor memory devices. More particularly, the present invention relates to a process for fabricating electrodes of storage dielectrics for high-density semiconductor memory devices having good capacitance and leakage current characteristics realized at low pressure in a cold wall reactor.
Technical Background
High-density serniconductor memory devices, especially DRAM devices, are being developed to the giga-bits per device level. Dielectric storage materials utilized in present-day mega-bit memory devices employing the current material technology in device fabrication will not carry these memory devices to storage densities higher than about 256M per device. This is primarily due to the limitation of the memory cell charge density they can hold and sustain for a reasonable period of time before requiring refreshing.
Among the materials considered for the storage dielectrics in the next generation of giga-bit memory devices, chemical vapor deposited TIO 2 films appear to be prorruising due to their inherent high permittivity and excellent step coverage characteristics. One serious problem, however, in utilizing these high dielectric constant storage materials is the high leakage current when they are implemented in the storage dielectrics utilizing the current technology. Until now, however, very little attention has been paid to the techniques used to reduce the leakage current in TIO 2 thus preventing the use of TIO 2 as a successful storage dielectric in the high- density memory devices. Systematic characterization of electrical properties of Ref.. 0487-US-PA/Final Filc: 0487USED0C low-pressure chemical vapor deposited TIO 2 treated under difYerent electrode materials is effectively unavailable at this stage.
SUMMARY OF THE INVENTION
It is therefore the primary object of the present invention to provide a process for fabricating electrodes for capacitor dielectrics of semiconductor memory devices having low leakage current characteristics.
It is another object of the present invention to provide a process for fabricating in low pressure environment capacitor dielectrics of semiconductor memory devices having low leakage current characteristics.
It is yet another object of the present invention to provide a process for fabricating with low cost the electrodes for capacitor dielectrics of semiconductor memory devices having low leakage current characteristics.
To achieve the above-identified objects, the present invention provides a process for fabricating electrodes for capacitor dielectrics of semiconductor memory devices with low leakage current characteristics. The process comprises the steps of first depositing a titanium oxide film over a semiconductor silicon substrate. The deposited titanium oxide film is then annealed. A layer of top electrode is then deposited on the annealed titanium oxide film. A second annealing procedure is then conducted. This step in the present invention is to simulate the high temperature process used in the borophosilicate glass (BPSG) densification or contact reflow commonly encountered in the manufacturing environment.
BRIEF DESCRIXTION OF THE DRAWING Other objects and features of the present invention are described VAth reference to the preferred embodiments exemplified below with the accompanying drawing in which FIGS. 1 a- 1 c schematically show the cross-sectional views of the storage dielectrics of the memory device together with the electrode thereof being fabricated in accordance with a preferred embodiment of the present invention as depicted from the selected process stages respectively., Ref.. 0487-US-PA/Final File: 04871JSF.DOC FIG. 2 shows the leakage current characteristics of CV1)-TIO 2 capacitors with various electrode materials before annealing, FIG. 3 shows the relationship between the Verit, work function and electrode materials before annealing; FIG. 4 shows the leakage current characteristics of the TIO 2 capacitors of FIG. 2 after 450 'C annealing; FIG. 5 shows the leakage current characteristics of the TiO 2 capacitors of FIG. 2 after 800 'C annealing; and FIG. 6 shows the Secondary Ion Mass Spectroscopy (SIMS) depth profiles of the WN/CVD-TiO 2 /Si capacitors after annealing.
DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENT
To provide for fabricating electrodes for capacitor dielectrics of senuconductor memory devices having low leakage current characteristics, the process of the present invention is exemplified in a preferred embodiment as described in the following paragraphs. Note that the dimensions in the FIGS. 1 a- 1 c are not drawn to the exact scale as they only schematically depict the cross-sectional views of the device being fabricated.
Step 1 Prepare a semiconductor silicon substrate as the basis for the fabrication of a high-density memory device utilizing the TiO 2 film as its memory cell capacitor dielectric layer.
As is seen in FIG. I a, the substrate 10 may, for example, be an n type silicon (Si) substrate, or an n polysilicon (poly-Si) substrate that may serve as the 25 bottom electrode of the memory cell capacitor for the fabricated memory device. Step 2 Deposit a TIO 2 film over the semiconductor silicon substrate.
In FIG. 1 b, the TIO 2 film 12 may be seen deposited in, for example, a cold-wall low-pressure chemical vapor deposition (UCVD) reactor on the n type Ref.. 0487-US-PA/Final File: 048MSF.DOC S] substrate or the n poly-SI substrate 10 that serves as the bottom electrode of the memory cell capacitor. The thin TiO 2 film 12 with a thickness of about 10 to 20 rim may be deposited at a temperature of about 350 'C, using tetra-isopropyltitanate (TPT, TI(P0C 3 H7),,) vapor and oxygen as the ambient atmosphere.
Step 3 Subject the deposited TiO 2 film to an annealing procedure.
The thermal annealing procedure of the deposited TiO 2 film 12 may be conducted in a dry 0 2 atmosphere, for example, at about 800 'C for about 30 rrfinutes.
io Step 4 Deposit a layer of top electrode on the TiO 2 film.
Top electrode for the capacitor dielectric layer, namely, the layer of top electrode 14 as is seen in FIG. lc may be deposited on the TiO 2 film 12 by, for example, the method of reactive sputtering, electron beam or chemical vapor deposition (CVD). The deposition material for the top electrode 14 may inQlude several metals and metal nitrides. For example, metals such as tungsten (W) and molybdenum (Mo), and metal nitrides such as tungsten ffitnide (WN), titanium dtride (TiN) and tantalum nitride (TaN) may be used as the matenial for top electrodes.
Step 5 Conduct an annealing procedure.
An annealing procedure is then conducted against the semiconductor device carried over the surface of the silicon substrate 10 at this stage. The annealing may be implemented in an N 2 environment for about 30 niinutes at the temperature of about 400-800 'C. It should be noted that this annealing procedure is conducted to simulate the high temperature process used, for example, in the borophosilicate glass (BPSG) densification or contact reflow commonly encountered in the manufacturing environment.
Ref.. 0487-US-PA/Final File.. 04MSFDOC The above-described procedural steps comprise the process of the present invention for fabricating the low leakage current electrode for the LPCVD TIO 2 capacitor storage dielectrics in high-density semiconductor memory devices.
In order to demonstrate the effects of annealing after deposition of the top electrode 0 14 as outlined in the above step 4, samples of different materials as mentioned above of top electrode 14 are annealed in N 2 for 30 min at 450 'C and 800 'C. Electrical characteristics of the TiO 2 layers are measured by PV, and C-V methods.
FIG. 2 shows the leakage current characteristics of TiO 2 semiconductor memory cell capacitors with several different electrode materials before being annealed in the above-described step 5. The electrodes of these device samples include those fabricated utilizing materials of W, Mo, TIN, WN, and TaN respectively, as is seen in the drawing. Negative bias is applied to the top electrode of these capacitors. Before annealing, leakage currents of capacitors with ruitride electrodes are smaller than those with metal ones, in particular, in the case of TaN electrode, a minimum leakage is obtained. The reason for using negative bias for the measurement of leakge current is due to the fact that electrons are injected from the electrode when negatively biased and the effect of electrode material selection over leakge current can be verified.
In order to verify the effects of electrode materials on the leakage 2 current, Vcrit, the voltage which induces a leakage current of 1 ptA/CM and the work function (0m) of the electrode before sintering are plotted for several different electrodes shown in Fig. 3. Before sintering, 0m of TaN, TiN, WN, W, and Mo are 5.41, 4.95, 5.00, 4.75, and 4.64 V, respectively. It is found that, in most electrode materials, VCM increases with increasing Orn. before sintering.
In other words, the leakage current decreases with increasing Orn, of the electrode. This is why TaN resultes in the lowest leakage current. These results indicate that the conduction mechanism in the case of negative bias is an electrodelimited type, and the energy barrier height for electrons at the top electrode/T10 2 interface limits the leakage current. Fig. 4 shows the leakage current characteristics Ref.. 0487-US-PA/Final File: 0487USED0C after annealing at a temperature of about 450 'C in the case of negative bias applying to the top electrode. When compared with the situation before the annealing procedure, all electrode materials in FIG. 4 are shown characterized with vast differences in leakage current behavlor. This is because the top electrode work function has a diminished influence on the leakage current. A comparison reveals the fact that capacitor with WN top electrode features the smallest leakage current. This is because WN has a better thermal stability than TaN, for example, and is able to sustain high temperature with virtuafly no dissociation. After the 450 'C sintering procedure, substantially no reaction or mutual diffusion occurs between the WN top electrode and the Ti02 layer therebelow, which allows for the lower leakage current. FIG. 6 confirms this fact, wherein VvrN and T102 remained intact after the 450 'C sintering procedure.
FIG. 5 shows the leakage current characteristics after annealing at a temperature of about 800 OC with the top electrode negatively biased. It confirms the results of Fig. 4, that the capacitor utilizing tungsten nitride (WN) top electrode has the lowest leakage current.
The examination to the above-descn'bed TiO 2 capacitor samples has shown that the work function of the top electrode material determines the electrical characteristics of a TiO 2 capacitor before sintering, and material with large work function, for example, TaN, has the lowest leakage. After 450 'C sintening, the reaction between TIO 2 and the top electrode reduces the work function difference among various materials, therefore the electrode effect is diminished. Thermal stability of the employed electrode material is a more important factor at this stage, and the " electrode capacitors exhibit the smallest leakage current.
Thus, the present invention has been able to demonstrate that the annealing procedure in N 2 for the TiO 2 capacitor with its top electrode formed can assist in unifying the electrode leakage current characteristics for various metal and metal nitride electrode materials. A process for the fabrication of low leakage current electrode for high-density memory cell capacitor is therefore possible in accordance with the disclosure of the present invention.
Ref.. 0487-US-PA/Final File: 0487USED0C While the present invention has been described by way of example and in terms of preferred embodiments, it is to be understood that the invention need not be limited to the disclosed embodiments. On the contrary, it is intended to cover various modifications and similar arrangements included within the spirit and scope of the appended claims, the scope of which should be accorded the broadest interpretation so as to encompass all such modifications and similar structures.
Ref.. 0487-US-PA/Final File: 0487USF.DOC
Claims (23)
1. A process for fabricating electrodes for capacitor dielectrics of semiconductor memory devices having low leakage current characteristics, said process comprising the steps of. preparing a semiconductor silicon substrate.. depositing a titanium oxide film over said semiconductor silicon substrate; annealing said deposited titanium oxide film; depositing a layer of top electrode on said annealed titanium oxide film; and subjecting a high temperature environment.
2. The process of claim 1, wherein said semiconductor silicon substrate is an n type silicon substrate, or an n type polysilicon substrate.
3. The process of claim 1, wherein said titanium oxide film is TiO 2 film.
4. The process of claim 3, wherein said TiO 2 film has a thickness of about 10 to 20 run.
5. The process of claim 4, wherein said TIO 2 film is deposited in a coldwall low-pressure chemical vapor deposition (LI?CVD) reactor.
6. The process of claim 5, wherein said TiO 2 film is deposited using tetra-isopropyl-titanate (TPT, Ti(i.OC 3 H 7)4) vapor and oxygen as the ambient atmosphere.
- 8 Rcf.. 0487-US-PA/Final File: 0487USED0C
7. The process of claim 6, wherein said TIO 2 film is deposited at a temperature of about 350 'C.
8. The process of claim 3, wherein said annealing of said deposited TIO 2 film is conducted in a dry 0 2 atmosphere.
9. The process of claim 8, wherein said annealing of said deposited TiO 2 film is conducted at a temperature of about 800 'C.
10. The process of claim 9, wherein said annealing of said deposited TiO 2 film is conducted for about 30 minutes.
11. The process of claim 3, wherein said top electrode layer is deposited on said TiO 2 film by a reactive sputtering method.
12. The process of claim 3, wherein said top electrode layer is deposited on said TiO 2 film by an electron beaming method.
13. The process of claim 3, wherein said top 'electrode layer is 20 deposited on said TiO 2 film by a chemical vapor deposition (CVD) method.
14. The process of claim 3, wherein said top electrode layer is deposited on said TiO 2 film by a reactive sputtering method, and said top electrode layer is deposited utilizing a metal nitride material. -
15. The process of claim 14, wherein said metal nitride material is tungsten nitride.
- 9 Ref.. 0487-US-PA/Final File: 0487USI7DOC
16. The process of claim 3, wherein said top electrode layer is deposited on said TIO 2 film by an electron beaming method, and said top electrode layer is deposited utilizing a metal nitride material.
17. The process of claim 16, wherein said metal nitride material is tungsten nitride.
18. The process of claim 3, wherein said top electrode layer is deposited on said TiO 2 film by a chemical vapor deposition method, and said top electrode layer is deposited utilizing a metal nitride material.
19. The process of claim 18, wherein said metal nitride material is tungsten nitride.
is
20. The process of claim 1, wherein the step of subjecting said high temperature environment is in an N2atmosphere.
21. The process of claim 20, wherein said high temperature environment is at a temperature of about 400-800 'C.
22. The process of claim 21, wherein the step of subjecting said high temperature environment is conducted for about 30 n-nutes.
23. A process for fabricating electrodes for capacitor dielectrics of semiconductor memory devices having low leakage current characteristics, said process compnsing the steps of.
preparing a semiconductor silicon substrate; depositing a titanium oxide film over said semiconductor silicon substrate,.
annealing said deposited titanium oxide film, Ref.. 0487-US-PA/Final File: 0487LISF.DOC depositing a layer of tungsten nitride top electrode on said annealed titanium oxide film; and subjecting a high temperature of about 400-800 OC in an N 2 environment for about 30 minutes.
Priority Applications (4)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| GB9625144A GB2320128B (en) | 1996-04-10 | 1996-12-03 | Process for fabricating low leakage, current electrode for LPCVD itianium oxide films |
| DE19651106A DE19651106A1 (en) | 1996-04-10 | 1996-12-09 | Mfg. low-leaking current electrode for LPCVD titania film |
| FR9700284A FR2747507B1 (en) | 1996-04-10 | 1997-01-14 | METHOD FOR MANUFACTURING A LOW LEAKAGE CURRENT ELECTRODE FOR TITANIUM OXIDE FILMS |
| JP09064899A JP3074469B2 (en) | 1996-04-10 | 1997-03-18 | Method for producing low leakage current electrode for forming low pressure chemical vapor deposited titanium oxide coating |
Applications Claiming Priority (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| TW85104195A TW285757B (en) | 1996-04-10 | 1996-04-10 | The manufacturing method of low-leaking current electrode for LPCVD TiO film |
| GB9625144A GB2320128B (en) | 1996-04-10 | 1996-12-03 | Process for fabricating low leakage, current electrode for LPCVD itianium oxide films |
Publications (3)
| Publication Number | Publication Date |
|---|---|
| GB9625144D0 GB9625144D0 (en) | 1997-01-22 |
| GB2320128A true GB2320128A (en) | 1998-06-10 |
| GB2320128B GB2320128B (en) | 2001-11-14 |
Family
ID=26310538
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| GB9625144A Expired - Fee Related GB2320128B (en) | 1996-04-10 | 1996-12-03 | Process for fabricating low leakage, current electrode for LPCVD itianium oxide films |
Country Status (4)
| Country | Link |
|---|---|
| JP (1) | JP3074469B2 (en) |
| DE (1) | DE19651106A1 (en) |
| FR (1) | FR2747507B1 (en) |
| GB (1) | GB2320128B (en) |
Family Cites Families (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5745968A (en) * | 1980-08-29 | 1982-03-16 | Ibm | Capacitor with double dielectric unit |
-
1996
- 1996-12-03 GB GB9625144A patent/GB2320128B/en not_active Expired - Fee Related
- 1996-12-09 DE DE19651106A patent/DE19651106A1/en not_active Withdrawn
-
1997
- 1997-01-14 FR FR9700284A patent/FR2747507B1/en not_active Expired - Fee Related
- 1997-03-18 JP JP09064899A patent/JP3074469B2/en not_active Expired - Lifetime
Also Published As
| Publication number | Publication date |
|---|---|
| JP3074469B2 (en) | 2000-08-07 |
| GB9625144D0 (en) | 1997-01-22 |
| JPH10116967A (en) | 1998-05-06 |
| GB2320128B (en) | 2001-11-14 |
| FR2747507A1 (en) | 1997-10-17 |
| DE19651106A1 (en) | 1997-10-16 |
| FR2747507B1 (en) | 1998-12-04 |
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Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| PCNP | Patent ceased through non-payment of renewal fee |
Effective date: 20020214 |