GB2317785A - Formatting signal timing data - Google Patents

Abstract

A multichannel receiver is used in analysis of a radio environment, in particular in the determination of various characteristics of pulse signals received on channels A-N. This entails the passing on by the receiver of data concerning the carrier frequencies, start times and durations of the various received pulses to a processor 9 over a common bus. In order to simplify the processing the sets of data should ideally be passed to the processor in the same chronological order as that in which the corresponding pulses are received. However this can result in data relating to many subsequent short pulses having to wait until the end of a previous long pulse. In order to mitigate this problem data concerning the start times is passed to the processor in the correct chronological order but is only accompanied by duration information if the duration is shorter than a predetermined amount. For longer-duration pulses the finish time is passed on later, allowing other pulse signals to be processed in the interim.

Description

DESCRIPTION FORMATTING SIGNAL TIMING DATA This invention relates to a method of generating on a common output of a multichannel radio receiver data representative of the start times and durations of signals received in the various channels. The invention also relates to a multichannel radio receiver including means for performing such a method.

There is sometimes a need to analyse the radio environment to identify the various signals present and ascertain various characteristics thereof. If the signals of interest are in the form of pulses then these characteristics may include, for example, carrier frequency, pulse duration and time of arrival. If the environment is very cluttered it can be helpful to use a multichannel receiver to receive the various signals, i.e. a receiver comprising a multiplicity of parallel channels each of which corresponds to a band of received carrier frequencies. (In such a receiver the various channels may be completely independent of each other, in which case the receiver will in effect be constituted by a multiplicity of single-channel receivers.

Alternatively part of the signal path(s) from a receiving aerial or aerial array may be common to some or all of the channels, this or these paths being split at some point into the various channels by, for example, a filter bank the various outputs of which feed respective ones of the parallel channels). Each received signal, or a signal derived therefrom e.g. by frequency translation, is directed to a particular channel in accordance with the received carrier frequency. In addition to providing an at least coarse indication of the carrier frequencies of the various signals received the provision of the parallel channels results in each channel having to cope with a rate of occurrence of events (e.g.

starts and finishes of received pulses) which is in general appreciably smaller than that which would occur if ?1l the signals travelled through the same channel.

While it is of course possible for an analysis process to be carried out on the signals passing through each channel individually, i.e. without reference to the signals passing through the other channels, there are circumstances in which the result of such an analysis process will be incomplete. In particular it may be the case that a transmitter of a succession of pulses employs so-called "frequency hopping"; successive pulses have carrier frequencies which differ from each other so that these successive pulses may be assigned to different channels of the receiver. If this is the case and the signals passing through each channel were to be analysed independently, it would be impossible for the successive pulses to be recognised as belonging to one and the same succession of pulses. Thus in general it is desirable that a collective analysis process be carried out on the signals passing through all the channels, which means that signals derived from all the channels will have to be fed to a common processor.

If pulse parameters of interest to the processor are carrier frequency, time of arrival and duration respectively, then for ease of processing it is highly desirable that data representing these parameters for each pulse be sent to the processor as a group and, moreover, that these groups are sent in the same chronological order as the times of arrival or start times of the corresponding pulses. However, to do this gives rise to problems because the complete data required to make up a group, in particular the data representative of the pulse duration, is not available until the pulse has ended. While waiting for the end of a long pulse, data sets for many short pulses (at other frequencies) which have later start times may become available from other channels and have to be stored. This storage would require an appreciable amount of memory configured as a chronologically-ordered first-in/first-out queue with the capability of completing partial data sets as and when the data becomes available. Within a given data set representation of frequency, start time and pulse duration can require a considerable number of bits. If the longest pulse is, say 400us and the highest pulse repetition frequency 300kHz, 120 data sets would have to be stored for each high pulse repetition frequency emitter while waiting for the end of such a 400gs pulse. The configuration of the memory would therefore be difficult, being short and wide, and the memory management would be difficult because of the search requirement when updating some of the fields. It is an object of the present invention to ease the memory requirements by providing a different data format.

According to one aspect the invention provides a method of generating on a common output of a multichannel radio receiver data representative of the start times and durations of signals received in the various channels, in which method representations of the start times are generated in the same chronological order as the corresponding start times, a representation of the elapsed time between the start and finish of each signal is generated together with the corresponding start time representation if and only if the corresponding elapsed time is less than a predetermined amount, and a representation of the corresponding finish time is itself generated subsequently otherwise.

It has now been recognised that the aforesaid memory requirements can be considerably eased if short-duration signals (duration less than the "predetermined amount'1) are treated differently to longer-duration signals, more particularly if data entities including representations of both start time and duration are outputted if and only if the duration is less than the "predetermined amount", separate data entities containing representations of the start time and the finish time respectively of the relevant signals being outputted otherwise (possibly interspersed with data entities relating to other signals). This means that outputting of data relating to a given signal need only be delayed by the continuing presence of a previous signal for a time related to the "predetermined amount" rather than to the actual duration of the previous signal. Moreover (subsequent) association of the finish time of a given signal with the start time thereof need only be necessary if the duration of the signal is equal to or greater than the "predetermined amount".

Furthermore, the amount of data (number of bits) outputted for a short-duration signal can be relatively small because the required representation of elapsed time (to the required resolution) has a maximum value equal to the predetermined amount.

Whereas measurement of the durations of the various signals is conveniently carried out by means of respective timers assigned to the relevant channels the generation of the various signals on the common output is preferably under a central control. A convenient way in which this can be done is to arrange that representations of said start times1 and representations of the finish times of signals whose durations are at least as long as said predetermined amount, are stored together with respective representations of the channels to which these start and finish times relate in a common first-in/first-out memory in the chronological order in which these start and finish times occur, that the durations of signals for which the elapsed time between the start and finish thereof is less than the predetermined amount are measured by respective timers assigned to the relevant channels and representations thereof are stored in respective buffer memories assigned to the relevant channels, and that the time representations stored in the first-in/first-out memory are read out in chronological order onto the common output each together with the presentation to said common output of a code derived from the relevant channel, said code comprising a representation of the duration of the signal to which the associated time representation relates if this duration was least than the predetermined amount and otherwise comprising an indication of whether the associated time representation is of a start time or a finish time.

According to another aspect the invention provides a multichannel radio receiver including, assigned to each channel, a respective detector for the starts and finishes of signals received in the corresponding channel and a respective timer, responsive to output signals from the relevant detector, for timing the durations of the received signals should these be less than a predetermined amount, the receiver also including start and finish time recording means arranged to respond to the output signals of each detector by recording the start times of the received signals, and also the finish times thereof should the durations of the corresponding signals be not less than said predetermined amount, and sequencing means arranged to cause representations of the recorded start times to be presented to a common output in the same chronological order as the corresponding start times, to cause a representation, derived from the corresponding timer, of the elapsed time between the start and finish of the corresponding received signal to be represented to the common output together with each start time representation if and only if the corresponding elapsed time is less than a predetermined amount, and to cause a representation of the recorded finish time of the corresponding signal to be presented to the common output subsequently otherwise.

Embodiments of the invention will now be described, by way of example, with reference to the accompanying diagrammatic drawings in which: Figure 1 is a block diagram of a first embodiment, Figure 2 is a flow diagram of a program which may be included in a processor which forms part of the embodiment of Figure 1, and Figure 3 is a flow diagram of a program which may be included in another processor which forms part of the embodiment of Figure 1.

In Figure 1 a multichannel radio receiver has an aerial 1.

The signals received by this aerial are allocated to individual ones of N channels (denoted by suffixes A,B,...N) on the basis of their carrier frequencies by means of a filter bank 2. Each channel comprises, in cascade, an RF and IF amplifier 3, a demodulator 4, a threshold detector 5 and a "channel" processor 6.

Three-state data output ports 7 of the processors 6 are connected in parallel via a common output bus 8 to an input port 19 of a "destination" processor 9. Further outputs 10 of the processors 6 are connected to respective inputs 11 of a common control processor 12, and respective outputs 13 of processor 12 are connected to further inputs 14 of the processors 6. An output 15 of processor 9 is connected to a further input 16 of processor 12 and a further output 17 of processor 12 is connected to a further input 18 of processor 9. An input port 20 of processor 12 is connected to the output 21 of a real-time clock 22. An output port 23 of processor 12 is connected via further bit lines 8' of the bus 8 to further bit inputs 19' of the input port 19 of destination processor 9.

Each channel processor 6 is in the form of a suitably programmed microcomputer and in conventional manner comprises a central processing unit and program/data store signified collectively by a block 24. Furthermore each processor 6 includes a timer 25 and an output buffer 26 (which may in fact form part of the store in the block 24).

The control processor 12 is likewise in the form of a suitably programmed microcomputer and in conventional manner comprises a central processing unit and program/data store signified collectively by a block 27. Furthermore processor 12 includes a first-in/first-out (FIFO) buffer 28 (which may in fact form part of the store in the block 27). Each storage location of buffer 28 comprises, inter alia, a bit field comprising a respective bit location corresponding to each of the channels A,B,...N.

The destination processor 9, which does not strictly form part of the multichannel receiver, is again in the form of a suitably programmed microcomputer. Its function is to analyse etc. the data presented to its input port 19,19' from the bus 8,8' and communicate the results to the outside world. The detailed manner in which it does this is irrelevant in the present context and will therefore not be elaborated upon.

When a signal pulse having a given carrier frequency is received by the aerial 1 it is directed by the filter bank 2 to the channel A,B,...N which is assigned to the frequency band which includes the given carrier frequency. Within the relevant channel the pulse is amplified and frequency-translated in the relevant RF/IF amplifier 3, demodulated in the relevant demodulator 4 and the demodulation result is presented to the relevant threshold detector 5. Detector 5 produces, for example, a logic "1" when its threshold is exceeded and a logic "0" otherwise. The presence of a logic "1" and "0" on the threshold detector output therefore indicates whether or not a signal pulse having a carrier frequency lying within the frequency band assigned to the relevant channel is being received at any given time.

Each processor 6 is programmed to respond (a) to a change from logic "0" to logic "1" in the output signal of the corresponding detector 5, i.e. to the start of reception of a signal in the relevant channel, by starting its timer 25 (which may take the form of a clocked counter which stops when its maximum count is reached) and generating a LOAD FIFO signal on its output 10, this last signal therefore being applied to that input 11 of the control processor 12 which corresponds to the relevant channel. The control processor is programmed to respond to reception of this LOAD FIFO signal by reading the current output of the real-time clock 22 into the FIFO 28 together with a logic "1" into that bit location of the relevant aforesaid bit field which corresponds to the channel A,B,...N from which the signal was received. (A logic "1" may be loaded into more than one bit location of the relevant bit field if a plurality of channel processors generate a LOAD FIFO signal simultaneously) Each processor 6 is furthermore programmed to respond (b) to time-out of its timer 25, i.e. its timer 25 reaching its maximum count, and also to a change from logic "1" to logic "0" in the output signal of the corresponding detector 5, i.e. to the finish of reception of a signal in the relevant channel, if this change should occur before time-out of the relevant timer 25 occurs, by reading the current output of the timer 25 into its output buffer 26 and then resetting (but not restarting) its timer 25. (The timer reading read into the buffer will be greater than zero and less than or equal to that corresponding to time-out).

Each processor 6 is furthermore programmed to respond (c) to a change from logic "1" to logic "0" in the output signal of the corresponding detector 5, i.e. to the finish of reception of a signal in the relevant channel, if this signal should occur after time-out of the relevant timer occurs, by generating a LOAD FIFO signal on its output 10, this last signal therefore being applied to that input 11 of the control processor 12 which corresponds to the relevant channel. The programmed response also entails the reading of the current content of its timer 25 (which will be zero) into its output buffer 26. The control processor 12 is programmed (as before) to respond to reception of the LOAD FIFO signal on the relevant one of its inputs 11 by reading the current output of the real-time clock 22 into the FIFO 28 together with a logic "1" into that bit location of the aforesaid relevant bit field which corresponds to the channel A,B,...N from which the signal was received.

In addition to the programmed responses involving loading FIFO 28 indicated above, (which may be carried out by means of an interrupt routine) the control processor 12 is programmed to perform a cyclic main program in which it examines in turn the bit locations of the aforesaid bit field currently present at the output of the FIFO 28 for a logic "1" to determine to which channel processor(s) 6 and hence channel(s) A,B,...N the associated real time data (if any) relates. As and when it encounters such a logic "1" it is programmed to generate an OUTPUT DATA signal on the corresponding output 13. Reception of this signal at the input 14 of the corresponding channel processor 6 constitutes an instruction to that channel processor to put the timer reading data in its output buffer 26 onto the bus 8. The channel processor is programmed to respond appropriately and generate a DATA OUTPUTTED signal on its output 10 when this has been done. Control processor is programmed to respond to reception of this DATA OUTPUTTED signal at its corresponding input 11 by putting the said associated real time data together with a code indicating to which channel A,B...,N this data corresponds, and hence the frequency band within which the carrier frequency of the relevant signal pulse lies, onto the lines 8' of the common bus and generate a signal on its output 17 to indicate to destination processor 9 that data is available at its input 19,19'. Destination processor 9 generates a signal on its output 15 when it has accepted this data and control processor 12 is programmed to respond to reception of this signal at its input 16 by removing the said real-time data from the bus portion 8' and generate a CANCEL DATA signal on that one of its outputs 13 which corresponds to that channel processor 6 which is at present putting data onto the bus 8. The relevant channel processor 6 is programmed to respond to this CANCEL DATA signal by removing the data from the bus 8, clearing its output buffer 26 of the removed data and generating a DATA CANCELLED signal on its output 10 indicating to control processor 12 that this has been done.

Control processor 12 is programmed to respond to reception of this DATA CANCELLED signal on its corresponding input 11 by continuing its investigation, if incomplete, of the bit locations of the aforesaid bit field at the output of FIFO 28 for further logic "l"s, and sending further OUTPUT DATA signals to the corresponding processors 6 if any are found. If no further logic "l"s are found it is programmed to clock the FIFO 28 so that the next item of real-time data and associated logic "l"(s) becomes available at the FIFO output. (The signal path between the outputs 10 of the channel processors 6 and the corresponding inputs 11 of the control processor 12, and between the outputs 13 of the control processor 12 and the corresponding inputs 14 of the channel processors 6 may each be multiple in the interests of differentiation between the various types of signal or command carried by these paths.

Alternatively each path may consist of a single line, the differentiation between the different signals or commands carried by each line being obtained by using respective serial codes for the different commands).

The net result of the above actions is that data entities each representative of the start time and carrier frequency of a signal received by the aerial 1 are presented to the input 19,19' of destination processor 9 in the same chronological order as that in which these start times occur. If the duration of the relevant signal is less than the time-out period T of the timers 25, data representative of this duration is included in the relevant data entity. If the duration of the relevant signal is equal to or greater than the time-out period T this fact is merely indicated by the inclusion in the relevant data entity of data representative of the time-out period T. In the latter case a further data entity representative of the finish time and frequency of the relevant signal is presented to the input 19,19' of destination processor 9 after the relevant signal finishes, the fact that this data entity is representative of a finish time being indicated by the inclusion therein of data representative of a zero reading from the relevant timer 25.

Of course further information may be included in the aforesaid data entities, if desired, in particular those portions thereof derived from the channel processors 6. Thus, if each channel processor 6 is also fed directly from the output of the corresponding demodulator 4 via an analog-to-digital converter, the processors can each be arranged to include data representative of the amplitude of the relevant signal in each set of data outputted from its buffer 26 into the common bus 8. As another example each channel may include a frequency analyser by which the carrier frequency of a signal directed to the relevant channel by the filter bank 2 can be determined relatively accurately, the relevant processor 6 then being arranged to include data representative of this accurately-determined frequency of the relevant signal in each set of data outputted from its buffer 26 onto the common bus 8.

Such further data will, of course, take a finite time to produce, and this could result in a delay in each channel processor loading its output buffer 26 each time, with a possible consequential delay between the control processor 12 instructing a given channel processor 6 to put the data in its output buffer 26 onto the bus 8 and the channel processor actually doing this. However, this will have no effect on the order in which the various data entities are presented to the output bus, because the control processor relies each time on a signal from the relevant channel processor that it has in fact put the data in its output buffer onto the bus.

The various times of occurrence recorded by the control processor 12 in the FIFO 28 could of course alternatively be recorded in the relevant channel processors, and outputted together with the corresponding other data from their output buffers at the appropriate times. However, this will entail communications from the real-time clock 22 to each channel processor 6, so recording of these times (in addition to their chronological orders) by the control processor 12 is preferred.

The time to which the real-time clock 22 is referenced is, of course, arbitrary.

The operations performed by the control processor 12 and the destination processor 9 may, of course, be performed by one and the same processor or suitably programmed microcomputer, if desired.

Figure 2 is a flow chart of an example of a cyclic main program for the control processor 12, as referred to above. In Figure 2 the letters "Y" and "N" denote "yes" and "no" respectively and the various blocks have the following significances.

30 - Start 50 - Set variable n = 0.

51 - Increment variable n.

52 - Is variable n equal to N + 1? 53 - Clock FIFO 28 and set variable n = 0.

31 - Is a logic "1" present in the nth bit location of the bit field at the output of FIFO 28? 32 - Generate on OUTPUT DATA command at that output 13 which corresponds to the channel corresponding to bit location n to instruct the relevant channel processor 6 to put the data in its output buffer 26 onto the bus 8.

33 - Is there a DATA OUTPUTTED signal at that input 11 which corresponds to the channel processor 6 instructed in step 32? 34 - Put real-time data at output of FIFO 28 together with a code indicating to which channel A,B,...N this data corresponds, and hence the frequency band within which the carrier frequency of the relevant signal pulse lies onto the line 8' of the bus and generate signal on output 17 indicating to destination processor 9 that data is available at its input 19,19'.

35 - Is there a signal at input 16 indicating that destination processor 9 has accepted the data from the bus 8,8'.

36 - Remove the real-time data and channel-identifying code from the bus line 8' and generate a CANCEL DATA command at that output 13 which corresponds to the channel processor 6 which is at present putting data onto the bus 8 to instruct the relevant channel processor to remove this data from the bus and clear its output buffer.

37 - Is there a DATA CANCELLED signal present at that input 11 which corresponds to the channel processor commanded in step 36 indicating that the channel processor has removedits data from the bus 8? The loading of FIFO 28 with the current output of real-time clock 22 and a channel-identifying logic "1" in response to a LOAD FIFO instruction from a given channel processor can be achieved by way of an interrupt routine which interrupts the main program of Figure 2, as indicated previously.

Figure 3 is a flow chart of an example of a cyclic main program which may be included in each channel processor 6 of Figure 1. In Figure 3 the various blocks have the following significances.

40 - Start.

41 - Has logic signal at output of corresponding detector 5 changed from "0" to "1"? 42 - Start timer 25 and generate a LOAD FIFO instruction at output 10 to instruct control processor 12 to load FIFO 28 with the current output of real-time clock 22 together with a logic "1" in that bit location of the bit field at the output of FIFO 28 which corresponds to the channel in which the relevant channel processor is included.

43 - Has timer 25 timed out? 44 - Is output signal of corresponding detector 5 logic "0"? 45 - Read output of timer 25 into output buffer 26.

46 - Reset timer 25 without restarting it 47 - Is output signal of corresponding detector 5 logic "0"? 48 - Generate a LOAD FIFO instruction at output 10 to instruct control processor 12 to load FIFO 28 with the current output of real-time clock 22 together with a logic "1" in that bit location of the bit field at the output of FIFO 28 which corresponds to the channel in which the relevant channel processor is included.

The aforesaid responses by the channel processors 6 to reception of OUTPUT DATA and CANCEL DATA instructions from the central processor 12 may be obtained by respective routines interrupting the main program of Figure 3. Thus each processor 6 may be programmed to respond to reception of an OUTPUT DATA instruction by performing an interrupt routine in which it first checks that its output buffer contains the relevant data (and waits until it does if the result of the check is negative) and then puts this data onto the bus 8 and generates a DATA OUTPUTTED signal on its output 10. Similarly each processor 6 may be programmed to respond to reception of a CANCEL DATA instruction by performing an interrupt routine in which it ceases putting data onto the bus 8, cancels this data from its output buffer 26, and generates a DATA CANCELLED signal on its output 10.

The optimum time-out periods of the timers 25 will, of course, depend on the characteristics of the signals normally present in the radio environment, and will normally be chosen to be longer than most of the pulses usually present.

From reading the present disclosure, other modifications will be apparent to persons skilled in the art. Such modifications may involve other features which are already known in the design, manufacture and use of multichannel radio receivers and component parts thereof and which may be used instead of or in addition to featuresalready described herein. Although claims have been formulated in this application to particular combinations of features, it should be understood that the scope of the disclosure of the present application also includes any novel feature or any novel combination of features disclosed herein either explicitly or implicitly or any generalisation thereof, whether or not it relates to the same invention as presently claimed in any claim and whether or not it mitigates any or all of the same technical problems as does the present invention. The applicants hereby give notice that new claims may be formulated to such features and/or combinations of such features during the prosecution of the present application or of any further application derived therefrom.

Claims (6)

CLAIMS:

1. A method of generating on a common output of a multichannel radio receiver data representative of the start times and durations of signals received in the various channels, in which method representations of the start times are generated in the same chronological order as the corresponding start times, a representation of the elapsed time between the start and finish of each signal is generated together with the corresponding start time representation if and only if the corresponding elapsed time is less than a predetermined amount, and a representation of the corresponding finish time is itself generated subsequently otherwise.

2. A method as claimed in Claim 1, wherein representations of said start times, and representations of the finish times of signals whose durations are at least as long as said predetermined amount, are stored together with respective representations of the channels to which these start and finish times relate in a common first-in/first-out memory in the chronological order in which these start and finish times occur, wherein the durations of signals for which the elapsed time between the start and finish thereof is less than the predetermined amount are measured by respective timers assigned to the relevant channels and representations thereof are stored in respective buffer memories assigned to the relevant channels, and wherein the time representations stored in the first-in/first-out memory are read out in chronological order onto the common output each together with the presentation to said common output of a code derived from the relevant channel, said code comprising a representation of the duration of the signal to which the associated time representation relates if this duration was least than the predetermined amount and otherwise comprising an indication of whether the associated time representation is of a start time or a finish time.

3. A multichannel radio receiver including, assigned to each channel, a respective detector for the starts and finishes of signals received in the corresponding channel and a respective timer, responsive to output signals from the relevant detector, for timing the durations of the received signals should these be less than a predetermined amount, the receiver also including start and finish time recording means arranged to respond to the output signals of each detector by recording the start times of the received signals, and also the finish times thereof should the durations of the corresponding signals be not less than said predetermined amount, and sequencing means arranged to cause representations of the recorded start times to be presented to a common output in the same chronological order as the corresponding start times, to cause a representation, derived from the corresponding timer, of the elapsed time between the start and finish of the corresponding received signal to be represented to the common output together with each start time representation if and only if the corresponding elapsed time is less than a predetermined amount, and to cause a representation of the recorded finish time of the corresponding signal to be presented to the common output subsequently otherwise.

4. A receiver as claimed in Claim 3, including a first-in/first-out memory for storing the recorded start and finish times.

5. A method of generating on a common output of a multi-channel radio receiver data representative of the start times and durations of signals received in the various channels, substantially as described herein with reference to the drawings.

6. A multi-channel radio receiver substantially as described herein with reference to the drawings.

6. A multi-channel radio receiver substantially as described herein with reference to the drawings.

Amendments to the claims have been filed as follows I. A method of generating on a common output of a multichannel radio receiver data representative of the start times and durations of signals received in the various channels, in which method representations of the start times are generated in the same chronological order as the corresponding start times, a representation of the elapsed time between the start and finish of each signal is generated together with the corresponding start time representation if and only if the corresponding elapsed time is less than a predetermined amount, and a representation of the corresponding finish time is itself generated subsequently otherwise.

2. A method as claimed in Claim 1, wherein representations of said start times, and representations of the finish times of signals whose durations are at least as long as said predetermined amount, are stored together with respective representations of the channels to which these start and finish times relate in a common first-in/first-out memory in the chronological order in which these start and finish times occur, wherein the durations of signals for which the elapsed time between the start and finish thereof is less than the predetermined amount are measured by respective timers assigned to the relevant channels and representations thereof are stored in respective buffer memories assigned to the relevant channels, and wherein the time representations stored in the first-in/first-out memory are read out in chronological order onto the common output each together with the presentation to said common output of a code derived from the relevant channel, said code comprising a representation of the duration of the signal to which the associated time representation relates if this duration was Less than the predetermined amount and otherwise comprising an indication of whether the associated time representation is of a start time or a finish time.

3. A multichannel radio receiver including, assigned to each channel, a respective detector for the starts and finishes of signals received in the corresponding channel and a respective timer, responsive to output signals from the relevant detector, for timing the durations of the received signals up to a predetermined duration, the receiver also including start and finish time recording means arranged to respond to the output signals of each detector by recording the start times of the received signals, and also the finish times thereof should the durations of the corresponding signals be not less than said predetermined duration, and sequencing means arranged to cause representations of the recorded start times to be presented to a common output in the same chronological order as the corresponding start times, to cause a representation, derived from the corresponding timer, of the elapsed time between the start and finish of the corresponding received signal to be presented to the common output together with each start time representation if and only if the corresponding elapsed time is less than said predetermined duration, and to cause a representation of the recorded finish time of the corresponding signal to be presented to the common output subsequently otherwise.

4. A receiver as claimed in Claim 3, including a first-in/first-out memory for storing the recorded start and finish times.

S. A method of generating on a coupon output of a multi-channel radio receiver data representative of the start times and durations of signals received in the various channels, substantially as described herein with reference to the drawings.