GB2317774A - Scrambling and descrambling apparatus - Google Patents

Abstract

A scrambling apparatus scrambles a video signal by superimposing a scrambling signal on a video signal to be scrambled in a pay television system. In the apparatus, horizontal and vertical sync separators 604,606 separates horizontal and vertical synchronizing signals from a video signal received to be scrambled, respectively. A counter circuit 608 counts the horizontal synchronizing signal M.SYNC in response to the vertical synchronizing signal V.SYNC from the vertical sync separator 606 to generate a count signal CS when the count reaches a first predetermined value. A reference clock generator 610 generates a reference clock signal RC based on the horizontal synchronizing signal H.SYNC from the horizonal sync separator 604. A switch 612 selectively transfers either one of an unscrambled signal of the video signal P1 or a scrambling pulse P2. A control section 614 controls the switch 612 based on the horizontal synchronizing signal H.SYNC from the horizontal sync separator 604, the count signal CS from the counter circuits 608, and the reference clock signal RC from the reference clock generator 610.

Description

SCRAMBLING AND DESCRAMBLING APPARATUS Background of the Invention 1. Field of the Invention The present invention relates to a pay television system, more particularly, an apparatus for scrambling a video signal by superimposing a scrambling signal on a video signal to be scrambled in a pay television system and an apparatus for descrambling the scrambled video signal by using a descrambling signal.

2. Description of the Prior Art The need for scrambling a video signal is well known in the art. Various methods of scrambling signals are known. One method involves inverting a signal or a portion of a signal at the transmitter side and reinverting the signal or portion at the receiver side to reconstruct the proper video signal.

At the transmitter side, the portion of the video signal that is inverted is inverted about a selected axis. Typically, this axis may be a function of system parameters. For example, if +100 IRE represents the peak white level of a video signal and -40 IRE represents the sync tip level or the most negative portion of the signal, then a likely choice for the axis of inversion would be +30 IRE. This point is half way between the most negative and most positive portions of the signal. Therefore, if the most negative portion of the signal is inverted about this axis it should not exceed the most positive portion (+100 IRE).

Similarly, if the white peak level is inverted about this axis, it will not fall below the most negative portion (-100 IRE).

For a better understanding of video signals and some inversion schemes, attention is now drawn to FIG.

1A to 1D illustrating a sketch of a video signal. This figure and the labelled parts thereof is intended to serve as a model to assist the reader in being able to identify some key portions of the video signals of this and other figures described in the specification.

With reference to FIG. 1A, it can be seen that each line of video signals is characterized by a horizontal sync pulse 101, represented by the sync tip pulse or the most negative state of the video signal.

This pulse normally lasts 4.7 microseconds and is repeated 15,734 times each second in the NTSC television system used in the U.S. and many other countries. Following the sync pulse, the signal voltage returns to the blanking level or black level, which is used as a reference level. By common convention, the amplitude of the blanking level is considered to be 0 IRE, a unit of measure adopted by the Institute of Radio Engineerings. The sync tip is at a level of -40 IRE, while peak white is at a level of +100 IRE. This maximum normal excursion of the TV signal of 140 IRE is conventionally equated to 1 volt peak to peak, though other voltage levels are sometimes employed internally to a particular piece of equipment.

Following the return to a blanking level after a sync tip portion, and after a delay known as the breezeway 102, the colour burst 103, occurs. This colour burst is composed of eight cycles (nominally) of the colour subcarrier 3.58 MHz in NTSC transmission.

The amplitude and more importantly, the phase of the colour burst are essential to proper recovery of the colour information, as is well understood by those skilled in the art. After a delay following the colour burst, the active video interval indicated generally as 107, begins. The time from the end of the sync pulse to the beginning of active video is called the back porch 104, shown twice to emphasize that the signal repeats.

The entire interval from the beginning of the front porch to the end of the back porch is collectively known as the horizontal blanking interval 105.

The active video interval 107 actually consists of various voltages representing the brightness (luminance) of the image, plus a colour subcarrier (not shown), which carries colour saturation ("purity") information as amplitude modulation, and colour value ("tint") represented by it's phase with respect to colour burst 103. This pattern of sync and active video is repeated for 252,5 lines (including vertical blanking). This number of lines constitutes one "field" and is followed by an interleaved second field. The two fields together make up a "frame", or one complete picture. Typically, the frame rate is 30/sec, that is, frames are produced 30 times each second.

FIGs. 2 to 4 illustrate some of the various ways in which a video signal may be inverted. In FIG. 2 the active video line is inverted but the horizontal blanking interval HBI is not. This is known by those skilled in the art as inverted video with non-inverted sync. FIG. 3 illustrates an inverted HBI with normal active video. FIG. 4 illustrates a combination of the two, that is, inverted video and inverted HBI.

In the case of active video inversion only, FIG.

2, the sync occurs normally, however the synchronization recovery circuits in the TV receiver have a hard time recovering the sync. This is because the sync circuits are designed to look for the most negative portion of the video signal. As shown, in the case of inverted video, the peak white signal has now been moved to the amplitude of the sync, so the sync circuits will not be able to distinguish sync from peak white. In the event the sync circuits do successfully identify the sync information, the picture will appear as the negative of the real picture, because the light and dark levels have been reversed. Further, the colour information will be rendered incorrect because the phase of the colour subcarrier in reversed in the inversion process.

FIG. 3 illustrates inverted sync with noninverted video. In this case the picture information would appear correct if sync recovery was possible, but since the sync has been inverted, the sync circuits will not be able to identify the sync, rendering the picture garbled.

FIG. 4 combines the above inversion methods by inverting both the sync and the video.

A desirable method of video scrambling would be to allow changing from one of these modes to another either randomly or based upon some predetermined condition such as average picture level. These modes have been used singly or in combination in scrambling systems employed during the last few years.

Past systems have suffered from at least two problems which create artifacts in the recovered signal. If sync is inverted, the automatic gain control (AGC) circuits of the demodulator, employed to recover the signal before descrambling, will be able to recover a good gain reference for AGC. This is so because the inverted sync pulse is normally transmitted as the highest amplitude of the modulated signal, which the AGC circuits look for in order to normalize the amplitude of the received signal. But when the sync pulse is inverted, the peak value of the modulated signal corresponds to the peak white level in the scene. Since the peak white level is a function of the picture, it does not form a satisfactory reference. One possible solution to this problem would be to detect minimum value of the carrier and use it as a reference as is done in the SECAM television system employed in France and other countries. However, since the same demodulator circuit is called upon to handle both scrambled and nonscrambled (inverted and noninverted), it would therefore be necessary to provide two AGC detectors for recovering scrambled and nonscrambled signals, one for detecting inverted and one for detecting non-inverted signals. This would significantly add to cost of the circuit. Moreover, the difficulty of matching the performance of two difference AGC detectors is formidable.

A second important deficiency of past systems arises due to the "calculation" of the axis of inversion, shown generally as 108 in FIG. 1. This axis is the voltage level about which a portion of the signal to be converted is rotated. One can imagine that the signal is "anchored" to the axis of rotation and flips about it so that its negative peak becomes its positive peak and vice versa. In order to effect proper descrambling, the axis of inversion in the scrambler and descrambler must be identical since if the signal or a portion thereof is inverted about an axis in the scrambler, it must be reinverted about the same axis in the descrambler to accurately produce the correct picture signal information. Should the descrambler have a different axis of inversion than the scrambler, the recovered signal will be shifted with respect to the transmitted signal. This results in either stretched or compressed video signals and/or sync pulses. In either case the brightness levels of the recovered video will be altered, leaving an undesirable artifact in the picture. This artifact is especially troublesome if the method of video inversion is changed frequently.

Past systems have relied on factory calibration to maintain the integrity of the axis of inversion in a system. This scheme is unsatisfactory. For example, some systems may measure the level of the sync signal, and "count off" the distance to the axis of inversion.

A particularly convenient axis of inversion is +30 IRE, half way between the sync tip -40 IRE and peak white (+100IRE). If the normal amplitude of the recovered signal at the descrambler is 1 volt, then the voltage difference between the sync and the axis is (70/140)x(1 volt) = 0.5 volt But suppose that the depth of modulation at the modulator is changed such that the recovered signal is not 1 volt, but is 0.9 volts instead. The descrambler has no knowledge of this change, so it will assume that the axis to be 0.5 volt from the sync tip. However, the axis is really (70/140)x(0.9 volt) = 0.45 volt from the sync tip. The descrambler places the axis in error by 0.05 volt, which can be shown equivalent to an error of 7.78 IRE. When the axis of inversion is in error it can be shown that the error in the resultant video is twice the error in the axis, or 15.56 IRE.

A further deficiency of past systems is manifested in the headen of the CATV system, where the signal is scrambled. The modulator, which must impress the scrambled signal on a RF carrier, includes a sync tip clamping circuit used to normalize the peak envelope of the modulated signal to a desired level. Reference to FIG. 3 or 4 shows that in these scrambling modes, the sync does not occur at the expected peak negative of the video signal, rendering the clamp useless. The systems have required that a modified modulator be used to retain the clamp function. The modification is expensive.

U.S. Patent No. 4,924,498 issued to James O.

Farmer et al. on May 8, 1990 discloses a method and apparatus for improving video scrambling and employing split sync pulses.

A patent of James O. Farmer et al. improves the quality of the recovered video compared with other video inversion systems by rendering the video less sensitive to variations in the modulation depth of the modulator carrying the inverted signal, the demodulation sensitivity of the demodulator and the stability of the recovery circuits. The patent of James O. Farmer et al.

further provides additional security against pirating by allowing the scrambling circuit to operate in diverse modes, each of which will cause a TV to react differently should a conventional device be employed.

The patent of James O. Farmer et al. also renders the signal capable of being transmitted with unmodified modulators of the type normally employed in the CATV industry. However, the patent of James O. Farmer et al.

has a different configuration from that of the present invention.

Summary of the Invention Therefore, it is a first object of the present invention, for the purpose of solving the above mentioned problems, to provide an apparatus for scrambling a video signal by superimposing a scrambling signal on a video signal to be scrambled in a pay television system.

It is a second object of the present invention to provide an apparatus for descrambling a scrambled video signal by using a descrambling signal.

In order to accomplish the first object, there is provided a scrambling apparatus, the apparatus comprising: horizontal and vertical sync separators for separating horizontal and vertical synchronizing signals from a video signal received to be scrambled, respectively; a counter circuit for counting the horizontal synchronizing signal in response to the vertical synchronizing signal from the vertical sync separator to generate a count signal when the count reaches a first predetermined value; a reference clock generator for generating a reference clock signal based on the horizontal synchronizing signal from the horizonal sync separator; a switch for selectively transferring either one of an unscrambled signal of the video signal or a scrambling pulse; and a control section for controlling the switch based on the horizontal synchronizing signal from the horizontal sync separator, the count signal from the counter circuit, and the reference clock signal from the reference clock generator.

In order to accomplish the second object, there is provided a descrambling apparatus, said apparatus comprising: a sync separator for separating a synchronizing signal and a scrambling pulse from a scrambled video signal to be descrambled received; a multivibrator for receiving the synchronizing signal and the scrambling pulse from the sync separator, removing the scrambling pulse, and outputting the synchronizing signal; horizontal and vertical sync separators for separating horizontal and vertical synchronizing signals from the synchronizing signal from the multivibrator, respectively; a counter circuit for counting the horizontal synchronizing signal in response to the vertical synchronizing signal from the vertical sync separator to generate a count signal when the count reaches a first predetermined value; a reference clock generator for generating a reference clock signal based on the horizontal synchronizing signal from the horizonal sync separator; a switch for selectively transferring either one of an unscrambled signal of the scrambled video signal or a descrambling signal; and a control section for controlling the switch based on the horizontal synchronizing signal from the horizontal sync separator, the count signal from the counter circuit, and the reference clock signal from the reference clock generator.

In accordance with the present invention, the scrambling and descrambling operations can be performed by superimposing a scrambling pulse to a front porch portion of a video signal to be scrambled.

Other objects and further features of the present invention will become apparent from the detailed description when read in conjunction with the attached drawings.

Brief Description of the Drawings The above objects and advantages of the present invention will become more apparent by describing in detail a preferred embodiment thereof with reference to the attached drawings in which: FIG. 1 is a schematic view for showing a video signal; FIGs. 2 to 4 are schematic views for showing various forms of scrambled signals; FIG. 5 is a view for showing a video signal scrambled by a method according to the present invention; FIG. 6 is a block diagram for showing a configuration of a scrambling apparatus according to an embodiment of the present invention; FIG. 7 is a timing diagram for illustrating an operation of the scrambling apparatus shown in FIG. 6; FIG. 8 is a detailed circuitry diagram for showing an example of the control section shown in FIG. 6; FIG. 9 is a timing diagram for explaining an operation of the control section shown in FIGs 6 and 8; FIG. 10 is a timing diagram for explaining operations of the control section and the switch shown in FIGs. 6 and 8; FIG. 11 is a block diagram for showing a configuration of a descrambling apparatus according to an embodiment of the present invention; FIG. 12 is a timing diagram for illustrating an operation of the descrambling apparatus shown in FIG.

11; FIG. 13 is a detailed circuitry diagram for showing an example of the control section shown in FIG.

11; FIG. 14 is a timing diagram for explaining an operation of the control section shown in FIGs 11 and 13; and FIG. 15 is a timing diagram for explaining operations of the control section and the switch shown in FIGs 11 and 13.

Description of the Preferred Embodiment A preferred embodiment of the present invention is described hereunder with reference to the drawings.

FIG. 5 shows a scrambled video signal SV by adding a scrambling pulse signal to the front porch interval of the video signal. An H.sync is a horizontal synchronizing signal, a CB is a colour burst signal, an AV is an active video signal, and an SP is a scrambling pulse signal. The time from the end of the horizontal synchronizing signal H.sync to the beginning of active video is called the back porch BP. The end of the active video signal defines the front porch FP. The entire interval from the beginning of the front porch FP to the end of the back porch BP is collectively known as the horizontal blanking interval HBI.

FIG. 6 shows a configuration of a scrambling apparatus 60 according to an embodiment of the present invention. The scrambling apparatus 60 includes a sync separator 602, a horizontal sync separator 604, a vertical sync separator 606, a counter circuit 608, a reference clock generator 610, a switch 612, and a control section 614. A reference numeral 600 is an input terminal for receiving the video signal to be scrambled.

The sync separator 602 receives a video signal CV through the input terminal 600 and separates a synchronizing signal SYNC from the received video signal CV. The synchronizing signal SYNC is applied to the horizontal sync separator 604 and the vertical synchronizing sync separator 606.

The horizontal sync separator 606 is connected to an output terminal of the sync separator 604 and separates a horizontal synchronizing signal H.sync from the synchronizing signal SYNC from the sync separator 602. The horizontal synchronizing signal H.sync is applied to the counter circuit 608, the reference clock generator 610, and the control section 614.

The vertical sync separator 608 is connected to the output terminal of the sync separator 602 and separates a vertical synchronizing signal V.sync from the synchronizing signal SYNC from the sync separator 602. The vertical synchronizing signal V.sync is applied to the counter circuit 608.

The counter circuit 608 is connected to output terminals of the horizontal and vertical sync separators 604 and 606 and counts the horizontal synchronizing signal H.sync in response to the vertical synchronizing signal V. sync from the vertical sync separator 606 to generate a count signal CS when the count reaches a first predetermined value. In an embodiment of the present invention, the first predetermined value is fifteen. The count signal CS is applied to the control section 614.

The reference clock generator 610 is connected to the output terminal of the horizontal sync separator 606 and generates a reference clock signal RC based on the horizontal synchronizing signal H.sync from the horizonal sync separator 606. The reference clock signal RS is applied to the control section 614.

The switch 612 includes a first input terminal for receiving the video signal, a second input terminal for a ground signal from the ground potential supply, and an output terminal for outputting a selected one signal from the video signal or the ground signal.

The switch (S/W) 612 selectively transfers either one of the video signal received through the input terminal 600 or a ground signal GS from the ground potential supply as a scrambling signal to the modulator 618 according to the control signal SCR of the control section 614. That is, a low level control signal is applied to the switch 606, and the switch 612 transfers the composite video signal to the modulator 618, while a high level control signal is applied to the switch transfers the ground signal to the modulator 618.

The control section 614 is connected to the horizontal sync separator 604, the reference clock generator 610, and the counter circuit 608 and controls a switching operation of the switch 612 based on the horizontal synchronizing signal H.sync from the horizontal sync separator 604, the reference clock signal RC from the reference clock generator 610, and the count signal CS from the counter circuit 608.

FIG. 7 is a timing diagram for illustrating an operation of the scrambling apparatus shown in FIG. 6.

As shown in FIG. 7(A), CV represents a video signal to be scrambled transmitted to the scrambling apparatus via a satellite and is applied to the sync separator 602 and the switch 612. As shown in FIG. 7(B), SYNC represents a synchronizing signal and is applied to horizontal and vertical sync separators 604 and 606. As shown in FIG. 7(C), V.sync represents a vertical synchronizing signal and is applied to the counter circuit 608. As shown in FIG. 7(D), CS represents a count signal and is applied to the control section 614.

As shown in FIG. 7(E), H.sync represents a horizontal synchronizing signal and is applied to the counter circuit 608, the reference clock generator 610, and the control section 614.

FIG. 8 shows a detailed circuitry diagram for showing an example of the control section as shown in FIG. 6. The control section 614 includes a first down counter 802, a second down counter 804, an inverter 806, and an AND gate 806.

The first down counter 802 is connected to the horizontal sync separator 604 and the reference clock generator 610 and counts a total number of the reference clocks corresponding to a first time interval T1 of FIG. 9 and generates a first detection signal FD when the count thereof reaches a second predetermined value. Preferably, in an embodiment of the present invention, the second predetermined value is zero. The first detection signal FD is applied to the first input terminal of the AND gate 808.

The second down counter 804 is connected to the horizontal sync separator 604 and the reference clock generator 610 and counts a total number of the reference clocks corresponding to a second time interval T2 of FIG. 9 and generates a second detection signal SD when the count thereof reaches a third predetermined value. Preferably, in an embodiment of the present invention, the third predetermined value is zero. The second detection signal SD is applied to an input terminal of the inverter 806.

An inverter 806 is connected to an output terminal of the second down counter 804 and inverts the second detection signal SD from the second down counter 704 to generate an inverted signal IS. The inverted signal IS applied to a second input terminal of the AND gate 808.

The AND gate 808 includes a first input terminal for receiving the first detection signal FD from the first down counter 802, a second input terminal for receiving the inverted signal IS from the inverter 806, a third input terminal for receiving the count signal CS from the counter circuit 608 of FIG. 6, and an output terminal for outputting the control signal SCR to the switch 512 of FIG. 6. The AND gate 808 receives the first detection signal FD from the first down counter 802 and the inverted signal IS from the inverter 806, and the count signal CS from counter circuit 608 and outputs the control signal SCR to switch 612.

FIG. 9 shows a timing diagram for explaining an operation of the control section shown in FIGs 6 and 8.

FIG. 9(A) shows an unscrambled video signal CV. FIG.

9(B) shows a scrambled video signal SC. FIG. 9(C) shows the horizontal synchronizing signal H.sync from the horizontal sync separator 604 of FIG. 6. FIG. 9(D) shows the reference clock signal RC from the reference clock generator 610 of FIG. 6. FIG. 9(E) shows the first detection signal FD from the first down counter 802 of FIG. 8. FIG. 9(F) shows the second detection signal SD from the second down counter 806 of FIG. 8.

FIG. 9(G) shows the inverted signal IS from the inverter 806. FIG. 9(H) shows the control signal CS from the AND gate 808.

A first time interval T1 represents a time from the end of the horizontal synchronizing signal H.sync to a beginning of the scrambling portion FP2 of the front porch FP. A second time interval T2 represents a time from the end of the horizontal synchronizing signal H.sync to the end of the scrambling portion FP2 of the front porch FP.

FIG. 10 shows a waveform for illustrating the switch and the control section shown in FIGs. 6 and 8.

FIG. 10(A) shows a scrambled video signal SC according to the present invention. The front porch FP includes a first unscrambling portion FP1, a scrambling portion FP2, and a second unscrambling portion FP3. A first unscrambling portion FP1 of the front porch FP is transmitted at a pedestal level for a first time duration of Till. The scrambling portion FP2 of the front porch FP is transmitted at a ground level for a second time duration of T12. A second unscrambling portion FP2 is transmitted for a third time duration of T13 at a pedestal level. In this embodiment, the first, second, and third time durations are different from the time duration of the other two or some may be equal to each other. The first, second, and third time durations are 0.4, 0.5, and 0.4 usec, respectively. The scrambling pulse signal SP is superimposed on front porch intervals of a plurality of horizontal sync scanning line and character data is added to an eighteen horizontal scanning line 18H to a twenty first 21H. Therefore, Preferably, in an embodiment of the present invention, the scrambling pulse signal SP is superimposed on front porch intervals of after a fourteenth horizontal scanning line, that is, a fifteen horizontal scanning line 15H to 525-th horizontal scanning line 525H every frame.

FIG. 10(B) shows the control signal CS generated by means of the control section 614. FIG. 10(C) explains a switching operation of the switch 612.

As shown in FIG. 10(B), until a time tl when the control signal SCR is in a low logic state, the switch 612 is in a first position P1 and is connected to the input terminal 600.

At time tl, when the control signal SCR changes from a low logic state to a high logic state, as shown in FIG. 10(C), the switch 612 is switched from the first position P1 to a second position P2 and is connected to ground potential supply Vss. Accordingly, the scrambling pulse SP is transmitted to the modulator through the switch 612. The switch 612 remains in the second position P2 until the end of the scrambling portion FP2 of the front porch FP, that is, until the time t2. At time t2, when the control signal SCR changes from the high logic signal to the low logic state, the switch 612 is returned to the first position P1 and is again connected to the input terminal 600.

The switch (S/W) 612 remains in the first position P1 until a beginning of a next scrambling portion FP22, that is, until time t3.

FIG. 11 shows a configuration of a descrambling apparatus 11 according to an embodiment of the present invention. The descrambling apparatus 11 includes a sync separator 1102, a multivibrator 1103, a horizontal sync separator 1104, a vertical sync separator 1106, a counter circuit 1108, a reference clock generator 1110, a switch 1112, and a control section 1114. A reference numeral 1100 is an input terminal for receiving the scrambled video signal to be scrambled.

The sync separator 1102 receives a scrambled video signal SC through the input terminal 1100 and separates a synchronizing signal SYNC and a scrambling pulse signal SP from the received scrambled video signal SC.

The synchronizing signal SYNC and the scrambling pulse signal SP are applied to the multivibrator 1103.

The multivibrator 1103 is connected to an output terminal of the sync separator 1102. The multivibrator 1103 receives the synchronizing signal SYNC and the scrambling pulse signal SP from the sync separator 1102, removes the scrambling pulse signal SP, and outputs the synchronizing signal SYNC.

The synchronizing signal SYNC is applied to the horizontal sync separator 1104 and the vertical synchronizing sync separator 1106.

The horizontal sync separator 1104 is connected to an output terminal of the multivibrator 1103 and separates a horizontal synchronizing signal H.sync from the synchronizing signal SYNC from the multivibrator 1103. The horizontal synchronizing signal H.sync is applied to the counter circuit 1108, the reference clock generator 1110, and the control section 1114.

The vertical sync separator 1108 is connected to the output terminal of the multivibrator 1103 and separates a vertical synchronizing signal V.sync from the synchronizing signal SYNC from the multivibrator 1103. The vertical synchronizing signal V. sync is applied to the counter circuit 1108.

The counter circuit 1108 is connected to output terminals of the horizontal and vertical sync separators 1104 and 1106 and counts the horizontal synchronizing signal H.sync in response to the vertical synchronizing signal V.sync from the vertical sync separator 1106 to generate a count signal CS when the count reaches a first predetermined value. In an embodiment of the presen predetermined value is fifteen. The count signal CS is applied to the control section 1114.

The reference clock generator 1110 is connected to the output terminal of the horizontal sync separator 1106 and generates a reference clock signal RC based on the horizontal synchronizing signal H.sync from the horizonal sync separator 1106. The reference clock signal RS is applied to the control section 1114.

The switch 1112 includes a first input terminal for receiving the scrambled video signal SC, a second input terminal for receiving a power source potential signal from the power source potential supply Vcc as descrambling signal DP, and an output terminal for outputting selected one signal from the unscrambling signal of the scrambled video signal and the descrambling signal DP.

The switch (S/W) 1112 selectively transfers either one of the unscrambled signal US of the scrambled video signal received through the input terminal 1100 or the power source potential signal from the power source potential supply Vcc as a descrambling signal DP according to the control signal DCR of the control section 1114. That is, a low level control sinal is applied to the switch 1106, the switch 1112 outputs the unscrambled signal US, while a high level control signal is applied to the switch 1112 the switch 1106 transfers the descrambling signal DP.

The control section 1114 is connected to the horizontal sync separator 1104, the reference clock generator 1110, and the counter circuit 1108 and controls a switching operation of the switch 1112 based on the horizontal synchronizing signal H.sync from the horizontal sync separator 1104, the reference clock signal RC from the reference clock generator 1110, and the count signal CS from the counter circuit 1108.

FIG. 12 is a timing diagram for illustrating an operation of the descrambling apparatus shown in FIG.

11. As shown in FIG. 12(A), SC represents a scrambled video signal to be from the scrambling apparatus and is applied to the sync separator 1102 and the switch 1112.

FIG. 12(B) shows a vertical synchronizing signal V.sync, a horizontal synchronizing signal H.sync, and a scrambling pulse signal SP. The vertical synchronizing signal V.sync, the horizontal synchronizing signal H.sync, and the scrambling pulse signal SP are applied to the multivibrator 1103. As shown in FIG. 12(C), V.sync represents a vertical synchronizing signal and is applied to the counter circuit 1108. As shown in FIG. 11(D), CS represents a count signal of counter circuit 1108 and is applied to the control section 1114. As shown in FIG. 11(E), H.sync represents a horizontal synchronizing signal from the horizontal sync separator 1104 and is applied to the counter circuit 1108, the reference clock generator 1110, and the control section 1114.

FIG. 13 shows a detailed circuitry diagram for showing an example of the control section as shown in FIG. 11. The control section 1114 includes a first down counter 1302, a second down counter 1304, an inverter 1306, and an AND gate 1308.

The first down counter 1302 is connected to the horizontal sync separator 1104 and the reference clock generator 1110 and counts a total number of the reference clocks corresponding to a first time interval T1 of FIG. 14 and generates a first detection signal FD when the count thereof reaches a second predetermined value. Preferably, in an embodiment of the present invention, the second predetermined value is zero. The first detection signal FD is applied to the first input terminal of the AND gate 1308.

The second down counter 1304 is connected to the horizontal sync separator 1104 and the reference clock generator 1110 and counts a total number of the reference clocks corresponding to a second time interval T2 of FIG. 14 and generates a second detection signal SD when the count thereof reaches a third predetermined value. Preferably, in an embodiment of the present invention, the third predetermined value is zero. The second detection signal SD is applied to an input terminal of the inverter 1306.

An inverter 1306 is connected to an output terminal of the second down counter 1304 and inverts the second detection signal SD from the second down counter 1304 to generate an inverted signal IS. The inverted signal is applied to a second input terminal of the AND gate 1308.

The AND gate 1308 includes a first input terminal for receiving the first detection signal FD from the first down counter 1302, a second input terminal for receiving the inverted signal IS from the inverter 1306, a third input terminal for receiving the count signal CS from the counter circuit 1108 of FIG. 11, and an output terminal for outputting the control signal DCR to the switch 1112 of FIG. 11. The AND gate 1308 receives the first detection signal FD from the first down counter 1302 and the inverted signal IS from the inverter 1306, and the count signal CS from the counter circuit 1308 and outputs the control signal DCR to switch 1112.

FIG. 14 shows a timing diagram for explaining an operation of the control section shown in FIGs 11 and 13. FIG. 14(A) shows a scrambled video signal SC to be descrambled according to the present invention. FIG.

14(B) shows a scrambled video signal SC. FIG. 14(C) shows the horizontal synchronizing signal H.sync from the horizontal sync separator 1104 of FIG. 11. FIG.

14(D) shows the reference clock signal RC from the reference clock generator 1110 of FIG. 11. FIG. 14(E) shows the first detection signal FD from the first down counter 1102 of FIG. 11. FIG. 14(F) shows the second detection signal SD from the second down counter 1106 of FIG. 11. FIG. 14(G) shows the inverted signal IS from the inverter 1106. FIG. 14(H) shows the control signal CS from the AND gate 1108 of the control section 1114. A first time interval T1 represents a time from the end of the horizontal synchronizing signal H.sync to a beginning of the scrambling portion FP2 of the front porch FP. A second time interval T2 represents a time from the end of the horizontal synchronizing signal H.sync to the end of the scrambling portion FP2 of the front porch FP.

FIG. 15 shows a waveform for illustrating the switch and the control section shown in FIGs. 11 and 13.

FIG. 15(A) shows a scrambled video signal SC to be descrambled. DP designates a descrambling signal. The front porch FP includes a first unscrambling portion FP1, a descrambling portion DP1, and a second unscrambling portion FP3. A first unscrambling portion FP1 of the front porch FP is transmitted at a pedestal level for a first time duration of T11. The descrambling portion DP1 of the front porch FP is transmitted at a pedestal level for a second time duration of T12. A second unscrambling portion is transmitted for a third time duration of T13 at a pedestal level. In this embodiment, the first, second, and third time durations are different from the time duration of the other two or some may be equal to each other. The first, second, and third time durations are 0.4, 0.5, and 0.4 usec, respectively.

Since the scrambling pulse signal SP is superimposed on the front porch after a fourteenth horizontal scanning line, that is, a fifteen horizontal scanning line 15H to 525-th horizontal scanning line 525H every frame.

The descrambling signal DP is added to the front porch interval a fifteen horizontal scanning line 15H to 525th horizontal scanning line 525H every frame.

FIG. 15(B) shows the control signal CS generated by means of the control section 614. FIG. 15(C) explains a switching operation of the switch 1112.

As shown in FIG. 15(B), until a time tl when the control signal DCR is in a low logic state, the switch 1112 is in a first position P1 and is connected to the input terminal 1100.

At time tl, when the control signal DCR changes from a low logic state to a high logic state, as shown in FIG. 15(C), the switch 1112 is switched from the first position P1 to a second position P2 and is connected to ground potential supply Vss. Accordingly, the descrambling pulse DP is transmitted to through the switch 1112. The switch 1112 remains in the second position P2 until the end of the descrambling portion DP1 of the front porch FP, that is, until the time t2.

At time t2, when the control signal DCR changes from the high logic signal to the low logic state, the switch 1112 is returned to the first position P1 and is again connected to the input terminal 600. The switch 1112 remains in the first position P1 until a beginning of a next descrambling portion DP22, that is, until time t3.

As mentioned above, in accordance with the present invention, the scrambling and descrambling operations can be performed by superimposing a scrambling pulse to a front porch portion of a video signal to be scrambled.

The invention may be embodied in other specific forms without departing from the spirit or essential characteristics thereof. The present embodiments are therefore to be considered in all respects as illustrative and not restrictive, the scope of the invention being indicated by the appended claims rather than by the foregoing description and all changes which come within the meaning and range of equivalency of the claims are therefore intended to be embraced therein.

Claims (20)

1. A scrambling apparatus, said apparatus comprising: horizontal and vertical sync separators for separating horizontal and vertical synchronizing signals from a video signal received to be scrambled, respectively; a counter circuit for counting the horizontal synchronizing signal in response to the vertical synchronizing signal from the vertical sync separator to generate a count signal when the count reaches a first predetermined value; a reference clock generator for generating a reference clock signal based on the horizontal synchronizing signal from the horizonal sync separator; a switch for selectively transferring either one of an unscrambled signal of the video signal or a scrambling pulse; and a control section for controlling the switch based on the horizontal synchronizing signal from the horizontal sync separator, the count signal from the counter circuit, and the reference clock signal from the reference clock generator.

2. The scrambling apparatus according to claim 1, wherein the first predetermined value is fifteen.

3. The scrambling apparatus according to claim 1, a voltage level of the scrambling pulse is equal a voltage level of the horizontal synchronizing signal.

4. The scrambling apparatus according to claim 1, the scrambling signal is superimposed on a front porch interval of the video signal during a plurality of horizontal scanning lines.

5. The scrambling apparatus according to claim 4, the scrambling signal is superimposed on a front porch interval of the video signal from a fifteen horizontal scanning line to 525-th horizontal scanning line.

6. The scrambling apparatus according to claim 1, wherein the control section generates a control signal for controlling the switch, and when the control signal is in a high logic state the switch outputs the unscrambled signal, and when the control signal is in a low logic state the switch outputs the scrambling pulse.

7. The scrambling apparatus according to claim 1, wherein the control section includes a first down counter for counting a total number of reference clocks corresponding to a first time interval which defined a time from an end of the horizontal synchronizing signal to a beginning of the scrambling portion of a front porch of the video signal to generate a first detection signal when the count reaches a second predetermined value; a second down counter for counting a total number of reference clocks corresponding to a second time interval which defines a time from the end of the horizontal synchronizing signal to an end of the scrambling portion of a front porch of the video signal to generates a second detection signal when the count reaches a third predetermined value; an inverter for inverting the second detection signal from the down second counter to generate an inverted signal a logic gate for logically operating the first detection signal from the first down counter, the inverted signal from the inverter, and the count signal from the counter circuit to output a control signal in order to the switch.

8. The scrambling apparatus according to claim 7, wherein the second predetermined value is equal to the third predetermined value.

9. The scrambling apparatus according to claim 8, wherein the second predetermined value and the third predetermined value are zero.

10. The scrambling apparatus according to claim 7, wherein the logic gate includes an AND gate for ANDing the first detection signal from the first down counter, the inverted signal from the inverter, and the count signal from the counter circuit to output a control signal in order to the switch.

11. A descrambling apparatus, said apparatus comprising: a sync separator for separating a synchronizing signal and a scrambling pulse from a scrambled video signal to be descrambled received; a multivibrator for receiving the synchronizing signal and the scrambling pulse from the sync separator, removing the scrambling pulse, and outputting the synchronizing signal; horizontal and vertical sync separators for separating horizontal and vertical synchronizing signals from the synchronizing signal from the multivibrator, respectively; a counter circuit for counting the horizontal synchronizing signal in response to the vertical synchronizing signal from the vertical sync separator to generate a count signal when the count reaches a first predetermined value; a reference clock generator for generating a reference clock signal based on the horizontal synchronizing signal from the horizonal sync separator; a switch for selectively transferring either one of an unscrambled signal of the scrambled video signal or a descrambling signal; and a control section for controlling the switch based on the horizontal synchronizing signal from the horizontal sync separator, the count signal from the counter circuit, and the reference clock signal from the reference clock generator.

12. The descrambling apparatus according to claim 11, wherein the first predetermined value is fifteen.

13. The descrambling apparatus according to claim 11, a voltage level of the descrambling pulse is equal a voltage level of a front porch of the video signal.

14. The scrambling apparatus according to claim 11, the descrambling signal is superimposed on a front porch interval of the video signal during a plurality of horizontal scanning lines.

15. The scrambling apparatus according to claim 14, the descrambling signal is superimposed on a front porch interval of the video signal from a fifteen horizontal scanning line to 525-th horizontal scanning line.

16. The descrambling apparatus according to claim 11, wherein the control section generates a control signal for controlling the switch, and when the control signal is in a high logic state the switch outputs the unscrambled signal, and when the control signal is in a low logic state the switch outputs the descrambling signal.

17. The descrambling apparatus according to claim 11, wherein the control section includes a first down counter for counting a total number of reference clocks corresponding to a first time interval which defined a time from an end of the horizontal synchronizing signal to a beginning of the scrambling portion of a front porch of the video signal to generate a first detection signal when the count reaches a second predetermined value; a second down counter for counting a total number of reference clocks corresponding to a second time interval which defines a time from the end of the horizontal synchronizing signal to an end of the scrambling portion of a front porch of the video signal to generates a second detection signal when the count reaches a third predetermined value; an inverter for inverting the second detection signal from the down second counter to generate an inverted signal a logic gate for logically operating the first detection signal from the first down counter, the inverted signal from the inverter, and the count signal from the counter circuit to output a control signal in order to the switch.

18. The descrambling apparatus according to claim 17, wherein the second predetermined value is equal to the third predetermined value.

19. The descrambling apparatus according to claim 18, wherein the second predetermined value and the third predetermined value are zero.

20. The descrambling apparatus according to claim 13, wherein the logic gate includes an AND gate for ANDing the first detection signal from the first down counter, the inverted signal from the inverter, and the count signal from the counter circuit to output a control signal in order to the switch.