GB2312361A - Symbol synchronisation method and apparatus - Google Patents
Symbol synchronisation method and apparatus Download PDFInfo
- Publication number
- GB2312361A GB2312361A GB9707835A GB9707835A GB2312361A GB 2312361 A GB2312361 A GB 2312361A GB 9707835 A GB9707835 A GB 9707835A GB 9707835 A GB9707835 A GB 9707835A GB 2312361 A GB2312361 A GB 2312361A
- Authority
- GB
- United Kingdom
- Prior art keywords
- data
- symbol
- frame
- timing
- error
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Classifications
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L7/00—Arrangements for synchronising receiver with transmitter
- H04L7/04—Speed or phase control by synchronisation signals
- H04L7/048—Speed or phase control by synchronisation signals using the properties of error detecting or error correcting codes, e.g. parity as synchronisation signal
Landscapes
- Engineering & Computer Science (AREA)
- Computer Networks & Wireless Communication (AREA)
- Signal Processing (AREA)
- Synchronisation In Digital Transmission Systems (AREA)
- Detection And Prevention Of Errors In Transmission (AREA)
- Time-Division Multiplex Systems (AREA)
Abstract
In a symbol synchronization apparatus, the period of time required to restore the symbol synchronization lost is minimized. The apparatus includes a receiver for receiving transmission data sent from a transmitter with an error detection code added to each data frame thereof. The receiver includes an error detector for detecting an error in the data frame of the transmission data and producing an error detection signal and a symbol synchronizing unit for receiving the transmission data according to the error detection result, establishing symbol synchronization for the transmission data, and following up the symbol synchronization. When the data frame is free of errors, the symbol synchronizing unit holds sample timing of a last symbol of the data frame and sets the sample timing as an initial value of sample timing of a first symbol of the subsequent data frame. When any error is found in the data frame, the symbol synchronizing unit sets sample timing beforehand held as an initial value of sample timing of a first symbol of the subsequent data frame.
Description
SYMBOL SYNCHRONIZATION METHOD
AND APPARATUS USING THE SAME
BACKGROUND OF THE INVENTION
The present invention relates to a symbol synchronization follow-up method and an apparatus using the same in which a follow-up of symbol synchronization is conducted for transmission data including an error detection code for each data frame.
Description of the Prior Art
Conventionally, in the symbol synchronization followup method of this kind, each symbol of transmission data (particularly indicating reception data) is sampled at an appropriate point of timing. For example. in a delay or comparison detection, the symbol acquisition and followed up are conducted to sample the symbols at timing at which the eye becomes wider in the eye pattern. Additionally, when the reception data is burst data, the follow-up of symbol synchronization is accomplished with the precision of selfrunning clock signals increased for the prevention of stepout of symbol synchronization in a portion where data is interrupted.
As a technology associated with the symbol synchronization follow-up above, reference is to be made to.
for example, the contents described in the Japanese Patent
Laid-Open Ser. No. 4-2235.
Figs. 1A and 1B are diagrams for explaining the frame synchronization detecting method. Fig. 1A shows in a block diagram the fundamental constitution of the method, whereas
Fig. 1B is a signal timing chart related to operation of the method, namely, operation to detect frame synchronization.
In the synchronization detecting method, as can be seen from Fig. 1A, a cyclic redundancy check (CRC) data generator 101 is provided on the transmission side. Data resultant from CRC generation conducted by the CRC data generating section 101 is added to each frame such that transmission data including the CRC data is sent to the reception side. On receiving the transmission data, the reception data checks the CRC data for each frame length by a
CRC data check section 201.
In the operation, CRC-TIM for which the CRC data check is started is shifted one bit for each frame length as shown in Fig. 1B. When CRC-TIM matches CDT-TIM for which the
CRC data check is to be commenced, it is assumed that matching takes place for the CRC data check. Deciding the position as the first position of a frame, it is possible to establish frame synchronization.
Specifically, as another technology related to the present invention, there has been known a synchronization circuit described in the Japanese Patent Laid-Open Ser. No. 4211547. In the synchronization circuit, the CRC data examination is adopted for the frame synchronization, not for the symbol synchronization, which is the same as the system in the Japanese Patent Laid-Open Ser. No. 4-2235. The technology is similar to that described above in the use of the results of error detection such as CRC data check.
However, the processes subsequent thereto varies between these technologies.
in accordance with the synchronization detecting method described above, once the symbol synchronization is
lost due to influence from disturbing waves such as cochannel
interference, the process of establishing the symbol
synchronization is required to be conducted beginning at the
start point thereof, just like in the initial point of data reception. for the restoration of the symbol synchronization.
This takes a long period of time and hence leads to a
problem of increase in the chance of decoding errors of
transmission (reception) data during the operation to restore
symbol synchronization.
The invention aims generally to reduce the time required to establish symbol synchronisation or to alleviate problems in synchronisation caused by reception errors.
In a first method aspect, there is provided a method as set out in
Claim 1, and in a corresponding apparatus aspect, there is provided apparatus as set out in Claim 8.
Preferred features are set out in the dependent claims.
In a refinement of the first method aspect, there is
provided a symbol synchronization follow-up method including
the steps of detecting. on receiving by a reception side
transmission data sent from a transmission side with an error
detection code added to each data frame thereof, an error in
the data frame of the transmission data, and acquiring a
result of the error detection and receiving the transmission
data according to the error detection result, establishing
symbol synchronization for the transmission data, following up
the symbol synchronization, holding. when the data frame is
free of errors, sample timing of a last symbol of the data
frame and setting the sample timing as an initial value of
sample timing of a first symbol of the subsequent data frame.
and setting, when the data frame is associated with any error, sample timing beforehand held as an initial value of sample timing of a first symbol of the subsequent data frame.
On the other hand, in accordance with the present invention, there is provided a symbol synchronization followup apparatus including a transmitter including error detection code generator means for adding an error detection code to each data frame and sending transmission data including the data frame and a receiver for receiving the transmission data.
The receiver includes error detecting means for detecting an error in each data frame of the transmission data and producing an error detection signal and symbol synchronizing means for receiving the transmission data according to the error detection result, establishing symbol synchronization for the transmission data, following up the symbol synchronization. The symbol synchronizing means holds, when the data frame is free of errors, sample timing of a last symbol of the data frame and sets the sample timing as an initial value of sample timing of a first symbol of the subsequent data frame. The symbol synchronizing means sets, when the data frame is associated with any error, sample timing beforehand held as an initial value of sample timing of a first symbol of the subsequent data frame.
Additionally, in a symbol synchronization follow-up apparatus in accordance with the present invention, the symbol synchronizing means sends a timing signal indicating a point of timing of sampling the transmission data according to the transmission data in the symbol synchronization follow-up operation and the error detecting means samples the transmission data according to the timing signal and thereby producing the error detection signal.
BRIEF DESCRIPTION OF THE DRAWINGS
The objects and features of the present invention will become more apparent from the consideration of the following detailed description taken in conjunction with the accompanying drawings in which:
Fig. 1A is a block diagram showing the fundamental structure of the conventional method of detecting frame synchronization;
Fig. 1B is a signal timing chart of operation of the method of Fig. 1A;
Fig. 2 is a block diagram showing the basic construction of a first embodiment of the symbol synchronization follow-up device using the symbol synchronization follow-up method in accordance with the present invention; and
Fig. 3 is a signal timing chart showing waveforms of operation processing signals at respective blocks of the symbol synchronization follow-up device of Fig. 2.
DESCRIPTION OF THE PREFERRED EMBODIMENTS
Referring now to the drawing, description will be given of embodiments of a symbol synchronization follow-up method and an apparatus using the same in accordance with the present invention.
First, description will be given of an output of the symbol synchronization follow-up method in accordance with the present invention. This method executes an error detection stage and a stage of processing follow-up of symbol synchronization. The error detection state is operative, when the reception side receives transmission data to which an error detection code is added for each data frame by the transmission side, to check an error in each data frame of the transmission data and to acquire results of the error check. When such an error is missing in the data frame is free, the stage of processing follow-up of symbol synchronization holds sample timing of the last symbol of the data frame to set the sample timing as the initial value of sample timing for the first symbol of the subsequent data frame. On the other hand, when the data frame is associated with a data error, the sample timing held before is set as the initial value of sample timing for the first symbol of the subsequent data frame.
In a case in which the data frame is free of errors as a result of the error check in the error detection stage, the sample timing of each symbol can be regarded as appropriate in the data frame. In this situation, in the symbol follow-up stage, the sample timing of the last symbol of the data frame is held such that the sample timing is set as the initial value of sample timing for the first symbol of the subsequent data frame. However, when the data is related to a data error, the sample timing beforehand held is set as the initial value of sample timing for the first symbol of the subsequent data frame. This resultantly establishes symbol synchronization for the first symbol of each data frame. With this provision, even when the symbol synchronization is destroyed due to, for example, the cochannel interference, it is possible to restore the symbol synchronization at the beginning of the subsequent data frame.
Fig. 2 shows in a block diagram the fundamental structure of an embodiment of the symbol synchronization follow-up device utilizing the symbol synchronization followup described above.
The The symbol synchronization follow-up device includes a transmitter (transmission side) 1 including an error detection code generator 11 as error detection code generating means for adding an error detection code to each data frame and thereby transmitting transmission data a and a receiver (reception side) 2 for receiving the transmission data a. The receiver 2 includes an error detector circuit 22 and a symbol synchronization circuit 21. The error detector circuit 22 is disposed as error detecting means for detecting errors in the transmission data a for each data frame and producing an error detection signal d. The symbol synchronization circuit 21 is used as symbol synchronizing means for receiving the transmission data a according to the error detection signal d and establishing and following up symbol synchronization. Moreover, when errors are not found in the data frame, the circuit 21 holds sample timing of the last symbol of the data frame to set thereafter the sample timing as the initial value of sample timing for the first symbol of the next data frame. When any error is found in the data frame, the circuit 21 sets sample timing beforehand held as the initial value of sample timing for the first symbol of the next data frame.
More concretely, on transmitting information data e sent from an external device, the error detection code generator 11 of transmitter 1 adds an error detection code for each data frame to create transmission data a including the code and then transmits the transmission data to the receiver 2.
At reception of the transmission data a, the error detector 22 of the receiver 2 samples the transmission data a according to a timing signal supplied from the symbol synchronizer circuit 21 to thereby detect any error in the data frame and then outputs to the symbol synchronizer 21 the error detection signal d indicating presence or absence of errors. Additionally, the error detector 22 processes the received transmission data a including the information data e to resultantly produce reception information data f.
The symbol synchronizer 21 accomplishes the symbol synchronization follow-up using two methods. In the first method, the circuit 21 processes the transmission data a to establish symbol synchronization and thereafter carries out the follow-up operation. In the second method, when the error detection signal d from the error detector 22 indicates absence of errors in the data frame, the symbol synchronizer 21 holds sample timing of the last symbol of the data frame.
When the signal d indicates presence of errors in the data frame, the synchronizer 21 continuously holds sample timing previously obtained. Thereafter, at timing of the first symbol of the subsequent data frame, the synchronizer 21 sets the sample timing as the initial value of sample timing for the subsequent operation to thereby follow up the symbol synchronization. Conducting the follow-up operation of the symbol synchronization, the symbol synchronizing circuit 21 sends to the error detector circuit 22 a timing signal b indicating a sampling point of timing of the transmission data a.
Fig. 3 shows in a signal timing chart showing waveforms of operating signals in respective blocks of the symbol synchronization follow-up device. In the graph, the abscissa represents time t and each signal operates on the axis of time t. Furthermore, the transmission data a is assumed to be burst data of which each frame includes n symbols,
The symbol synchronizer 21 receives the transmission data a, establishes symbol synchronization, and produces a timing signal b of which a fallin-g edge is used as sample timing of transmission data a. When a particular data frame is decoded without any data error, it can be considered that the symbol synchronization is appropriate for the data frame.
Namely, the sample timing is appropriate for each symbol of the data frame. When the results of error detection indicate absence of errors, the synchronizer 21 holds sample timing of the last symbol of the data frame decoded without any error.
On the other hand, when an error is detected, sample timing beforehand held is kept retained to set as the initial value of sample timing for the first symbol of the subsequent data frame, thereby efficiently following up the symbol synchronization.
In conjunction with the relationship between the signals shown in Fig. 1B. when frame 1 of transmission data a is decoded without any error, the error detector 22 set the error detection signal d to a high level relative to level 0.
Receiving the signal d, the symbol synchronizer 21 holds sample timing of the last symbol of frame 1 at a rising edge of the detection signal d.
The sample timing of the last symbol of frame 1 is at a position of phase X 1. Consequently, when there is held phase information of a timing signal b which falls in phases 1 for symbols, the sample timing can be held. In the graph, the hold phase c is changed from phase X O held up to the point to phase 0 1 at the rising edge of error detection signal d.
To match sample timing of the first symbol of frame 2 with that of the last symbol of frame 1 the phase of timing signal b is adjusted according to phase 1. After the second symbol of the data frame, the symbol synchronization is followed up by processing the transmission data a. Like in the case of frame 2, when there exists an interference wave D greater than the transmission data a, an error appears in the results from the decoding of data a and there is increased the chance in which the symbol synchronization is adversely influenced by the disturbing wave.
When an error is detected in frame 2, the error detector set the error detection signal d to a low level relative to level 0. The symbol synchronizer 21 does not hold sample timing (phase 0 2) of the last symbol of frame 2 but keeps the sample timing (phase f1) held up to this point.
In this case, to match sample timing of the first symbol of frame 3 with the sample timing of the last symbol of frame 1 the phase of timing signal b is adjusted according to phases 1.
For the second and subsequent symbols, the transmission data a is processed to follow up the symbol synchronization. When the error is missing in frame 3, sample timing of the last symbol is held at the rising edge of the error detection signal d and then the phase c is changed from phase 01 to phase3.
According to the follow-up of synchronization above, when it is found as a result of error detection that the data frame is free of errors, the sample timing of the last symbol is held. When the data frame is associated with an error, the sample timing held before is kept held. The obtained sample timing is thereafter set as the initial value of sample timing of the first symbol of the next data frame. Consequently, even when the symbol synchronization is lost, it is possible to restore the state in which the symbol synchronization is established in the first symbol of the subsequent data frame.
Resultantly, there can be implemented a symbol synchronization follow-up method in which the chance of errors in the symbol synchronization follow-up can be reduced and which is resistive against disturbing waves such as the cochannel interference.
In accordance with the present invention described above when receiving transmission data in which an error detection code is added to each data frame. the symbol synchronization is followed up by processing the received data. Moreover, sample timing of the last symbol of the data frame which is decoded without error through the error detection is held to be set as the initial value of sample timing of the first symbol of the next data frame. When an error occurs in the decoding operation, the sample timing held up to the point is kept retained to be set as the initial value of sample timing of the first symbol of the data frame. Even when the symbol synchronization is destroyed due to the cochannel interference or the like, it-is possible to recover the state in which the symbol synchronization is established at the beginning of the subsequent data frame.
In consequence, the period of time required to restore the symbol synchronization is minimized and the change of decoding errors for the transmission (reception) data can be lowered.
That is, in accordance with the present invention, in addition to the conventional symbol synchronization and follow-up operation in the reception of the transmission (reception) data, there is achieved an operation to restore the state in which the symbol synchronization is established at the first position of the data frame. Therefore, symbol synchronization follow-up errors are decreased and there can be achieved a symbol synchronization follow-up operation not easily influenced by disturbing wave such as the cochannel interference.
While the present invention has been described with reference to the particular illustrative embodiments, it is not to be restricted by those embodiments but only by the appended claims. It is to be appreciated that those skilled in the art can change or modify the embodiments without departing from the scope and spirit of the present invention.
Thus, broadly speaking, the invention extends to any apparatus
or method in which the timing used to sample or decode a data frame
comprising a series of symbols is adjusted in response to successful
detection of a preceding frame. In particular, the timing may be set
based on the timing of a symbol, preferably the last symbol, in the
successfully detected frame. In the event of an error, timing is not
adjusted, but, for example, a sampling clock may continue to run without
adjustment of phase, at least for the initial symbol in the subsequent
data frame.
The appended abstract is herein incorporated by reference. Each
feature disclosed above may be independently provided.
Claims (11)
1. A method of receiving data comprising:
receiving a first frame of data comprising a sequence of symbols;
setting the timing at which data is sampled to establish synchronisation with said sequence of symbols;
detecting whether the frame of data contains an error; and
if the first frame is free of errors, setting the initial timing to be used for a second data frame based on the timing of the last symbol of the first data frame.
2. A method according to Claim 1, wherein1 if the first frame contains an error, the initial timing for the second frame is set based on a previously set timing.
3. A method according to Claim 1 or Claim 2, wherein detection of an error is based on an error detection code included in each frame of data that is transmitted.
4. A symbol synchronization follow-up method, comprising the steps of:
detecting, on receiving by a reception side transmission data sent from a transmission side with an error detection code added to each data frame thereof, an error in the data frame of the transmission data and acquiring a result of the error detection; and
receiving the transmission data according to the error detection result, establishing symbol synchronization for the transmission data, following up the symbol synchronization,
holding, when the data frame is free of errors.
sample timing of a last symbol of the data frame and setting the sample timing as an initial value of sample timing of a first symbol of the subsequent data frame; and
setting, when the data frame is associated with any error. sample timing beforehand held as an initial value of sample timing of a first symbol of the subsequent data frame.
5. A method according to any preceding claim, wherein timing
is set by clock means associated with apparatus in which the data is
received1 the phase of the clock means being adjusted in response to
detection of an error-free frame.
6. A symbol synchronization follow-up apparatus comprising:
a transmitter including error detection code generator means for adding an error detection code to each data frame and sending transmission data including the data frame; and
a receiver for receiving the transmission data, wherein the receiver includes:
error detecting means for detecting an error in each data frame of the transmission data and producing an error detection signal; and
symbol synchronizing means for receiving the transmission data according to the error detection result, establishing symbol synchronization for the transmission data, following up the symbol synchronization,
the symbol synchronizing means holding, when the data frame is free of errors, sample timing of a last symbol of the data frame and setting the sample timing as an initial value of sample timing of a first symbol of the subsequent data frame,
the symbol synchronizing means setting, when the data frame is associated with any error, sample timing beforehand held as an initial value of sample timing of a first symbol of the subsequent data frame.
7. A symbol synchronization follow-up apparatus according to claim 6, wherein:
the symbol synchronizing means sends a timing signal indicating a point of timing of sampling the transmission data according to the transmission data in the symbol synchronization follow-up operation; and
the error detecting means samples the transmission data according to the timing signal and thereby producing the error detection signal.
8. Apparatus for receiving data comprising:
means for receiving a first frame of data comprising a sequence of symbols;
means for sampling the received data;
means for setting the timing at which data is sampled to establish synchronisation with said sequence of symbols;
means for detecting whether the frame of data contains an error; and
timing adjustment means arrnaged to set the initial timing to be used for a second data frame based on the timing of the last symbol of the first data frame if the first frame is free of errors.
9. Apparatus according to Claim 8, wherein the timing adjustment means is arranged to adjust the phase of clock means which controls said sampling.
10. Apparatus substantially as herein described, with reference to the accompanying drawings.
11. A method substantially as herein described, with reference to the accompanying drawings.
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP9892496A JPH09284270A (en) | 1996-04-19 | 1996-04-19 | Symbol synchronization tracking method and symbol synchronization tracking device adopting it |
Publications (3)
Publication Number | Publication Date |
---|---|
GB9707835D0 GB9707835D0 (en) | 1997-06-04 |
GB2312361A true GB2312361A (en) | 1997-10-22 |
GB2312361B GB2312361B (en) | 2000-09-06 |
Family
ID=14232684
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
GB9707835A Expired - Fee Related GB2312361B (en) | 1996-04-19 | 1997-04-18 | Symbol synchronization method and apparatus using the same |
Country Status (3)
Country | Link |
---|---|
JP (1) | JPH09284270A (en) |
AU (1) | AU724437B2 (en) |
GB (1) | GB2312361B (en) |
Cited By (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
WO2006032978A3 (en) * | 2004-09-22 | 2006-12-28 | Freesystems Pte Ltd | A method and apparatus for ensuring high quality audio playback in a wireless or wired digital audio communication system |
WO2006070222A3 (en) * | 2004-09-22 | 2007-01-25 | Freesystems Pte Ltd | An apparatus and method for adaptive digital locking and soft evaluation of data symbols in a wireless digital communication system |
Citations (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
GB2075309A (en) * | 1980-04-29 | 1981-11-11 | Sony Corp | Processing binary data framing |
GB2232040A (en) * | 1989-05-04 | 1990-11-28 | Stc Plc | Data stream frame synchronisation. |
GB2264212A (en) * | 1992-02-12 | 1993-08-18 | British Telecomm | Frame synchronisation by use of parity bits in data communication |
Family Cites Families (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US5715278A (en) * | 1993-05-11 | 1998-02-03 | Ericsson Inc. | Standby power saving in mobile phones |
US5528634A (en) * | 1993-11-18 | 1996-06-18 | Motorola, Inc. | Trajectory directed timing recovery |
US5768323A (en) * | 1994-10-13 | 1998-06-16 | Westinghouse Electric Corporation | Symbol synchronizer using modified early/punctual/late gate technique |
-
1996
- 1996-04-19 JP JP9892496A patent/JPH09284270A/en active Pending
-
1997
- 1997-04-18 GB GB9707835A patent/GB2312361B/en not_active Expired - Fee Related
- 1997-04-18 AU AU18975/97A patent/AU724437B2/en not_active Ceased
Patent Citations (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
GB2075309A (en) * | 1980-04-29 | 1981-11-11 | Sony Corp | Processing binary data framing |
GB2232040A (en) * | 1989-05-04 | 1990-11-28 | Stc Plc | Data stream frame synchronisation. |
GB2264212A (en) * | 1992-02-12 | 1993-08-18 | British Telecomm | Frame synchronisation by use of parity bits in data communication |
Cited By (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
WO2006032978A3 (en) * | 2004-09-22 | 2006-12-28 | Freesystems Pte Ltd | A method and apparatus for ensuring high quality audio playback in a wireless or wired digital audio communication system |
WO2006070222A3 (en) * | 2004-09-22 | 2007-01-25 | Freesystems Pte Ltd | An apparatus and method for adaptive digital locking and soft evaluation of data symbols in a wireless digital communication system |
Also Published As
Publication number | Publication date |
---|---|
GB9707835D0 (en) | 1997-06-04 |
AU1897597A (en) | 1997-10-23 |
GB2312361B (en) | 2000-09-06 |
AU724437B2 (en) | 2000-09-21 |
JPH09284270A (en) | 1997-10-31 |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
US5974584A (en) | Parity checking in a real-time digital communications system | |
AU5963194A (en) | Digital demodulator with frequency and timing control | |
US4599723A (en) | Method of encoding data for serial transmission | |
WO1994020898A1 (en) | De-skewer for serial data bus | |
EP0798890A3 (en) | Error correcting apparatus for digital data and digital sync. detecting apparatus | |
CZ315999A3 (en) | Process and apparatus for synchronization | |
US6529148B1 (en) | Apparatus and method for acquisition of an incoming data stream | |
GB2312361A (en) | Symbol synchronisation method and apparatus | |
US6226768B1 (en) | Coded frame synchronizing method and circuit | |
JP2003218838A (en) | Receiver circuit for receiving message signal | |
KR950007977B1 (en) | Method and arrangement for the synchronisation of digital information signals | |
US7301969B2 (en) | OFDM transmitting apparatus, receiving apparatus and transmitting system and signal structure of transmission signal for use in the same | |
JP2508090B2 (en) | Digital communication device | |
JPH08186473A (en) | Demodulator control system | |
JP3106709B2 (en) | Data decoding device | |
US6154512A (en) | Digital phase lock loop with control for enabling and disabling synchronization | |
JP2848229B2 (en) | Receiver circuit | |
JPH05276152A (en) | Synchronization hold circuit | |
JP4487230B2 (en) | Satellite capture device | |
JPH066335A (en) | Pseudo synchronization prevention method for high efficiency voice transmission | |
KR100351800B1 (en) | Rs decoding apparatus | |
JPH04345229A (en) | Squelch system | |
JPH08335930A (en) | Communication equipment and communication method | |
JPS61101138A (en) | Frame synchronizing system | |
JPH1174870A (en) | Data transmitter |
Legal Events
Date | Code | Title | Description |
---|---|---|---|
PCNP | Patent ceased through non-payment of renewal fee |
Effective date: 20020418 |