GB2308249A - A clock frequency multiplier whose output waveform is insensitive to input duty cycle - Google Patents

Description

CLOCK MULTIPLYING METHODS AND APPARATUS USING DELAY LINE LOOP CIRCUITRY Background of the Invention This invention relates to an improved clock multiplying scheme. The invention can be used in programmable logic arrays such as those disclosed in Wong et al. U.S. patent 4,871,930 or Cliff et al. U.S.

patent 5,260,611. However, the invention is not limited to these applications.

In the clock multiplying scheme of commonly assigned, copending application Serial No.

08/571,351, filed December 13, 1995, which is hereby incorporated by reference herein, the resultant multiplied clock signal is the result of an EXCLUSIVE OR type logic function of clock signals having various delays as compared to the reference clock signal. While this circuit is not as sensitive to noise as prior art circuits, this circuit is sensitive to the duty cycle of the reference clock signal. In particular, the duty cycle of the multiplied clock signal is variable depending on the duty cycle of the reference clock. Circuitry receiving the multiplied clock signal usually requires a steady clock signal and may have unpredictable results when the duty cycle of the multiplied clock signal varies.

Thus, there is a need for a clock multiplying scheme in which the resultant multiplied clock signal is not sensitive to the duty cycle of the reference clock signal.

Summary of the Invent ion It is an object of the present invention to provide a method of multiplying the reference clock signal which is not sensitive to the duty cycle of the reference clock signal.

It is a further object of the present invention to provide a method of multiplying the reference clock signal using delay line loop circuitry.

The disadvantages and limitations of other clock multiplying schemes are overcome by the present invention which is a clock multiplying method using delay line circuitry for creating a multiplied clock signal with a frequency which is an integer multiple of the reference clock signal and which is not dependent on the duty cycle of the reference clock signal.

The invention utilizes circuitry with which the reference clock signal is input into a delay line block. To create a multiplied clock signal with a frequency which is an integer n times the frequency of the reference clock, a plurality of signals are brought out from the delay line block. Each of these signals is delayed from the reference signal. The signals brought out may be respectively indicative of a full delay of the reference signal, (l/2n)T of such full delay, (2/2n)T of such full delay, (3/2n)T of such full delay, and so on, up to and including ((2n-2)/2n)T of such full delay and ((2n-1)/2n)T of such full delay.

The multiplied clock signal is achieved from a logic function of these delay signals. For example, when n equals 2, four delay signals are brought out from the delay line block which are indicative of a full delay of the reference, a quarter (1/4) delay of the reference clock signal, a half (1/2) delay of the reference clock signal, and a three-quarter (3/4) delay of the reference clock signal. To create the multiplied clock signal, a first intermediate signal may be produced from the NAND of the full delay signal and the inverse of the one-quarter delay signal. A second intermediate signal may be produced from the NAND of the half delay signal and the inverse of the three-quarter delay signal. The multiplied clock signal may then be produced from the NAND of the first and second intermediate clock signals.

Brief Descrintion of the Drawings The above and other objects and advantages of the invention will be apparent upon consideration of the following detailed description, taken in conjunction with the accompanying drawings, in which like reference characters refer to like parts throughout, and in which: FIG. 1 is a circuit diagram illustrating the clock multiplying scheme of the above-mentioned concurrently filed application in delay line loop circuits; FIG. 2 is a simplified circuit diagram illustrating the clock multiplying scheme of the abovementioned concurrently filed application in delay line loop circuits; FIG. 3 is a simplified circuit diagram showing an illustrative embodiment of a clock multiplying scheme using delay line loop circuitry in accordance with the present invention; FIG. 4A is a diagram illustrating the duty cycle of a multiplied clock signal produced by the apparatus of FIG. 2 in response to a reference clock having a 50% duty cycle; FIG. 4B is a diagram illustrating the duty cycle of a multiplied clock signal produced by the apparatus of FIG. 2 in response to a reference clock having an odd duty cycle; FIG. 5A is a diagram illustrating the duty cycle of a multiplied clock signal produced by the apparatus of FIG. 3 in response to a reference clock having a 50% duty cycle; FIG. 5B is a diagram illustrating the duty cycle of a multiplied clock signal produced by the apparatus of FIG. 3 in response to a reference clock having an odd duty cycle; and FIG. 6 is a circuit diagram showing an illustrative embodiment of a clock multiplying scheme using delay line loop circuitry in accordance with the present invention.

Detailed DescriDtion of the Invention The invention is a clock multiplying scheme in which the resultant multiplied clock signal is not sensitive to the duty cycle of the reference clock.

The invention utilizes delay circuitry, such as delay line loop circuitry, which locks the multiplied clock signal in phase with the reference clock.

FIG. 1 illustrates the circuitry used in the clock multiplying scheme of the above-mentioned concurrently filed application. In this scheme, the reference clock 100 is input to a delay line loop 102 and n signals 144-149 are brought out from the loop.

Each of the n signals 144-149 is delayed from the reference clock. The n signals 144-149 are input to multiplication circuitry 152. The output of the multiplication circuitry 152 is the nXClock signal 154.

The nXClock signal 154 is input into division circuitry 200 where it is divided by n. The divided signal is the feedback clock signal 402, having a frequency of lx. The feedback clock signal 402 is input into a phase/frequency detector 300 where it is compared to the reference clock before being input to a charge pump and loop filter 400. The charge pump and loop filter 400 outputs a control signal 404. It is this control signal 404 which is input to the delay line 406. Thus the delay line loop does not oscillate at the same frequency as nXClock, and thus is not as sensitive to noise. Also, the multiplication circuitry 152 is digital circuitry which is outside of the delay line loop. FIG. 2 is a simplified illustration of FIG.1 in which the clock multiplying circuitry is utilized to create a multiplied clock signal which has a frequency which is twice the frequency of the reference clock signal (n=2). A reference clock signal 100 goes into a delay line loop 102. A Full Delay signal 104 and a Quarter Delay signal 106 are brought out from the delay loop 102. Both the Full Delay signal and the Quarter Delay signal are input to an EXCLUSIVE OR gate or function 108. The output from the EXCLUSIVE OR function is the multiplied clock signal, 2XClock signal 110. This method for creating a multiplied clock signal is sensitive to the duty cycle of reference clock signal 100, as is illustrated in FIGS. 4A and 4B.

FIG. 4A illustrates the 2XClock signal 110 which results from the clock multiplying circuit of FIG. 2 when the reference clock has a 50% duty cycle, i.e., the signal is "on" or at a "high level" for half of the cycle and "off" or at a "low level" for the other half of the cycle. As illustrated in FIG. 4A, the resultant Double Clock signal 110, which is the result of an Exclusive Or function of the Full Delay signal 104 and the Quarter Delay signal 106, also has a 50S duty cycle.

FIG. 4B illustrates the 2XClock signal 110 which results from the clock multiplying circuit of FIG. 2 when the reference clock signal 100 has an odd duty cycle, e.g., the signal is "on" or at a "high level" for longer than the signal is "off" or at a "low level". As illustrated in FIG. 4B, the resultant 2XClock signal 110, which is the result of an Exclusive or function of the Full Delay signal 104 and the Quarter Delay signal 106, also has an odd period.

Thus, the regularity of the 2XClock signal 110 is dependent on the duty cycle of the reference clock signal 100. This is undesirable because the circuitry receiving the 2XClock signal has unpredictable results when the duty cycle of the 2XClock signal varies.

The method of the present invention for creating a multiplied clock signal is not sensitive to the duty cycle of the reference clock signal. FIG. 3 illustrates a preferred embodiment of the present invention utilizing delay line loop circuitry. In this illustration, the clock multiplying circuitry is utilized to create a multiplied clock signal which has a frequency which is twice the frequency of the reference clock (n"2). The reference clock signal 112 goes into a delay line loop 114. Four delay signals, (2n in number), are brought out from the delay line loop 114. As evident in FIG. 3, the following signals may be brought out of delay line loop 114: a Full Delay (2n/2n)T signal 116; an inverted Quarter Delay (1/2n)T signal 118; a Half Delay ((2n-2)/2n)T signal 120; and an inverted Three-Quarter Delay ((2n-1)/2n)T signal 122. The 2XClock signal 134 is the result of a logic function of the delay signals which are brought out from the delay line loop 114. The logic function of the preferred embodiment may be written in Boolean logic as follows: 2XClock signal 134 - (Full Delay 116 * inverted Quarter Delay 118) + (Half Delay 120 * Three-Quarter Delay 122). In the circuitry of FIG. 3, this logic function is implemented in the following manner. The Full Delay signal 116 and the inverted Quarter Delay signal 118 are input to a first NAND logic function or gate 124. The Half Delay signal 120 and the inverted Three-Quarter Delay signal 122 are input to a second NAND logic function or gate 126. The output of the first NAND logic function 128 and the output of the second NAND logic function 130 are input to a third NAND logic function or gate 132. The output of the third NAND logic function or gate 132 is the 2XClock signal 134. 2XClock signal 134 is not sensitive to the duty cycle of the reference clock as is illustrated in FIGS. 5A and 5B.

FIG. 5A illustrates the 2XClock signal 134 which results from the circuitry of the present invention when the reference clock signal has a 50% duty cycle. As is evident from FIG. 5A, the resultant 2XClock signal 134 also has a 50% duty cycle. However, unlike the 2XClock signal resulting from the circuitry of FIG.1, the 2XClock signal resulting from the circuitry of the present invention has a constant period regardless of the duty cycle of the reference clock signal. FIG. 5B illustrates that the 2XClock signal which results from the circuitry of the present invention has a 50% duty cycle and constant period even when the reference clock signal has an odd duty cycle.

FIG. 6 illustrates an embodiment of the present invention for creating a clock signal having a frequency n times that of the reference clock signal, where n is an integer. The reference clock signal 112 goes into the delay line loop 114. Delay signals 202 through 209, 2n in number, are brought out from the delay line loop 114. Delay signals 202 through 209 are delayed from the reference clock as follows: (2n/2n)T; (1i2n)T; (2/2n)T; (3/2n)T; (4/2n)T; (5/2n)T; up to and including ((2n-2)/2n)T and ((2n-1)/2n)T, respectively.

The clock signal 238 is the result of a logic function of the delay signals which are brought out from the delay line loop. The logic function of the embodiment may be written in Boolean logic as follows: ((2n/2n)T delay signal 202 * inverted (1/2n)T delay signal 203) + ((2/2n)T delay signal 204 * inverted (3/2n)T delay signal 205) + ((4/2n)T delay signal 206 * inverted (5/2n)T delay signal 207) + ... + (((2n2)/2n)T delay signal 208 * inverted ((2n-1)/2n)T delay signal 209).

In the circuit of FIG. 6, this logic function is implemented in the following manner. The (2n/2n)T delay signal 202 and the inverted (1/2n)T delay signal 203 are input to a first AND gate 218. The (2/2n)T delay signal 204 and the inverted (3/2n)T delay signal 205 are input to a second AND gate 220. The (4/2n)T delay signal 206 and the inverted (5/2n)T delay signal 207 are input to a third AND gate 222. This circuit continues in this manner until the ((2n-2)/2n)T delay signal 208 and the inverted ((2n-1)/2n)T delay signal 209 are input to an nth AND gate 224. The outputs of the AND gate logic functions 226 through 229 are input to an n-input OR gate 232. The output of the n-input OR gate 232 is the nXClock signal 238. This clock signal has a frequency which is n times the frequency of the reference clock, where n is an integer.

As can be understood with reference to FIG.

6, in the clock multiplying circuit of the present invention, 2n signals 202-209, are brought out from the delay line loop of FIG. 6. The first of these signals 202, being delayed (2n/2n)T from the reference clock signal 112, and every other signal 204, 206, 208, following the first of these signals 202, are each the first input of n two-input AND gates 218, 220, 222 and 224. These signals may be referred to as "even" signals, with the remaining of the 2n delay signals 203, 205, 207 and 209 being referred to as "odd" signals. FIG. 6 illustrates that the inverse of the odd signals 203, 205, 207 and 209 are each the second input of the n two-input AND gates 218, 220, 222 and 224, respectively. The outputs of the AND gates 226 through 229 are input to an n-input OR gate 232. The output of the OR gate 232 is the multiplied clock signal 238.

Another way to look at and describe the present invention is to note that all of the transitions and re-transitions in the multiplied clock signals are produced from transitions of one polarity of the reference clock signal. For example, in FIG. 6, both rises ("transitions") and falls ("re-transitions") in the nXClock signal 238 are triggered from rises ("transitions") in the reference clock signal 112.

Logic circuitry 218, 220, 222 and 224 prevents the clock signal from responding to falls ("retransitions") in the reference clock signal 112.

Rather, the circuitry of FIG. 6 produces a transition in the clock signal 238 in response to each of the transitions in the even signals, and produces a retransition in the nXClock signal 238 in response to each of the transitions in the odd signals.

Looking again at either FIG. SA or FIG. 5B, when n"2, the first rise ("transition") in 2XClock signal 134 is triggered by the first rise ("transition") in Full Delay signal 116. The first fall ("re-transition") in 2XClock signal 134 is triggered by the first rise ("transition") in the Quarter Delay signal (which is actually inverted as shown at 118 so that the first rise in the Quarter Delay signal produces the first fall in depicted inverted Quarter Delay signal 118). The second rise ("transition") in 2XClock signal 134 is triggered by the first rise ("transition") in Half Delay signal 120.

And the second fall ("re-transition") in 2XClock signal 134 is triggered by the first rise ("transition") in the Three-Quarter Delay signal (which is actually inverted as shown at 122 so that the first rise in the Three-Quarter Delay signal produces the first fall in depicted inverted Three-Quarter Delay signal 122).

Because the logic circuitry of this invention prevents 2XClock signal 134 from responding to retransitions in reference clock signal 112, it does not matter when those re-transitions occur between transitions in signal 112. The duty cycle of the reference clock signal therefore does not affect the regularity of the clock signal. (Whether clock signal 238 responds to rises or falls in reference clock signal 112 is arbitrary, and it will be understood that signal features and terms like "transition" and "re-transition" or "rise" and "fall" can be reversed if desired.) While a delay line loop 114 has been described as producing signals which are delayed T, T/2n, 2T/2n, 3Ti2n, etc. (where T is the "period" of, or time interval between successive rises ("transitions") or successive falls ("re-transitions") in, reference clock signal 112), it will be understood that each of these time delays can be modified by any other time delay "t". Thus the actual delay of the signals mentioned in the preceding sentence may be t+T, t+T/2n, t+2T/2n, t+3T/2n, etc. Also, a delay of T (or t+T) is logically the same as a zero delay (or a delay of t), but either delay will be referred to as a "full" delay.

Thus a logic circuit for creating a multiplied clock signal with a frequency which is an integer multiple of the reference clock signal and which is not sensitive to the duty cycle of the reference clock is provided. Although particular illustrative embodiments have been disclosed, persons skilled in the art will appreciate that the present invention can be practiced by other than the disclosed embodiments, which are presented for purposes of illustration, and not of limitation, and the present invention is limited only by the claims that follow.

Claims (28)

WHAT IS CLAIMED IS:

1. A method for creating a clock signal with a frequency which is an integer multiple of the frequency of a reference clock signal, said reference clock signal having a duty cycle, comprising: inputting the reference clock signal into delay circuitry so as to create a plurality of delay signals having various delays as compared to the reference clock signal; and creating a logic function of the delay signals which result in a clock signal having a frequency which is an integer multiple of the frequency of the reference clock signal, and which is not sensitive to the duty cycle of the reference clock signal.

2. The method of claim 1 wherein the delay circuitry comprises delay line loop circuitry.

3. The method of claim 1 wherein the circuitry of the logic function is outside of the delay circuitry.

4. The method of claim 1 wherein the circuitry of the logic function is digital circuitry.

5. A method for creating a clock signal with a frequency which is n times the frequency of a reference clock signal, where n is an integer, said reference clock signal having a duty cycle, comprising: inputting the reference clock signal into delay circuitry so as to create n pairs of delay signals which include a (2n/2n)T delay signal, an inverted (1/2n)T delay signal, a ((2n-2)/2n)T delay signal and an inverted ((2n-1)/2n)T delay signal as compared to the reference clock signal; and creating a logic function of the delay signals which results in a clock signal that has a frequency which is n times that of the reference clock signal and a duty cycle which is not sensitive to the duty cycle of the reference clock signal.

6. The method of claim 5 wherein the delay circuitry comprises delay line loop circuitry.

7. The method of claim 5 wherein the circuitry of the logic function is outside of the delay circuitry.

8. The method of claim 5 wherein the circuitry of the logic function is digital circuitry.

9. Apparatus for producing an output clock signal which has n times the frequency and lin times the period of a reference clock signal, with n being an integer, the period of each of said signals being given by the time interval between successive transitions of a predetermined polarity in said signal, the period of said reference clock signal being the time interval T, and wherein t is any predetermined time interval, said apparatus comprising: a delay circuit responsive to said reference clock signal for producing 2n signals having transitions that are delayed relative to transitions in said reference clock signal, wherein half of the 2n signals are even signals and half of the 2n signals are odd signals; and logic circuitry responsive to said delay signals for producing a transition in said output clock signal in response to each of said transitions in the even signals, and for producing a re-transition in said output clock signal in response to each of said transitions in the odd signals.

10. The apparatus defined in claim 9 wherein said logic circuitry prevents said output logic signal from responding to re-transitions in said reference clock signal.

11. The apparatus defined in claim 9 wherein said logic circuitry prevents said output logic signal from responding to re-transitions in said 2n signals.

12. A method for creating a clock signal from a reference clock signal, said reference clock signal having a duty cycle, comprising: inputting the reference clock signal into delay circuitry so as to create a plurality of delay signals having various delays as compared to the reference clock signal; and creating a logic function of the delay signals which result in a clock signal having a frequency which is twice that of the reference clock signal and which is not sensitive to the duty cycle of the reference clock signal.

13. The method of claim 12 wherein the delay circuitry comprises delay line loop circuitry.

14. The method of claim 12 wherein the circuitry of the logic function is outside of the delay circuitry.

15. The method of claim 12 wherein the circuitry of the logic function is digital circuitry.

16. A method for creating a clock signal from a reference clock signal, said reference clock signal having a duty cycle, comprising: inputting the reference clock signal into delay circuitry so as to create four delay signals having various delays as compared to the reference clock signal; and creating a logic function of the delay signals which result in a clock signal having a frequency which is twice that of the reference clock signal and which is not sensitive to the duty cycle of the reference clock signal.

17. The method of claim 16 wherein the delay circuitry comprises delay line loop circuitry.

18. The method of claim 16 wherein the circuitry of the logic function is outside of the delay circuitry.

19. The method of claim 16 wherein the circuitry of the logic function is digital circuitry.

20. A method for creating a clock signal from a reference clock signal, said reference clock signal having a duty cycle, comprising: inputting the reference clock signal into delay circuitry so as to create a full delay signal, a half delay signal, an inverted three-quarter delay signal, and an inverted quarter delay signal as compared to the reference clock signal; and creating a logic function of the delay signals which result in a clock signal having a frequency which is twice that of the reference clock signal and which is not sensitive to the duty cycle of the reference clock signal.

21. The method of claim 20 wherein the delay circuitry comprises delay line loop circuitry.

22. The method of claim 20 wherein the circuitry of the logic function is outside of the delay circuitry.

23. The method of claim 20 wherein the circuitry of the logic function is digital circuitry.

24. Apparatus for producing an output clock signal which has twice the frequency and half the period of a reference clock signal, the period of each of said signals being given by the time interval between successive transitions of a predetermined polarity in said signal, the period of said reference clock signal being the time interval T, and wherein t is any predetermined time interval, said apparatus comprising: a delay circuit responsive to said reference clock signal for producing first, second, third, and fourth signals respectively having transitions that are delayed relative to transitions in said reference clock signal by delays t+T/4, t+T/2, t+3T/4, and t+T; and logic circuitry responsive to said first, second, third, and fourth signals for producing a transition in said output clock signal in response to each of said transitions in said first and third signals, and for producing a re-transition in said output clock signal in response to each of said transitions in said second and fourth signals.

25. The apparatus defined in claim 24 wherein said logic circuitry prevents said output logic signal from responding to re-transitions in said reference clock signal.

26. The apparatus defined in claim 24 wherein said logic circuitry prevents said output logic signal from responding to re-transitions in said first, second, third, and fourth signals.

27. The apparatus defined in claim 24 wherein said logic circuitry performs a logic function on said first, second, third, and fourth signals which is logically equivalent to the logical OR of (1) the logical AND of the fourth signal and the inverse of the first signal and (2) the logical AND of the second signal and the inverse of the third signal.

28. The apparatus defined in claim 27 wherein said logic circuitry comprises: a first NAND gate whose inputs are the fourth signal and the inverse of the first signal, and whose output is a first intermediate signal; a second NAND gate whose inputs are the second signal and the inverse of the third signal, and whose output is a second intermediate signal; and a third NAND gate whose inputs are the first and second intermediate signals, and whose output is said output clock signal.