GB2308250A

GB2308250A - Clock frequency multiplier using a delay line loop

Info

Publication number: GB2308250A
Application number: GB9622934A
Authority: GB
Inventors: John E Turner; Behzad Nouban
Original assignee: Altera Corp
Current assignee: Altera Corp
Priority date: 1995-12-13
Filing date: 1996-11-04
Publication date: 1997-06-18
Also published as: GB9622934D0

Description

CLOCK MULTIPLYING APPARATUS USING DELAY LINE LOOP CIRCUITRY Backaround of the Invention This invention relates to clock multiplying schemes using delay line loop circuitry. The invention can be used in programmable logic arrays such as those disclosed in Wong et al. U.S. patent 4,871,930 or Cliff et al. U.S. patent 5,260,611. However, the invention is not limited to these applications.

Walzman, A., "A Delay Line Loop for Frequency Synthesis of De-Skewed Clock," ISSCC Digest of Technical Papers, pp. 298-299, 1994, discloses clock frequency synthesis using a delay line loop. In the Walzman method, the resultant clock signal is input back to the delay line loop to form a ring oscillator, otherwise known as a Voltage Controlled Oscillator, or VCO. In the Walzman method the reference clock signal is not directly input into the delay line loop. Such circuitry is very sensitive to the noise of the circuit. One reason for this in that the frequency synthesis takes place in the delay line loop, which is analog circuitry, and which is very sensitive to noise.

A second reason for the sensitivity to noise is the ring oscillator. The ring oscillator causes the delay line loop to oscillate at the same frequency as the resultant clock signal. This oscillation exaggerates any noise in the circuitry which causes a greater effect on the resultant clock signal. Thus, the resultant clock signal may not lock in frequency with the incoming clock or the resultant clock signal may take a significant amount of time to lock in frequency with the incoming clock. This causes the resultant clock signal to be unpredictable. Circuitry receiving the resultant clock signal requires a signal which is frequency-locked with the reference clock. Such circuitry has unpredictable results when the resultant clock signal varies. Thus, there is a need for a clock multiplying scheme in which the resultant multiplied clock signal is not as sensitive to the noise of the circuit.

Summary of the Invention It is an object of the present invention to provide a method of multiplying the reference clock signal which is not as sensitive to the noise of the circuit.

It is a further object of the present invention to provide a method of multiplying the reference clock signal in delay line loop circuitry.

It is a further object of the present invention to provide a method of multiplying the reference clock signal in delay line loop circuitry which oscillates at the frequency of the reference clock.

It is a further object of the present invention to provide a method of multiplying the reference clock signal in which the multiplication circuitry is digital.

The disadvantages and limitations of previous clock multiplying schemes are overcome by the present invention which is a clock multiplying method using delay circuitry which is not as sensitive to the noise of the circuit.

The invention utilizes circuitry with which the reference clock signal is input into delay circuitry. To create a multiplied clock signal with a frequency which is an integer n times the frequency of the reference clock, a plurality of signals are brought out from the delay circuitry. Each of these signals is delayed from the reference signal. The signals brought out may be respectively indicative of a full delay of the reference signal, 1/2n of such full delay, 2/2n of such full delay, 3/2n of such full delay and so on, up to and including (n-l)/2n of such full delay. The multiplied clock signal is achieved from a logic function of these delay signals. For example, when n-2, two delay signals are brought out from the delay circuitry which are indicative of a full delay of the reference clock signal, and a quarter delay (1/4) of the reference clock signal. The multiplied clock signal may be produced from the EXCLUSIVE OR of the full delay signal and the quarter delay signal.

Brief Descrintion of the Drawinas The above and other objects and advantages of the invention will be apparent upon consideration of the following detailed description, taken in conjunction with the accompanying drawing, in which like reference characters refer to like parts throughout, and in which: FIG. 1 is a circuit diagram showing an illustrative embodiment of a clock multiplying scheme using delay line loop circuitry in accordance with the present invention.

FIG. 2 is a more detailed circuit diagram of the embodiment of FIG. 1.

FIG. 3 is a circuit diagram showing a particular case of the more general embodiment of FIG.

1.

FIG. 4 is a schematic diagram of an illustrative embodiment of a portion of the circuit shown in FIG. 1 or FIG. 2.

FIG. 5 is a schematic diagram of another illustrative embodiment of a portion of the circuit shown in FIG. 1 or FIG. 2.

Detailed Descrintion of the Invention The invention is a clock multiplying scheme in which the resultant multiplied clock signal is not an sensitive to the noise of the circuit. The invention utilizes delay circuitry, such as delay line loop circuitry, which locks the multiplied clock signal in phase with the reference clock.

FIG. 1 illustrates the circuitry used in an embodiment of the present invention for creating a clock signal having a frequency n times that of the reference clock signal, where n is an integer. A Reference Clock signal 100 goes into a delay line loop 102. Delay signals 104 through 109, n in number, are brought out from the delay line loop. Delay signals 104 through 109 are delayed from the reference clock as follows: (2n/2n)T; (1/2n)T; (2/2n)T; (3/2n)T; up to and including ((n-1)/2n)T, respectively, where T is the period of the reference clock signal. The nXClock signal 114 is the result of a logic function of the delay signals which are brought out from the delay line loop.

In the circuit of FIG. 1, this logic function is implemented in the following manner. All of the delay signals 104 through 109 are input to a clock multiplier function 112. The output from the clock multiplier function is the nXClock signal 114. The nXClock signal 114 is a logic zero (0) if an even number of the n inputs are a logic one (1), and is a logic one (1) if an odd number of the n inputs are a logic one (1). For example, FIG. 4 shows a network of two-input EXCLUSIVE OR gates 10 that performs this logic function on the n output signals of a delay line loop. FIG. 5 shows another example of a network of two-input EXCLUSIVE OR gates 10, 12, 14, etc. that performs this logic function on the n output signals of a delay line loop. It will be understood that FIGS. 4 and 5 are only illustrative, and that other logic circuitry can be used to implement the above-described logic function if desired.

In this method for creating a multiplied clock signal, the nXClock signal is not directly fed back into the delay line loop. Instead, as is illustrated in FIG. 2, the nXClock signal 114 is input into division circuitry 200 where it is divided by n.

The divided signal is the feedback clock signal 402, having a frequency of 1X. The feedback clock signal 402 is input into a phase/frequency detector 300 where it is compared to the reference clock before being input to a charge pump and loop filter 400. The charge pump and loop filter 400 outputs a control signal 404.

It is this control signal 404 which is input to the delay line 406. Thus the delay line loop does not oscillate at the same frequency as nXClock, and thus is not as sensitive to noise. Also, as is evident from FIGS. 1 and 2, the multiplication circuitry 112 is digital circuitry which is outside of the delay line loop. Thus, this circuitry is not as sensitive to the noise of the circuit. Therefore, the multiplied clock signal locks in frequency with the reference clock more quickly and does not lose the frequency lock with the reference signal.

FIG. 3 illustrates a preferred embodiment of the present invention utilizing delay line loop circuitry. In this illustration, the clock multiplying circuitry is utilized to create a multiplied clock signal which has a frequency which is twice the frequency of the reference clock (n"2). The Reference Clock signal 100 goes into a delay line loop 102. A Full Delay (2n/2n)T signal 104 and a Quarter Delay ((n 1)/2n)T signal 105 are brought out from the delay loop 102. Both the Full Delay signal and the Quarter Delay signal are input to a clock multiplier function 112.

The output from the clock multiplier function 112 is the 2XClock signal 114. In the embodiment illustrated in FIG. 3, the clock multiplier function is implemented as a two-input EXCLUSIVE OR gate.

While delay line loop 102 has been described as producing signals which are delayed (2n/2n)T, (1/2n)T, (2/2n)T, (3/2n)T, up to and including ((n1)/2n)T, (where T is the "period" of, or time interval between successive rises ("transitions") or successive falls ("re-transitions") in, Reference Clock signal 100), it will be understood that each of these time delays can be modified by any other time delay "t".

Thus the actual delay of the four signals mentioned in the preceding sentence may be t+(2n/2n)T, t+(l/2n)T, t+(2/2n)T, t+(3/2n)T, up to and including t+((n1)/2n)T. Also, a delay of T (or t+T) is logically the same as a zero delay (or a delay of t), but either delay will be referred to as a "full" delay.

Thus a logic circuit for creating a multiplied clock signal which is not as sensitive to the noise of the circuit is provided. Although a particular illustrative embodiment has been disclosed, persons skilled in the art will appreciate that the present invention can be practiced by other than the disclosed embodiment, which is presented for purposes of illustration, and not of limitation, and the present invention is limited only by the claims that follow.

Claims

WHAT IS CLAIMED IS:

1. Apparatus for producing an output clock signal which has an integer n times the frequency and 1/n the period of a reference clock signal, the period of each of said signals being given by the time interval between successive transitions of a predetermined polarity in said signal the period of said reference clock signal being the time interval T, and wherein t is any predetermined time interval, said apparatus comprising: a delay circuit responsive to said reference clock signal for producing n signals having transitions that are delayed relative to transitions in said reference clock signal; and logic circuitry responsive to said signals for producing said output clock signal.

2. The apparatus defined in claim 1 wherein said logic circuitry performs a logic function on said n signals which results in a logic zero (O) if an even number of the n inputs are a logic one (1), and results in a logic one (1) if an odd number of the n inputs are a logic one (1).

3. The apparatus defined in claim 1 wherein the delay circuit comprises delay line loop circuitry.

4. The apparatus defined in claim 1 wherein the logic circuitry is outside of the delay circuit.

5. The apparatus defined in claim 1 wherein the logic circuitry is digital circuitry.

6. Apparatus for producing an output clock signal which has twice the frequency and half the period of a reference clock signal, the period of each of said signals being given by the time interval between successive transitions of a predetermined polarity in said signal the period of said reference clock signal being the time interval T, and wherein t is any predetermined time interval, said apparatus comprising: a delay circuit responsive to said reference clock signal for producing a first and a second signal having transitions that are delayed relative to transitions in said reference clock signal by delays t+T/4 and t+T; and logic circuitry responsive to said first and second signals for producing said output clock signal.

7. The apparatus defined in claim 6 wherein the delay circuit comprises delay line loop circuitry.

8. The apparatus defined in claim 6 wherein the logic circuitry is outside of the delay circuit.

9. The apparatus defined in claim 6 wherein the logic circuitry is digital circuitry.

10. The apparatus defined in claim 6 wherein said logic circuitry performs a logic function on said first and second signals which is logically equivalent to the logical EXCLUSIVE OR of the first and second signals.

11. The apparatus defined in claim 10 wherein said logic circuitry comprises an EXCLUSIVE OR gate whose inputs are the first signal and the second signal, and whose output is said output clock signal.