GB2307364A

GB2307364A - Voltage clamp circuit; non-contact type information card

Info

Publication number: GB2307364A
Application number: GB9624047A
Authority: GB
Inventors: Shigeru Arisawa
Original assignee: Sony Corp
Current assignee: Sony Corp
Priority date: 1995-11-20
Filing date: 1996-11-18
Publication date: 1997-05-21
Anticipated expiration: 2016-11-18
Also published as: GB2307364B; JPH09148869A; GB9624047D0; JP3755675B2

Abstract

A voltage clamp circuit 25 comprises a group of Darlington connected bipolar transistors (Tr[1] to Tr[M], Fig. 2) is series with a group of diode-connected MOS transistors (PMOS[1] to PMOS[N]). Use of the diode-connected MOS transistors in place of some of the Darlington connected bipolar transistors of a prior art voltage clamp (Figs.7,8) avoids the clamping action being interfered with by a parasitic transistor (Fig. 2) associated with a diode-connected transistor Tr(0) which acts as a rectifier/detector connected to a resonance circuit 10, C3 of a non-contact information card used in an automatic ticket clipping system. An electromagnetic wave from a reader/writer (2, Fig.6) is applied to the card for writing and reading data to/from the card and for supplying power to the card. A digital signal processor 15 receives input data from the resonance circuit, and turns a transistor 11 on and off to change the resonance frequency of the resonance circuit for reading out data. The power supply for the card includes a smoothing capacitor C5 and a voltage regulator 13.

Description

CLAMP CIRCUIT AND NON-CONTACT TYPE INFORMATION CARD This invention relates to an information card used in a non-contact type card system such as an automatic ticket clipping system or the like.

The existing automatic ticket clipping system at present employs a method of reading out information of a commutation ticket inserted by a user into an automatic ticket clipping machine by a magnetic head being in contact with the commutation ticket. Accordingly, the user needs to take out the commutation ticket from a case and insert it into the automatic clipping machine. In other words, the existing system requires much labour in operation.

To cope with such an inconvenience, the present applicant has previously proposed a convenient non-contact type card system not requiring such a troublesome operation.

According to this non-contact type card system, information can be processed (by data communication or the like) in a non-contact manner, so that when the system is applied to the aforesaid automatic ticket clipping system, a user can conveniently enter or exit out of the automatic ticket clipping machine with the commutation ticket being stored in a case. The non-contact type card system previously proposed by the applicant is shown in Figure 6 of the accompanying drawings. As shown in this figure, a noncontact type card system 1 is composed of a reader/writer 2 corresponding to the aforesaid automatic ticket clipping machine and an IC card 3 corresponding to the aforesaid commutation ticket, wherein an electromagnetic wave is applied as the medium to supply an electrical power and to read or write data.

The reader/writer 2 discharges an electromagnetic wave through a loop antenna 9 formed on a printed circuit board 8 to supply an electrical power to the information card 3 in a non-contacted state and to write data in it. In addition, the reader/writer 2 may receive a reflection wave coming from the information card 3 through the loop antenna 9 formed on the printed circuit board 8 and read out information stored in the information card. In this case, the transmitted data and the received data are processed by a digital signal processing section 6 and a host computer 7, respectively. In addition, the present applicant has proposed a method in which all functions required by the information card 3 are realized with one CMOS Complementary MOS) chip IC.

Fig. 7 shows another example of configuration of the information card 3 previously proposed by the present applicant. An IC card 3A shown in Fig. 7 uses a transistor Tr(0) in which a base and an emitter are connected to each other and a collector is connected to the ground, in place of a rectifier/detector diode D2 in the IC card 3 shown in Fig. 6. The connection point between the base and the emitter is connected to a connection point D between a loop antenna 10 and a capacitor C3. One end of a capacitor C4 is connected to the connection point D for changing a resonance frequency of the resonance circuit composed of the loop antenna 10 and the capacitor C3, and the other end of the capacitor C4 is connected a drain of a FET 11.A source of the FET 11 is connected to the ground (connected to a P substrate) and a gate thereof is connected to a digital signal processing section 15 in the same manner as that shown in Fig. 6.

An overvoltage protection circuit 16 (a resistor R2 and a transistor group 16A) is arranged at a rear stage of the rectifier/detector transistor Tr (0) in place of a overvoltage protection circuit 12 (a resistor R2, diode groups 12A, 12B) shown in Fig. 6, and one end of the resistor R2 is connected to a point D (I) of the connection point C or D between the loop antenna 10 and the capacitor C3. In addition, the other end of the resistor R2 is connected to an emitter of the foremost stage transistor (PNP transistor) of the transistor group 16A and a base of the final stage transistor (PNP transistor) thereof is connected to the ground.

In addition, a voltage drop of 0.7 [V], for example, is produced between the emitter and the base of each of the transistors constituting the transistor group 16A. The transistor group 16A is composed of five transistors (PNP transistors), for example. Accordingly, the overvoltage protection circuit 16 composed of the resistor R2 and the transistor group 16A is constructed such that a potential between the connection points C and D of the loop antenna 10 and the capacitor C3 is restricted in the same manner as that of the overvoltage protection circuit 12 shown in Fig.

6.

In the information card constructed as described above, when an electromagnetic wave is radiated from the reader/writer 2 shown in Fig. 6, an electromotive force is generated in response to a variation in the magnetic flux (magnetic field) of the electromagnetic wave crossing the loop antenna 10. Of the voltage thus generated, a voltage component having a predetermined frequency range centered at a resonance frequency of a parallel resonance circuit composed of the loop antenna 10 and the capacitor C3 is allowed to efficiently pass through a block of the rear stage.

The signal passing through the parallel resonance circuit composed of the loop antenna 10 and the capacitor C3 is rectified through the transistor Tr(0) without occurrence of any substantial loss and is removed in ripple through a smoothing capacitor C5. The signal from which the ripple is removed is supplied to a constant-voltage regulator 13, to be stabilized at a predetermined specified voltage VDD. The voltage VDD is supplied to the digital signal processing section 15 as a power supply.

After the digital signal processing section 15 is turned in an operation state by the power supply thus fed, the signal passing through the parallel resonance circuit composed of the loop antenna 10 and the capacitor C3 is detected through the transistor Tr(0) and outputted to the digital signal processing section 15 through a capacitor C7 and an amplifier 14. The digital signal processing section 15 then interprets the content of the detected command, to carry out a predetermined processing on the basis of the interpreted content.

In turn, in the case where a data reading-out operation is carried out, a voltage corresponding to the data read out of a non-volatile memory 15A is applied to the gate of the FET11, to turn on or off the FET11. When the FET11 is turned on, one end of the capacitor C4 connected to the FET11 becomes equal to the case in which it is connected to a point C, that is, one end of the capacitor C3 through the FET11, substrate, point F, capacitor C5, points E and I short circuited by AC. As a result, a resonance frequency of a resonance circuit composed of the loop antenna 10 and the capacitor C3 is changed between on and off of the FET11.

In addition, when the information card 3A approaches very near to the reader/writer 2 and thereby a high current is outputted from the resonance circuit composed of the loop antenna 10 and the capacitor C3, that is, when a voltage more than a protection voltage is applied between the points I and J, a current flows from the emitter to the base of each of the transistors constituting a transistor group 16A (along with this operation, the current also flows from the emitter to the collector). On the other hand, when a high current is outputted from a resonance circuit composed of the loop antenna 10 and a coil C3, part of the current flows as a bypassing current in the resistor R2 and the transistor group 16A, thus restricting a peak value of the output voltage of the resonance circuit.

The information card proposed in the earlier application, in which the overvoltage protection circuit 16 constituting a front end of the information card is composed of a resistor element R2 and a clamp circuit (a transistor group 16A) as shown in Fig. 8, has a disadvantage that a clamp voltage at this clamp circuit is dropped due to the following two reasons, thus shortening a communication available distance.

The first reason is as follows. Since the transistor group 16A constituting the clamp circuit is so-called Darlington connected to each other, a base current of each of the transistors is decreased exponentionally with respect to the number of the laminated stages of the transistor group 16A, as shown in Fig. 9. More specifically, for the transistor group 16A in which a large number of the transistors are laminated, a base current of the transistor at the ground side becomes quite low.

Letting IB(k), IE(k) be a base current and an emitter current flowing in the transistor Tr(k) of k-th stage respectively, and hfc be a current amplification rate, the base current flowing in the transistor Tr(k) of k-th stage is given by the following equation.

Accordingly, it is apparent that a base current 1B(M) flowing in the M-th one of the transistors laminated in the number of M becomes almost zero in accordance with the following equation.

Since a voltage drop between a base and an emitter with respect to a base current is in an exponentional relationship as described above, it is scarcely possible to obtain the voltage drop between the emitter and the base when the base current is extremely low. As a result, for the transistor group 16A in which a large number of the transistor are laminated to each other, the voltage drop between the emitter and the base of the transistor near the ground becomes quite low, thereby making it difficult to obtain a desired voltage drop of the transistor group 16A.

The second reason will be described with reference to Figures 10,11. Figure 10 shows a sectional structure of an IC chip of the front end of the information card shown in Figure 7 and Figure 11 shows its equivalent circuit.

In these figures, Tr(O) corresponds to the rectifier/detector transistor shown in Figure 7, and TR(1) to Tr(N) correspond to the transistor group 16A constituting the clamp circuit.

From these figures, it becomes apparent that a PN junction between the collector and the base of the rectifier/detector transistor Tr(0) and the base of each of the transistors of the transistor group 16A may form a parasitic-NPN transistor.

Then, it will be described below how action may be applied by this parasitic-transistor when the rectifier/ detector circuit is operated.

When the rectifier/detector transistor is operated, it is naturally found that a current flows through the PN junction face between the collector and the base of the transistor Tr(0). At this time, since a base current flows through the parasitic transistor, the parasitic-NPN transistor is turned on to make conductive the collector to the emitter. However, the collector of the parasitic-NPN transistor is concurrently a connection point of each of the transistors in the transistor group 16A, so that a voltage at the connection point is dropped to a CM level.

With the aforesaid mechanism, the clamp voltage of the transistor group 16A is interfered with the rectifier/detector circuit (that is, the rectifier/detector transistor Tr(O)) and forcibly dropped to the CM level.

From these reasons, the voltage drop of the transistor group 16A is dropped lower than a desired voltage.

In that case, a current flows even when a voltage less than the protective voltage is applied between the points I and J, with a result that a loss of the received electrical power may occur. This causes a disadvantage that a communication reaching distance is shortened.

In addition to the foregoing, to obtain a clamp voltage for an overvoltage protection circuit on a MOS process, the MOS transistor may be dependently connected onto a diode. In this method, however, it is difficult for MOSs of normal size in view of its layout to accommodate for all the excessive currents during the clamping operation.

Moreover, this method tends to be affected by a variation in Vlh caused by dispersion of process.

The present invention has been devised in view of the foregoing points, and provides a non-contact type information card storing a clamp circuit which is difficult to affect by surrounding circuitry.

According to the present invention, there is provided a clamp circuit comprising a plurality of clamp circuit stages composed of groups of different elements, which are dependently connected to each other, wherein clamp voltage compensation for characteristics of said clamp circuit stages are generated at both ends of said clamp circuit stages.

Accordingly, it becomes possible to obtain a desired voltage not affected by interference from a rectifier/detector circuit and/or other surrounding circuits.

The invention will be further described by way of non-limitative example with reference to the accompanying drawings, in which: Figure 1 is a block diagram showing an entire configuration of an information card of the present invention; Figure 2 is an equivalent circuit diagram showing a connection configuration of a front end part using a clamp circuit of the present invention; Figure 3 is a plan view showing an example of configuration of layout of a transistor group for the clamp circuit; Figure 4 is a schematic diagram showing a sectional structure of a chip; Figure 5 is a block diagram showing a simple layout configuration at the front end; Figure 6 is a block diagram showing a general configuration of a non-contact type card system; Figure 7 is a block diagram showing the prior art information card; ; Figure 8 is a connection diagram showing an overvoltage protection circuit; Figure 9 is a graph showing a relationship between a base-emitter voltage and a base current Figure 10 is a schematic diagram showing the sectional structure of a chip shown in Figure 8; and Figure 11 is a connection diagram showing a configuration at the prior art front end.

(1) Base Structure In this embodiment, some transistors, from the ground side, of a transistor group in a clamp circuit constituting of an overvoltage protection circuit are replaced with diode-connected MOS transistors so as to obtain a structure in which the MOS transistors and the bi-polar transistors are combined to each other. However, replacement of too many transistors with the diodeconnected MOS transistors increases a dependency of dispersion of process, so that only several transistors on the ground side tending to be affected by the rectifier circuit are replaced with the diode-connected MOS transistors.

In this embodiment, the transistors of the transistor group are arranged on an IC layout in a nesting manner. Namely, a second stage transistor Tr(2) is placed inside a first stage transistor Tr(1); a third stage transistor Tr(3) is placed inside the second stage transistor Tr(2); and the same rule is repeated until an Mth stage transistor Tr(M) is located at the inner-most position, to form a structure for protecting the transistor tending to be affected by interference of the rectifier/ detector circuit and/or other surrounding circuits.

(2) Practical Example An operation of a basic structure used in the embodiment will be described. Fig. 1 shows one example of an information card 23 using a clamp circuit 24 of the present invention. Fig. 2 shows a configuration of a front end part using the clamp 24. The front end part is composed of an overvoltage protection circuit 25 and a rectifier/detector circuit Tr(O).

Referring now to this figure, the operation of the overvoltage protection circuit will be described.

A current flowing through each of the bi-polar transistors and each of MOS transistors will be first examined. The clamp circuit 24 is composed of M (bip) pieces of bi-polar transistors and N (mos) pieces of MOS transistors; however, for a sake of convenience in description, number is applied in sequence to each of the transistors from a CP side. A relationship of each of the currents is given by the following equation.

In this equation, IB IK) and 1(K) indicate a base current and an emitter current of a k-th stage bi-polar transistor respectively; hfc indicates a current amplification rate; and Iso) and It(1) indicate a source current and a drain current of an MOS1 respectively.

From the above equation, the base current 1B(K) of the k-th stage bi-polar transistor and the source current 1S(1) of the MOS1 are expressed by the following equation.

Since the number M (prev) of parasitic transistors is larger than the number M (bip) of the bi-polar transistors, Ih(Mtbip]J = IS(K) = ID(K) > > IBIM(prev)] = O is attained on the basis of the above equation.

Accordingly, a voltage drop between an emitter and a base of the transistor is assured and a desired clamp voltage can be attained in the entire clamp circuit.

With such an arrangement, the current flowing in the MOS transistor can be adjusted to the most suitable value (IBIP X [1/1 + hfC]M(biP)), with a result that the MOS transistors can be arranged on the IC chip of an actual size.

Moreover, this clamp circuit has an advantage that it is difficult to be affected by the dispersion of process as compared with the clamp circuit composed of only the diodeconnected MOS transistors.

Next, an interference applied by the parasitic transistor will be examined. In Figure 2, character Parasitic-NPN indicates a parasitic-transistor.

When a current flows in the rectifier/detector transistor Tr(O), the parasitic transistor turns on between the collector and emitter and it exerts such an adverse effect that a voltage of the clamp circuit is dropped to a voltage on the CM side. In this case, the anti-interference of the clamp circuit is increased linearly with the current flowing in the clamp circuit. Since the current flowing in the clamp circuit of the present invention is higher than that flowing in the clamp circuit previously proposed, it is hardly affected by the interference.

An arrangement in layout will be described as follows.

Figs. 3 and 4 show one example of a layout of the overvoltage protection circuit and the rectifier/detector section.

In these figures, the transistors of the transistor group are arranged in a nesting manner that a (m + l)-th transistor is placed inside a m-th transistor, wherein the MOS transistor tending to be affected by the rectifier/ detector circuit or other surrounding circuits is layout more inside.

With such a layout, even if a leak current flows to the clamp circuit from other surrounding circuit blocks, the bi-polar transistor located outside and hardly affected by the interference accommodate for a leak current, and thereby the leak current does not flow to the MOS transistor easily affected by the interference. As a result, an anti-interference property from the surrounding circuits in the clamp circuit is improved. Since influence applied by the parasitic transistor may also be similarly considered, the above layout makes it possible to prevent the clamp voltage from being decreased by the parasitic transistor.

Although it is impossible to improve an antiinterference characteristic from the surrounding circuits other than the rectifier/detector circuit, the layout in the order of the rectifier/detector circuit, MOSN, , MOS1, TrM, , Trl enables a degree of influence from the rectifier/detector circuit TrO to be reduced.

With the foregoing configuration, it is possible to realize a clamp circuit capable of obtaining a desired voltage without being affected by interference of a rectifier/detector circuit and/or other surrounding circuits. Accordingly, the non-contact type information card using the overvoltage protection circuit including the clamp circuit of the present invention makes it possible to receive an electrical power without any loss even at a distance to which the power is barely supplied while positively restricting the peak output voltage of a rectifier/detector circuit, and hence to obtain a maximum communication reaching distance.

(3) Other Preferred Embodiments In the aforesaid preferred embodiment, the clamp circuit has a clamp circuit stage composed of bipolar transistors and a clamp circuit stage composed of MOS transistors, wherein both the clamp circuit stages are dependently connected to each other; however, the present invention is not restricted thereto, but can be widely applied to the case in which a plurality of clamp circuit stages composed of different element groups are dependently connected to each other.

According to the present invention, there is provided a clamp circuit in which a plurality of clamp circuit stages composed of different element groups are dependently connected to each other, wherein an influence applied by the surrounding circuits is accommodated by the clamp circuit stage hardly affected by the surrounding circuits, thereby generating necessary clamp voltage at both ends of the clamp circuit. With this configuration, it becomes possible to obtain a desired voltage without being affected by an interference from a rectifier/detector circuit and/or other surrounding circuits. Accordingly, the noncontact type information card using the overvoltage protection circuit including the clamp circuit of the present invention makes it possible to receive an electrical power without any loss even at a distance to which the power is barely supplied while positively restricting the peak output voltage of a rectifier/detector circuit, and hence to obtain a maximum communication reaching distance.

Claims

1. A clamp circuit comprising a plurality of clamp circuit stages composed of groups of different elements, which are dependently connected to each other, wherein clamp voltage compensation for characteristics of said clamp circuit stages are generated at both ends of said clamp circuit stages.

2. A clamp circuit according to claim 1, wherein said plurality of clamp circuit stages are composed of a combination a clamp circuit stage having a group of Darlington connected bi-polar transistors and a clamp circuit stage having a group of diode-connected uni-polar transistors which is connected in series to the clamp circuit stage having a group of Darlington connected bi-polar transistors.

3. A clamp circuit according to claim 2, wherein said clamp circuit stage having a group of Darlington connected bi-polar transistors is of a nesting layout structure in which each transistor is formed in sequence inside another transistor in dependent relation to the transistor and the bi-polar transistor with less current is located more inside the structure.

4. A non-contact type information card comprising: means for generating a voltage in correspondence with a variation in a magnetic field; a resonance circuit for passing a component of said voltage in a predetermined frequency band; means for detecting a signal passed through said resonance circuit; means for executing a predetermined processing in correspondence with an output of said detecting means; and an overvoltage protection circuit including a clamp circuit having a plurality of clamp circuit stages composed of groups of different elements which are dependently connected to each other, wherein when a high output current is outputted from a resonance circuit, part of an output current of said resonance circuit bypasses to said clamp circuit, thereby limiting a peak value of an output voltage to less than a predetermined value.

5. A non-contact type information card constructed and arranged to operate substantially as hereinbefore described with reference to and as illustrated in Figures 1 to 5 of the accompanying drawings.