GB2306021A

GB2306021A - Data acquisition system

Info

Publication number: GB2306021A
Application number: GB9520447A
Authority: GB
Inventors: Seamus Rispin; Edward Rispin; Ciaran Lynch; Francis Lynch
Original assignee: G D N ELECTRONICS Ltd
Current assignee: G D N ELECTRONICS Ltd
Priority date: 1995-10-04
Filing date: 1995-10-06
Publication date: 1997-04-23
Anticipated expiration: 2015-10-06
Also published as: GB9520447D0; GB2306021B; IES950774A2; IES66901B2

Abstract

A data acquisition system receives and stores a datastream from a monitored process via a datastore memory (10). A dataword generator using a memory array decode register (14), a step size shift register (15), a minimum shift register (16) and a maximum shift register (17) controls storage of datawords in the datastream into a memory array (20) where they are sorted using a memory sequencer (27) in response to data type. Sorted datawords stored in the memory array (20) are then transmitted to a secondary datastore for storage in a contiguous block of memory.

Description

"A data acquisition system" The present invention relates to a data acquisition system and more particularly to a data acquisition system for use with a computer system.

A variety of data acquisition systems are known for collecting data for processing by a computer. One system has a storage device for periodically receiving and storing process data relating to a monitored process locally which is subsequently retrieved and processed by a computer system. To accurately monitor the process, the volume of data is normally large, necessitating an equally large local memory device to accurately record all of the process data. Processing demands on the computer system are similarly high, particularly when results are required quickly and at irregular intervals to correct an error in the monitored process. An alternative is to dedicate one or more connected computer systems to continuously monitor a given process.As monitored processes are frequently distributed over a large geographical area skilled operators are required and the cost of such systems is often prohibitive. While reducing the amount of process data recorded will reduce system demands the efficiency of the system also suffers.

It is an object of the invention to provide an efficient data acquisition system which will overcome at least some of these problems.

Accordingly there is provided a data acquisition system of the type having a local storage device, for use with a computer system, the data acquisition system comprising: data reception means for receiving a datastream from a monitored process and storing the received datastream in a primary datastore; a dataword generator means for retrieving the stored datastream from the primary datastore as a plurality of thirty two bit datawords; an identifier for recognising a data type associated with each dataword; indexing means for sorting related datawords in response to the data type; and a secondary datastore for storing the related sorted datawords.

Thus, data storage costs are reduced by optimising use of local memory. Additionally, indexing related data words in this way minimises delays in retrieving related blocks of information when necessary to update process data from the monitored process.

Preferably the indexing means assigns a contiguous block of memory in the secondary datastore for related datawords.

Ideally the contiguous block of memory is assigned by a memory write enable circuit. In this way related datawords are stored together to reduce memory access time requirements.

In one arrangement, related datawords in the secondary datastore have a single common index. In this way, datawords may be added to the contiguous block and do not require a separate associated index identifier.

This significantly reduces the number of errors arising from erroneous sample values as out of range conditions are immediately noticed.

Preferably the dataword generator includes a shift register.

Ideally the dataword generator is provided by four eight bit shift registers connected in series thereby, providing the dataword generator in a simple and relatively inexpensive manner.

Preferably the identifier includes a memory array having a plurality of previously stored data types connected to the memory array. This allows for the ease of addition of a process variable to be monitored. The time taken to add monitored values to the process is significantly reduced and may be achieved by non specialist personnel.

Training in the use of the system is also significantly reduced due to this ease of use.

Ideally the indexing means includes a memory sequencer and associated control circuit connected to the memory array.

In one embodiment the memory sequencer is a bubble sort circuit connected to the memory array. Thus datawords may be easily added to a memory block and sorted relatively in a simple manner which ensures that they are accurately located without unnecessary complexity of the overall data acquisition system.

Preferably the control circuit includes as at least two latches connected to an adder.

Ideally the adder has an associated delay counter. Thus erroneous results are eliminated by configuring the delay counter to sample result data only after the delay associated with the delay counter has elapsed.

The invention will be more clearly understood from the following description thereof, given by way of example only with reference to the accompanying drawings in which: Fig. 1 is a diagrammatic view illustrating a data acquisition system according to the invention.

Referring to the drawing there is illustrated a data acquisition system according to the invention indicated generally by the reference numeral 1.

In broad outline the data acquisition system has a data reception means for receiving and storing a datastream provided by a datastore memory 10, a datastore decoder 11 and a memory controller 12. A dataword generator is provided by four eight bit shift registers connected in series namely, a memory array decode register 14, a step size shift register 15, a minimum shift register 16 and a maximum shift register 17. An identifier provided by a memory array 20 with a number of previously stored data types recognises a data type for each dataword.

The data words are sorted using a memory sequencer 27, in this case a bubble sort circuit in response to the recognised data type. The memory sequencer 27 has an associated control circuit connected to the memory array 20 provided by a step latch 21, a minimum latch 22 and a maximum latch 23 connected to an adder 24. The adder 24 is in turn connected to a delay counter 25 and a sum latch 26 to allow the adder result settling time.

Sorted datawords stored in the memory array 20 are then transmitted to the secondary datastore for storage in a contiguous block of memory. The secondary datastore receives the datawords on a memory array data output bus 180 upon receipt of a signal from the memory controller 12 and from an output gate 191 of a memory AND array 33 included in a memory write enable circuit. The memory write enable circuit has a shift register 29 connected to the memory array 20, a location register 30, a maximum register 31, a maximum latch 32 and a counter 34 to control the memory AND array 33.

In more detail the datastore memory 10 has a thirty two bit datastore output port 105 and receives an address control signal 104 from the datastore decoder 11. The memory controller 12 has an address output port 101 connected to the input port 102 of the datastore decoder 11 by a datastore address bus 103. The datastore memory 10 also has a thirty two bit datastore output port 105 connected to an input port 106 of the memory array decode register 14 by a thirty two bit databus 107. The memory controller 12 provides an enable signal 108 to a pulse generator 13 in turn providing a clock pulse 109 to the memory array decode register 14. A serial data line 111 is connected between the memory array decode register 14 and the memory array 20.The memory array decode register 14 also has a memory array decode register output port 112 connected to a step size shift register input port 113 of the step size shift register 15. The step size shift register 15 has a step serial data line 114 connected to a step latch input port 130. The step size shift register 15 receives a clock signal 115 and has a step size shift register output port 120 connected to a step minimum register input port 122 of the minimum shift register 16. The minimum shift register 16 provides an output on a minimum serial data line 123 in response to a clock signal 125 from the pulse generator 13.A minimum shift register output port 126 of the minimum shift register 16 is connected to the maximum shift register 17 through a maximum register input port 127 and the minimum shift register 16 has a maximum serial data line 128 and receives a clock signal 129 from the pulse generator 13.

The step latch 21 has a latch input port 130, the minimum latch 22 has a minimum latch input port 131 and the maximum latch 23 has a maximum latch input port 132.

The adder 24 has an input port 133 connected to a data line 134 for receiving data from the step latch 21 and an input port 136 connected to a data line 137 for receiving data from the minimum latch 22. The adder 24 is connected to the delay counter 25 by an adder output line 138 and the delay counter 25 is in turn connected to a sum latch input port 140 of the sum latch 26. The adder 24 has a sum input port 142 connected to the sum latch 26 by a databus 141.

The sum latch 26 is connected to a control AND gate 26 control bus 143 and the maximum latch 23 has an output port 144 connected to the same control AND gate 26 by a maximum control bus 145. The control AND gate 26 has an AND gate output pin 150 connected to the memory sequencer 27 through an active low input pin 151. The memory sequencer 27 has an array enable output pin 152 connected to the memory array 20 and a control enable output pin 154 for providing an enable signal 153. The enable signal 153 is connected to the minimum latch 22 and connected to the sum latch 26 through an inverter 158. The sum latch 26 has a databus 141 connected to the sum input port 142 of the adder 24 and a control bus 143 connected to the control AND gate 26.

The data acquisition system 1 has a start memory load input pin 160 connected to an AND gate 27 having an output pin 161. The output pin 161 is connected to a pulse generator 28 at an enable input pin 165 through an inverter 166 by a connector 167. The pulse generator 28 produces a pulse train 170 for actuating the memory shift register 29 to receive information on a memory location bus 171 through a data input port 172 connected to the memory array 20. The location register 30 receives information from a shift register output port 174 of the memory shift register 29 along a contents bus 175.

A databus 176 is connected between the memory shift register 29 and the maximum register 31 which is in turn connected to the maximum latch 32 by a memory maximum bus 177.

The memory AND array 33 receives information on a databus 178 from the maximum latch 32 and a location register 30 loads information into the counter 34 along a counter input line 179 for delivery to the AND array 33 as a counter output 190. The output gate 191 controls operation of the secondary storage and thus delivery of information from the memory array 20 to the memory array data output bus 180.

In use, a datastream is received from the external data monitoring device (not shown) and loaded into the datastore memory 10 through a thirty two bit datastore input port 100.

When all of the incoming datastream has been loaded, the memory controller 12 generates a datastore address at the address output port 101 for each thirty two bit dataword of the received datastream in turn and communicates the address of each word to the input port 102 of the datastore decoder 11 along the datastore address bus 103. Upon receipt of the datastore address the datastore decoder 11 generates the appropriate address control signal 104 to address the desired location in the datastore memory 10 and to place the contents of the addressed location on the thirty two bit datastore output port 105 of the datastore memory 10.

The contents of the location in the datastore memory 10 are thus passed to the input port 106 of the memory array decode register 14 along the thirty two bit databus 107.

The memory controller 12 generates the enable signal 108 to the pulse generator 13 which in turn provides the clock pulse 109 for the memory array decode register 14.

The clock pulse 109 allows the memory array decode register 14 to serially shift out the eight most significant bits of the contents of the memory array decode register 14 to the memory array 20 along the serial data line 111 and enable the memory array decode register output port 112. The dataword appearing at the memory array decode register output port 112 is read into the step size shift register 15 through the step size shift register input port 113 and bits twenty three to sixteen are shifted out serially along the step serial data line 114 upon receipt of the clock signal 115 from the pulse generator 13.The dataword appearing at the step size shift register output port 120 is read into the minimum shift register 16 through the step minimum register input port 122 and bits fifteen to eight are shifted out serially along the minimum serial data line 123 upon receipt of the clock signal 125 from the pulse generator 13. The dataword appearing at the minimum shift register output port 126 is read into the maximum shift register 17 through the maximum register input port 127 and bits seven to zero are shifted out serially along the maximum serial data line 128 upon receipt of the clock signal 129 from the pulse generator 13.

Each dataword from the received datastream is sequenced in turn within the memory array 20 by using the values in the step latch 21, the minimum latch 22 and the maximum latch 23. Data from the step serial data line 114 is read into the step latch 21 through the step latch input port 130. Data from the minimum serial data line 123 is read into the minimum latch 22 through the minimum latch input port 131 and data from the maximum serial data line 128 is read into the maximum latch 23 through the maximum latch input port 132.

The adder 24 first reads in a value from the step latch 21 through the input port 133 along the data line 134 and a value from the minimum latch 22 through the input port 136 along the data line 137. The values at the input port 133 and the input port 136 are then added and the sum loaded into the delay counter 25 along the adder output line 138. The delay counter 25 times out in two milliseconds before the value in the delay counter 25 is refreshed from the adder 24 thus preventing erroneous intermediate error results from being loaded into the memory array 20. The value in the delay counter 25 is then loaded into the sum latch 26 through the sum latch input port 140. The contents of the sum latch 26 received through the input port 140 is then returned to the sum input port 142 of the adder 24 along the databus 141 and to the control AND gate 26 along the control bus 143.The contents of the maximum latch 23 are connected to the AND gate 26 through the output port 144 on the maximum control bus 145.

When the AND gate 26 produces a logic zero on the AND gate output pin 150, indicating that the value on the control bus 143 and the value on the maximum control bus 145 are not the same and thus that the maximum value has not been reached the memory sequencer 27 is enabled by receiving the logic zero at the active low input pin 151. The memory sequencer 27 in turn provides a validation signal at the array enable output pin 152 to reserve a memory location in the memory array 20 to receive the next dataword from the datastore memory 10.

The memory sequencer 27 also provides an enable signal 153 through the control enable output pin 154 to enable the sum latch 26 and disable the minimum latch 22 through the inverter 158. The adder 24 then adds the value on the databus 141 to the value on the input port 133 as the minimum latch is disabled and the new value is placed on the control bus 143 and logically anded with the value on the maximum control bus 145 by the AND gate 26 as before.

When the AND gate 26 produces a logic one at the AND gate output pin 150 the memory sequencer 27 is disabled there by disabling the memory array 20 and the memory controller 12 through the AND gate 27. The memory controller 12 may also be disabled at any time during the processing of the received datastream by removing the logic one from the start memory load input pin 160, thereby producing a logic zero on the output pin 161 of the AND gate 27.

When a logic zero is provided on the output pin 161 of the AND gate 27 the pulse generator 28 is enabled by receiving a logic one at the enable input pin 165, the logic one being provided by the output of the inverter 166 connected to the output pin 161 by the connector 167. The enabled pulse generator 28 delivers a pulse train 170 to the memory read shift register 29 to read in the memory locations from the memory array 20 supplied on the memory location bus 171 through the data input port 172. The sixteen most significant bits of the memory location bus 171 are shifted out into the location register 30 through the shift register output port 174 and along the contents bus 175. The sixteen least significant bits are communicated along the databus 176 and received by the max register 31. The maximum register 31 passes the sixteen least significant bits to the maximum latch 32 along the memory maximum bus 177 where the value is held and maintained as one input to the memory AND array 33 on the databus 178.

The contents of the location register 30 are passed to the counter 34 along the counter input line 179. The contents of each of the memory locations are transmitted to the address decoder (not shown) through the memory array data output bus 180 until the values presented to the AND array 33 namely the value on the memory maximum bus 177 and the value on the output 190 of the counter 34 are the same producing a logic one at the output pin 191 of the AND array 33.

The embodiment described above would be particularly useful for real time monitoring of production information in a manufacturing site. The data acquisition system receives and processes a datastream and communicates results with a secondary datastore.

The secondary datastore is provided in this case by a fixed disk and associated controller of personal computer which has been omitted so as to facilitate understanding of the present invention, however it will be appreciated that the system may equally be configured with a local secondary datastore and used for batch processing of results. The functionality of components described below may also be combined and may include one or more software routines to provide compatibility with a given computer system without departing from the spirit of the invention.

It will be appreciated that the data acquisition system described provides an efficient and cost effective method of monitoring a given process by intelligently sorted related data from the monitored process. This is particularly useful for smaller organisations involved in procedures leading to and arising from the implementation of international quality standards such as ISO 9000. Similarly it aids the monitoring of data gathered as a result of implementing the inspection plans and sampling such as DIN 40080, MIL-STD 105E and BS 6001.

It will be noted that the secondary storage may be of any suitable type for example it may be provided by a fixed disk in a personal computer connected directly or by any form of data link and it may also be provided by portion of the primary data store. It is envisaged that the components used may be of any suitable type conducted either in hardware or software. Further, it is envisaged that the apparatus described may easily be modified for use in 16 bit operations as the number of bits in each dataword may be easily changed and the components changed accordingly. Devices, used may be combined to incorporate the functionality of a number or all of the components described using VLSI techniques or application specific integrated circuits and may be provided by a microcontroller having associated internal or external software routines where appropriate.

It will also be noted that the above description does not refer to specific devices or timing and performance details as they have been omitted in order not to unnecessarily obscure an understanding of the present invention and that any suitable arrangement may be used.

The invention is not limited to the embodiments hereinbefore described, which may be varied in both construction and detail.

Claims

1. A data acquisition system of the type having a

local storage device, for use with a computer system, the data acquisition system comprising: data reception means for receiving a datastream from a monitored process and storing the received datastream in a primary datastore; a dataword generator means for retrieving the stored datastream from the primary datastore as a plurality of thirty two bit datawords; an identifier for recognising a data type associated with each dataword; indexing means for sorting related datawords in response to the data type; and a secondary datastore for storing the related sorted datawords.

2. A data acquisition system as claimed in claim 1 wherein the indexing means assigns a contiguous block of memory in the secondary datastore for related datawords.

3. A data acquisition system as claimed in claim 2 wherein the contiguous block of memory is assigned by a memory write enable circuit.

4. A data acquisition system as claimed in any preceding claim wherein related datawords in the secondary datastore have a single common index.

5. A data acquisition system as claimed in any preceding claim wherein the dataword generator includes a shift register.

6. A data acquisition system as claimed in any of claims one to 4 wherein the dataword generator is provided by four eight bit shift registers connected in series.

7. A data acquisition system as claimed in any preceding claim wherein the identifier includes a memory array having a plurality of previously stored data types connected to the memory array.

8. A data acquisition system as claimed in claim 7 wherein the indexing means includes a memory sequencer and associated control circuit connected to the memory array.

9. A data acquisition system as claimed in claim 8 wherein the memory sequencer is a bubble sort circuit connected to the memory array.

10. A data acquisition system as claimed in claim 8 or claim 9 wherein the control circuit includes as at least two latches connected to an adder.

11. A data acquisition system as claimed in claim 10 wherein the adder has an associated delay counter.

12. A data acquisition system as claimed in any preceding claim substantially as described herein with reference to the accompanying drawing.