GB2305581A

GB2305581A - Detecting completion of carrier recovery and symbol timing recovery

Info

Publication number: GB2305581A
Application number: GB9615629A
Authority: GB
Inventors: Dong-Seog Han
Original assignee: Samsung Electronics Co Ltd
Current assignee: Samsung Electronics Co Ltd
Priority date: 1995-09-23
Filing date: 1996-07-25
Publication date: 1997-04-09
Anticipated expiration: 2016-07-25
Also published as: CN1147742A; GB9615629D0; US5818544A; KR970019680A; JPH09130690A; JP3154664B2; CN1078033C; KR0170690B1; GB2305581B; GB2305581B8

Abstract

A circuit for detecting the completion of carrier recovery and symbol timing recovery in a receiver (e.g. a high definition television) comprises a DC offset estimator 130 and a detection signal generator 150. The DC offset estimator calculates the average of a number of received symbol values and provides a signal representing the average to the detection signal generator which determines completion of carrier recovery by comparing the average signal with a threshold. The detection signal generator further determines completion of symbol timing recovery by calculating the difference between successive average signals supplied by the DC offset estimator and comparing this difference with a further threshold. Following detection of completion of carrier recovery and symbol timing recovery, the detection signal generator provides an enabling signal to equaliser 160 to allow further processing of received signals to proceed.

Description

CTRCUIT FOR DETECTING COMPLETION OF CARRIER RECOVERY AND SYMBOL TIMING RECOVERY. METHOD THEREOF. AND HIGH DEFINITION TELEVISION ADOPTING TE SAME The present invention relates to a circuit for detecting the completion of carrier recovery and symbol timing recovery, and a method thereof, and a high definition television (HDTV) adopting the same, and more particularly, to a circuit for detecting the completion of carrier recovery and symbol timing recovery, and a method thereof, which enables stable operation within a short time period in an HDTV receiver.

For years, there has been much effort in the development of a television having a large screen and high resolution. As a result of this development, the first high definition television broadcasts, based on multiple sub-Nyquist sampling encoding (MUSE) in an analog transmission mode, are in service in Japan.

In the United States, the Grand Alliance (GA) committee have proposed technical standards for the HDTV system. The GA committee has adopted vestigial side band (VSB) modulation as a GA-HDTV modulation standard.

Specifically, 8-VSB using eight levels and 16-VSB using sixteen levels have been adopted for terrestrial broadcast mode and high speed cable mode, respectively, as modulation standards in the GA-HDTV.

Figure 1 is a schematic block diagram of a conventional HDTV proposed by the GA committee. In Figure 1, a tuner 102 selects an intended TV channel signal received from an antenna. Generally, the output of the tuner 102 is a modulated HDTV signal whose central frequency is 44MHz and whose bandwidth is 6MHz.

However, the output of the tuner 102 includes the signal of adjacent channels instead of passing the intended HDTV signal of 6 MHZ bandwidth due to the non-ideal characteristics of the inner filter of the tuner 102. Since the signal of the adjacent channels causes interference with respect to the signal of the intended channel, the output of the tuner 102 is filtered by a surface acoustic wave (SAW) filter 104 whose bandwidth is exactly 6MHz.

An intermediate frequency (H:) amplifier 106 maintains the input of an analog-to-digital (AID) converter 110 at a proper level. The gain of the IF amplifier 106 is controlled in response to an automatic gain control (AGC) signal output from an AGC circuit 114. Here, the proper levels are -5.75, -3.75, -175, 0.25, 2.25, 4.25, 6.25 and 8.25 obtained by adding a DC offset, 1.25, to the 8-levels of fl, i3, iS, f7.

Also, the tuner 102 includes a radio frequency (RF) amplifier. If the gain of the IF amplifier 106 is not sufficient, the RF amplifier amplifies the received signal responding to the AGC signal output from the AGC circuit 114.

On the other hand, the first operation after applying power to the HDTV receiver should completely recover the carrier by precisely controlling the synchronization frequency of the tuner 102. A frequency and phase locked loop (FPLL) circuit 108 performs the carrier recovery by tracking a pilot signal present in the output signal of the IF amplifier 106 and adjusting the local oscillation frequency of the tuner 102 so that the pilot signal exists at a frequency of OHz.

The output of the IF amplifier 106 is then multiplied by the recovered carrier, thereby being demodulated to be a baseband signal.

The AID converter 110 converts the output of the FPLL circuit 108 into digital data according to a symbol clock signal recovered in a symbol clock recovery circuit 112. The symbol clock recovery circuit 112 is called a symbol timing recovery circuit. The symbol clock recovery circuit 112 estimates the sampling point of the A/D converter 110 and generates the operation clock signal of the whole system.

A DC offset remover 116 removes the DC offset, which results from the pilot signal and the non-linearity of the A/D converter 110, from the converted digital data. As the signal is transmitted, a small digital DC level of 1.25 is added to symbol data segment sync having the signal levels such as +5, -5, -5 and +5 and to 832-symbol data having a randomized level among 8 levels including i 1, i3, i5 and f7 before the transmission. This provides an effect of adding the pilot signal to the data signal. Also, the A/D converter 110 in Figure 1 shows non-linear characteristics. Thus, the receiver should remove the DC offset of 1.25 by the pilot signal and the DC offset generated by the non-linearity of the AID converter 110 in order to recover the original signal level.The DC offset remover 116 detects the average DC offset of field sync data, and subtracts the detected average DC offset from the output of the AID converter 110, thereby removing the DC offset.

Here, as shown in Figure 2, the HDTV data frame is comprised of two fields, each of which is composed of one field sync segment and 312 data segments. Each data segment is composed of 832 data accompanying the 4symbol segment sync pulse. That is, as shown in Figure 3, one data segment is composed of 836 symbols including the 832 symbols (including data and forward-error-correction (FEC)) and the data segment sync pulse of 4 symbols. The data segment sync pulse is inserted into a 8-level digital data stream at the start of each data segment. Here, the data segment sync pulse is composed of a predetermined pattern of 4 symbols such as +5, -5, -5 and +5, and the remaining data is composed of randomized signals.

In the field sync segment of each field shown in Figure 2, a reference field sync signal is recorded with respect to all 511 symbols. The reference field sync signal of the first and second field sync segments FIELD SYNC &num;1 and FIELD SYNC &num;2 have the same absolute values but the signs thereof are different from each other. Since the DC offset of 1.25 is added to the reference field sync signal, the average of the first and the second reference field sync signals becomes the DC offset. The DC offset remover 116 calculates the average value.

An equalizer 118 removes the multi-path distortion. This multi-path distortion is due to the multi-path channel transmission caused by the reflection of electromagnetic waves from the landscape, buildings and airplanes for the case of a terrestrial broadcast. The multi-path distortion results in images being overlapped with others which are delayed and attenuated with respect to the image of the original signal, and distorts the frequency characteristics of the HDTV signal.

A phase tracking loop (put) 120 corrects the phase error which was not completely eliminated by the FPLL 108.

On the other hand, before being transmitted, the signal is coded by Reed Solomon (RS) coding, interleaving and Trellis coded modulation (TCM) to reduce the symbol error generated during the transmission. A channel decoder 122 decodes the coded signal. The channel decoder 122 Trellisdemodulates the output of PTL 120 and de-interleaves the Trellis-decoded data. Since the de-interleaved data is product-coded using the RS code, a signal processing of error-correction decoding the product-coded data using the parity is performed.

A source decoder 124 variable-length-decodes the error-correction decoded data output from the channel decoder 122 and inverse-quantizes the variable-length decoded data. Also, the source decoder 124 performs an inverse discrete cosine transform (IDCT) with respect to the inverse-quantized data according to the quantization step size used during the encoding process and recovers the compressed data into the original data, and then displays the results in a display 126.

According to the operational sequence of each block of the above described transmitter, the first step should be the completion of the recovery of the carrier. Then, the symbol timing is recovered by the symbol clock recovery circuit. Thereafter, the remaining blocks such as the equalizer operate in sequence.

Therefore, in order to bring the transmitter to normal operation within a short period of time, it is desirable for the equalizer and the following blocks to operate when both carrier recovery and the symbol timing recovery are completed. That is, according to the conventional HDTV receiver shown in Figure 1 where all blocks begin simultaneous operation just after the power is applied thereto, even if the correct data is input to the equalizer after completion of the carrier recovery and symbol timing recovery, it will take some time for the equalizer and the following blocks to reach normal operating conditions from the transient malfunction. In a worse case, the time required for the equalizer and the following blocks to reach normal operating conditions may be longer than that which is required for the carrier recovery and symbol timing recovery.

Therefore, an apparatus for detecting whether both carrier recovery and symbol timing recovery are completed is required.

The first aim of embodiments of the present invention is to provide a circuit for detecting the completion of carrier recovery and symbol timing recovery for a signal receiver to reach normal operating conditions within a short time period.

The second aim of embodiments of the present invention is to provide an HDTV having the function of detecting the completion of carrier recovery and symbol timing recovery.

The third aim of embodiments of the present invention is to provide a method of detecting the completion of carrier recovery and symbol timing recovery for a signal receiver to reach a normal operation condition within a short time period.

According to a first aspect of the invention, there is provided a circuit for detecting the completion of carrier recovery and symbol timing recovery, included in a receiver in which a carrier of a received signal is recovered, the received signal is demodulated into a baseband signal using the recovered carrier, a symbol timing of the demodulated signal is recovered, the demodulated signal is equalized according to the recovered symbol timing, and the equalized signal is decoded, comprising: estimating means for calculating an average of the demodulated signals in a predetermined symbol unit and outputting the average as a DC estimation value; first detection means for detecting the completion of the carrier recovery in response to the DC estimation value; second detection means for detecting the completion of the symbol timing recovery in response to the difference between two consecutive DC estimation values; and generating means for generating an operation control signal, in response to the outputs of the first and second detection means, for controlling equalization of the demodulated signal and decoding.

Preferably, said first detection means is comprised of a first comparator for comparing said DC estimation value with a first threshold value and outputting a first comparison signal representing whether the carrier recovery is completed.

Preferably, said second detection means comprises: a delay for delaying said DC estimation value by a predetermined symbol period; a subtracter for subtracting the DC estimation value output from said delay from the current DC estimation value output from said estimating means; and a second comparator for comparing the output of said subtracter with a second threshold value and outputting a second comparison signal representing whether the symbol timing recovery is completed.

According to a second aspect of the invention, there is provided a high definition television (HDTV) comprising: a tuner for selecting an intended channel signal from a received HDTV signal; an intermediate frequency (IF) amplifier for amplifying the output of the tuner; a frequency and phase locked loop (FPLL) circuit for recovering a carrier by tracking a pilot signal present in the output signal of the IF amplifier, and demodulating the output signal of the IF amplifier into a baseband signal using the recovered carrier; an analogto-digital (A/D) converter for converting the output signal of the FPLL circuit into a digital signal; a symbol clock recovery circuit for restoring a symbol clock from the output of the AID converter and estimating a point of sampling time of the A/D converter; a DC offset remover for calculating the average of the outputs of the A/D converter in a predetermined symbol unit as a DC estimation value and subtracting the obtained DC estimation value from the output of the A/D converter, thereby removing the DC offset; a detection signal generator for generating a detection signal representing whether the carrier recovery and the symbol timing recovery are completed in response to the DC estimation value and a difference of two consecutive DC estimation values; an equalizer for equalizing the output of the offset remover according to the detection signal; a phase tracking loop (PTL) circuit for correcting a phase error of the output of the equalizer which is not completely eliminated by the FPLL circuit; a channel decoder for Trellis-decoding the output of the PTL circuit and error-correction-decoding the Trellis-decoded data; and a source decoder for expanding the error-correction-decoded data.

Preferably, said DC offset remover comprises: a DC offset estimator for calculating the average of the outputs from said AID converter in a predetermined symbol unit and outputting the average as a DC estimation value; and a subtracter for subtracting said DC estimation value from the output of said A/D converter.

Said detection signal generator preferably comprises: a first comparison circuit for comparing said DC estimation value with a first threshold value and outputting a first comparison signal which represents whether the carrier recovery is completed; a second comparison circuit for comparing the difference between two consecutive DC estimation values with a second threshold value and outputting a second comparison signal which represents whether the symbol timing recovery is completed; and a logic AND gate for generating a detection signal which enables said equalizer when both said first and second comparison signals are present.

Said second comparison circuit may comprise: a delay for delaying said DC estimation value for the predetermined symbol period; a subtracter for subtracting the DC estimation value delayed by said delay from the current DC estimation value output from said DC offset estimator; an absolute circuit for calculating the absolute value of the output from said subtracter; and a comparator for comparing the output of said absolute circuit with a second threshold value and outputting a second comparison signal which represents whether the symbol timing recovery is completed.

The television preferably further comprises an automatic gain control (AGC) circuit for generating an AGC signal in response to the output of said A/D converter and outputting the AGC signal to said tuner and said IF amplifier.

According to a third aspect of the invention, there is provided a high definition television comprising: a tuner for selecting an intended channel signal from a received HDTV signal; an intermediate frequency (IF) amplifier for amplifying the output of said tuner; an analog-to-digital (A/D) converter for converting the output signal of said IF amplifier into a digital signal; a digital frequency and phase locked loop (DFPLL) circuit for recovering a carrier using a pilot signal included in the data output from said A/D converter and demodulating the output signal of said A/D converter into a baseband signal using the recovered carrier; a symbol clock signal recovery circuit for restoring a symbol clock signal from the output of said DFPLL circuit and estimating a point of sampling time of said A/D converter;; a DC offset remover for calculating the average of the outputs of said DFPLL circuit in a predetermined symbol unit as a DC estimation value and subtracting the obtained DC estimation value from the output of said DFPLL circuit, thereby removing the DC offset; a detection signal generator for generating a detection signal representing whether the completion of the carrier recovery and the symbol timing recovery are completed in response to said DC estimation value and a difference of two consecutive DC estimation values; an equalizer for equalizing the output of said DFPLL circuit according to said detection signal; a phase tracking loop (PTL) circuit for correcting a phase error of the output of said equalizer which is not completely eliminated by said DFPLL circuit; a channel decoder for Trellis-decoding the output of said PTL circuit and error-correction-decoding the Trellis-decoded data; and a source decoder for expanding said error-correction-decoded data.

Preferably, said offset remover comprises: a DC offset estimator for calculating the average of the outputs from said DFPLL circuit in a predetermined symbol unit and outputting the average as a DC estimation value; and a subtracter for subtracting said DC estimation value from the output of said DFPLL circuit.

Said second comparison circuit preferably comprises: a delay for delaying said DC estimation value for the predetermined symbol period; a subtracter for subtracting the DC estimation value delayed by said delay from the current DC estimation value output from said DC offset estimator; an absolute circuit for calculating the absolute value of the output from said subtracter; and a comparator for comparing the output of said absolute circuit with a second threshold value and outputting a second comparison signal which represents whether the symbol timing recovery is completed.

Preferably, the television further comprises an automatic gain control (AGC) circuit for generating an AGC signal in response to the output of said DFPLL circuit and outputting the AGC signal to said tuner and said IF amplifier.

According to a fourth aspect of the invention, there is provided a method of detecting the completion of carrier recovery and symbol timing recovery, by signal processing in a receiver in which a carrier of a received signal is recovered, the received signal is demodulated into a baseband signal using the recovered carrier, a symbol timing of the demodulated signal is recovered, the demodulated signal is equalized according to the recovered symbol timing, and the equalized signal is decoded, the detecting method comprising the steps of: (a) estimating a DC estimation value by calculating the average of the demodulated signals in a predetermined symbol unit; (b) generating a first detection signal which represents whether the carrier recovery is completed, in response to the DC estimation value; (c) generating a second detection signal which represents whether the carrier recovery is completed, in response to a difference between two consecutive DC estimation values; and (d) generating an operation control signal for controlling equalization and decoding of the demodulated signal, in response to the first and second detection signals generated in steps (b) and (c).

For a better understanding of the invention, and to show how embodiments of the same may be carried into effect, reference will now be made, by way of example, to the accompanying diagrammatic drawings, in which: Figure 1 is a schematic block diagram of a conventional HDTV; Figure 2 is a diagram showing the structure of an HDTV data frame; Figure 3 is a diagram showing the structure of an HDTV data segment; Figure 4 is a schematic block diagram of the HDTV according to a preferred embodiment of the present invention; Figure 5 is a diagram showing the constellation of an 8-level VSB transmission signals; Figure 6 is a scattering plot of the VSB transmission signal in an unlocked frequency state; Figure 7 is a circuit diagram of the detection signal generator shown in Figure 4; and Figure 8 is a schematic block diagram of the HDTV according to another preferred embodiment of the present invention.

Referring to Figure 4, the structure and operation of the HDTV according to the present invention will be described. Here, the same reference numerals are designated for structures that are the same as those shown in Figure 1 and the description and the operation thereof will be omitted. Thus, the HDTV according to the present invention will be described focusing on the structure in a portion A, which is different from the conventional HDTV shown in Figure 1.

In Figure 4, a DC offset estimator 130 calculates the average of a predetermined number N of symbols, and outputs a DC frequency offset estimation value or DC estimation value DC EST to a DC offset remover 140 and a carrier and symbol timing recovery completion detection signal generator 150 (hereinafter is called 1detection signal generator"). Also, the DC offset estimator 130 outputs a clock signal CLK having period of N symbol to the detection signal generator 150.

The DC offset remover 140 is composed of a subtracter which subtracts the estimation value DC EST from the output of the A/D converter 110, thereby removing the DC offset.

The detection signal generator 150 generates a recovery completion detection signal (hereinafter is called "detection signal") responding to the estimation value DC EST and the clock signal CLK.

An equalizer 160 operates responding to the detection signal generated from the detection signal generator 150. Thereafter, the following blocks operate.

Here, the DC offset estimator 130 may be included in the the DC offset remover 140 or in the detection signal generator 150.

Figure 5 shows the constellation of 8-level VSB transmission signals in a complex plane in the normal state. The original 8-level VSB signal has eight levels, -7, -5, -1, 1, 3, 5 and 7, to which a DC value of 1.25 is added to make a signal having the levels -5.75, -3.75, 75 -1.75, -1.75,0.25,2.25,4.25, 6.25 or 8.25, as shown in Figure 5. In reality, the VSB receiver processes only the real number component of a signal rather than a complex signal. In Figure 5, the output of the AID converter 110 is represented as a complex signal after Hilbert transform.

If the carrier is not precisely recovered and there is a frequency error, the average of the estimated DC values of the received signal is close to zero, because the complex frequency of the VSB transmitted signal is scattered around the origin so that the axis of coordinates can continuously rotate in an arbitrary direction, as shown in Figure 6. Thus, the average value is near to zero.

When the carrier is recovered, the DC level of the received signal is close to 1.25. Also, when the symbol timing recovery is completed, the change of the DC level will be very small. Taking this into account, the detection signal generator 150 is constructed as shown in Figure 7.

Figure 7 is a circuit diagram of the detection signal generator shown in Figure 4. In Figure 7, the input port of the DC offset estimator 130 is connected to the output port of the AID converter 110 shown in Figure 4, and the output port is connected to the input port of the DC offset remover 140 shown in Figure 4.

The detection signal generator 150 comprises a first comparator 151 whose first input port X and clock port are connected to the data output port and the clock output port of the DC offset estimator 130, respectively, and whose second input port Y receives a first threshold value; a unit delay 152 whose input port and clock port are connected to the data output port and the clock output port of the DC offset estimator 130, respectively; a subtracter 153 whose minuend port and clock port are connected to the data output port and the clock output port of the DC offset estimator 130, respectively, and whose subtrahend port is connected to the output port of the unit delay 152; an absolute circuit 154 whose input port is connected to the output port of the subtracter 153 and whose clock port is connected to the clock output port of the DC offset estimator 130; a second comparator 155 whose first input port X is connected to the output port of the absolute circuit 154, whose second input port Y receives a second threshold value, and whose clock port is connected to the clock output port of the DC offset estimator 130; and a logic AND gate 156 whose first and second input ports are connected to the output ports of the first and second comparators 151 and 155 and whose output port is connected to the enable port of an equalizer 160.

The circuit shown in Figure 7 operates as follows. The DC offset estimator 130 calculates the average of N symbols output from the A/D converter 110 and outputs the average as a DC estimation value DC EST.

Whenever a new average DC EST is output, a clock signal CLK having a period of N symbols is also output.

The first comparator 151, which determines whether the carrier is completely recovered, outputs a "1" if the estimation value DC EST value output from the DC offset estimator 130 is greater than the first threshold value and outputs a "0" otherwise. The output of "1" from the first comparator 151 means that the carrier is completely recovered in the FPLL circuit 108 shown in Figure 4. That is, if the carrier is not recovered sufficiently, the average DC offset will be almost "0" as shown in the scattering plot of Figure 6. On the contrary, if the carrier is completely recovered, each of the DC offset level approaches 1.25 as shown in Figure 5. Here, the first threshold value may be set at a value which is greater than 0 and less than 1.25.

The unit delay 152 delays the estimation value DC EST output from the DC offset estimator 130 according to the clock signal CLK having a period of N symbol and then outputs the delayed DC estimation value to the subtrahend port of the subtracter 153.

The subtracter 153 subtracts the DC estimation value which is delayed by the unit delay 152 from estimation value DC EST input to the minuend port according to CLK.

The absolute circuit 154 calculates the absolute value of the output of the subtracter 153 according to the CLK and then outputs the absolute value to first input port X of the second comparator 155.

The second comparator 155, which determines whether the symbol timing recovery is completely performed, outputs a "1" if the difference between two consecutive estimation values DC EST's is less than the second threshold value and outputs a "0" otherwise. The output of "1" from the second comparator 155 means that the symbol clock recovery is completely performed by the symbol clock recovery circuit 112 shown in Figure 4. That is, when the symbol clock is recovered, timing errors decrease so that the difference between the estimation values DC EST's decreases.

In short, if the carrier is not recovered, the DC offset is "0", and if the carrier is completely recovered, i.e., the frequency is locked, a DC offset value is generated. As the frequency is being locked, the timing error decreases. Finally, when the symbol timing is recovered, the DC offset value very slightly changes.

If both the outputs of the first and second comparators 151 and 152 are "1", the output of the logic AND gate 156 becomes "1." This leads to a detection signal, representing the completion of the carrier recovery and the symbol timing recovery, being output to the enable port of the equalizer 118 shown in Figure 4. On reception of the detection signal, the equalizer 118 starts to operate, and the remaining blocks operate according to the operation of the equalizer 118.

Figure 8 is a schematic block diagram of the HDTV according to another preferred embodiment of the present invention. Here, the same reference numerals are designated for structures that are the same as those shown in Figure 4 and the description and the operation thereof will be omitted.

Thus, the HDTV shown in Figure 8 will be described focusing on the structure in a portion B, which is different from the HDTV shown in Figure 4.

In Figure 8, an A/D converter 170 converts the amplified IF signal output from the IF amplifier 106 into a digital signal. A digital frequency and phase locked loop (DFPLL) 188 recovers the carrier using a pilot signal included in the data output from the A/D converter 170, and multiplies the output data of the A/D converter 170 by the recovered carrier, thereby extracting a baseband data.

A matched filter 190 minimizes interference between symbols when a multipath does not exist for maximizing the energy of data output from the DFPLL 188.

The symbol clock recovery circuit 200 recovers the symbol clock signal, and the AID converter 170 samples the data according to the recovered symbol clocksignal.

The AGC 210 generates the AGC signal in response to the amplitude of the output signal of the matched filter 190 and then outputs the AGC signal to the tuner 102 and the IF amplifier 106. In the IF amplifier 106, the gain is controlled responding to the AGC signal output from the AGC 210 so that the signal level input to the matched filter 190 is maintained properly. Also, if the gain of the IF amplifier is not sufficient, an internal RF amplifier of the tuner 102 further amplifies the signal responding to the AGC signal.

The output of the matched filter 190 is input to the DC offset estimator 130 and the DC offset remover 140. The operations of the blocks following the DC offset estimator 130 and the DC offset remover 140 are the same as those described with reference to Figure 4.

In the above description of the present invention, the HDTV receiving an 8-level VSB signal was described as an example. However, the scope of the present invention is not limited to the particular forms illustrated.

As described above, according to the HDTV of the present invention, the completion of the carrier recovery and the symbol timing recovery is detected based on the fact that the DC offset is generated when the carrier is recovered and the offset is slightly changed when the symbol timing is recovered, and then the equalizer and the remaining blocks are enabled.

Thus, normal operation can be conducted within a short time period.

The reader's attention is directed to all papers and documents which are filed concurrently with or previous to this specification in connection with this application and which are open to public inspection with this specification, and the contents of all such papers and documents are incorporated herein by reference.

All of the features disclosed in this specification (including any accompanying claims, abstract and drawings), and/or all of the steps of any method or process so disclosed, may be combined in any combination, except combinations where at least some of such features and/or steps are mutually exclusive.

Each feature disclosed in this specification (including any accompanying claims, abstract and drawings), may be replaced by alternative features serving the same, equivalent or similar purpose, unless expressly stated otherwise. Thus, unless expressly stated otherwise, each feature disclosed is one example only of a generic series of equivalent or similar features.

The invention is not restricted to the details of the foregoing embodiment(s). The invention extends to any novel one, or any novel combination, of the features disclosed in this specification (including any accompanying claims, abstract and drawings), or to any novel one, or any novel combination, of the steps of any method or process so disclosed.

Claims

1. A circuit for detecting the completion of carrier recovery and symbol timing recovery, included in a receiver in which a carrier of a received signal is recovered, the received signal is demodulated into a baseband signal using said recovered carrier, a symbol timing of said demodulated signal is recovered, said demodulated signal is equalized according to said recovered symbol timing, and the equalized signal is decoded, the circuit comprising: estimating means for calculating an average of said demodulated signals in a predetermined symbol unit and outputting the average as a DC estimation value; first detection means for detecting the completion of the carrier recovery in response to said DC estimation value; second detection means for detecting the completion of the symbol timing recovery in response to the difference between two consecutive DC estimation values; and generating means for generating an operation control signal, in response to the outputs of said first and second detection means, for controlling equalization of said demodulated signal and decoding.

2. A circuit for detecting the completion of carrier recovery and symbol timing recovery as claimed in claim 1, wherein said first detection means is comprised of a first comparator for comparing said DC estimation value with a first threshold value and outputting a first comparison signal representing whether the carrier recovery is completed.

3. A circuit for detecting the completion of carrier recovery and symbol timing recovery as claimed in claim 1 or 2, wherein said second detection means comprises: a delay for delaying said DC estimation value by a predetermined symbol period; a subtracter for subtracting the DC estimation value output from said delay from the current DC estimation value output from said estimating means; and a second comparator for comparing the output of said subtracter with a second threshold value and outputting a second comparison signal representing whether the symbol timing recovery is completed.

4. A high definition television (HDTV) comprising: a tuner for selecting an intended channel signal from a received HDTV signal; an intermediate frequency (IF) amplifier for amplifying the output of said tuner; a frequency and phase locked loop (FPLL) circuit for recovering a carrier by tracking a pilot signal present in the output signal of said IF amplifier, and demodulating the output signal of said IF amplifier into a baseband signal using said recovered carrier; an analog-to-digital (A/D) converter for converting the output signal of said FPLL circuit into a digital signal; a symbol clock signal recovery circuit for restoring a symbol clock signal from the output of said AID converter and estimating a point of sampling time of said A/D converter;; a DC offset remover for calculating the average of the outputs of said AID converter in a predetermined symbol unit as a DC estimation value and subtracting the obtained DC estimation value from the output of said A/D converter, thereby removing the DC offset; a detection signal generator for generating a detection signal representing whether the carrier recovery and the symbol timing recovery are completed in response to said DC estimation value and a difference of two consecutive DC estimation values; an equalizer for equalizing the output of said offset remover according to said detection signal; a phase tracking loop (PTL) circuit for correcting a phase error of the output of said equalizer which is not completely eliminated by said FPLL circuit;; a channel decoder for Trellis-decoding the output of said PTL circuit and error-correction-decoding the Trellis-decoded data; and a source decoder for expanding said error-correction-decoded data.

5. A high definition television as claimed in claim 4, wherein said DC offset remover comprises: a DC offset estimator for calculating the average of the outputs from said A/D converter in a predetermined symbol unit and outputting the average as a DC estimation value; and a subtracter for subtracting said DC estimation value from the output of said A/D converter.

6. A high definition television as claimed in claim 4 or 5, wherein said detection signal generator comprises: a first comparison circuit for comparing said DC estimation value with a first threshold value and outputting a first comparison signal which represents whether the carrier recovery is completed; a second comparison circuit for comparing the difference between two consecutive DC estimation values with a second threshold value and outputting a second comparison signal which represents whether the symbol timing recovery is completed; and a logic AND gate for generating a detection signal which enables said equalizer when both said first and second comparison signals are present.

7. A high definition television as claimed in claim 6, wherein said second comparison circuit comprises: a delay for delaying said DC estimation value for the predetermined symbol period; a subtracter for subtracting the DC estimation value delayed by said delay from the current DC estimation value output from said DC offset estimator; an absolute circuit for calculating the absolute value of the output from said subtracter; and a comparator for comparing the output of said absolute circuit with a second threshold value and outputting a second comparison signal which represents whether the symbol timing recovery is completed.

8. A high definition television as claimed in claim 4, 5, 6 or 7, further comprising an automatic gain control (AGC) circuit for generating an AGC signal in response to the output of said A/D converter and outputting the AGC signal to said tuner and said IF amplifier.

9. A high definition television comprising: a tuner for selecting an intended channel signal from a received HDTV signal; an intermediate frequency (IF) amplifier for amplifying the output of said tuner; an analog-to-digital (A/D) converter for converting the output signal of said IF amplifier into a digital signal; a digital frequency and phase locked loop (DFPLL) circuit for recovering a carrier using a pilot signal included in the data output from said A/D converter and demodulating the output signal of said A/D converter into a baseband signal using the recovered carrier; a symbol clock signal recovery circuit for restoring a symbol clock signal from the output of said DFPLL circuit and estimating a point of sampling time of said AID converter; ; a DC offset remover for calculating the average of the outputs of said DFPLL circuit in a predetermined symbol unit as a DC estimation value and subtracting the obtained DC estimation value from the output of said DFPLL circuit, thereby removing the DC offset; a detection signal generator for generating a detection signal representing whether the completion of the carrier recovery and the symbol timing recovery are completed in response to said DC estimation value and a difference of two consecutive DC estimation values; an equalizer for equalizing the output of said DFPLL circuit according to said detection signal; a phase tracking loop (PTL) circuit for correcting a phase error of the output of said equalizer which is not completely eliminated by said DFPLL circuit; a channel decoder for Trellis-decoding the output of said Pm L circuit and error-correction-decoding the Trellis-decoded data; and a source decoder for expanding said error-correction-decoded data.

10. A high definition television as claimed in claim 9, wherein said offset remover comprises: a DC offset estimator for calculating the average of the outputs from said DFPLL circuit in a predetermined symbol unit and outputting the average as a DC estimation value; and a subtracter for subtracting said DC estimation value from the output of said DFPLL circuit.

11. A high definition television as claimed in claim 9 or 10, wherein said detection signal generator comprises: a first comparison circuit for comparing said DC estimation value with a first threshold value and outputting a first comparison signal which represents whether the carrier recovery is completed; a second comparison circuit for comparing the difference between two consecutive DC estimation values with a second threshold value and outputting a second comparison signal which represents whether the symbol timing recovery is completed; and a logic AND gate for generating a detection signal which enables said equalizer when both said first and second comparison signals are present.

12. A high definition television as claimed in claim 11, wherein said second comparison circuit comprises: a delay for delaying said DC estimation value for the predetermined symbol period; a subtracter for subtracting the DC estimation value delayed by said delay from the current DC estimation value output from said DC offset estimator; an absolute circuit for calculating the absolute value of the output from said subtracter; and a comparator for comparing the output of said absolute circuit with a second threshold value and outputting a second comparison signal which represents whether the symbol timing recovery is completed.

13. A high definition television as claimed in claim 9, 10, 11 or 12 further comprising an automatic gain control (AGC) circuit for generating an AGC signal in response to the output of said DFPLL circuit and outputting the AGC signal to said tuner and said IF amplifier.

14. A method of detecting the completion of carrier recovery and symbol timing recovery, by signal processing in a receiver in which a carrier of a received signal is recovered, the received signal is demodulated into a baseband signal using the recovered carrier, a symbol timing of the demodulated signal is recovered, the demodulated signal is equalized according to the recovered symbol timing, and the equalized signal is decoded, said detecting method comprising the steps of:: (a) estimating a DC estimation value by calculating the average of said demodulated signals in a predetermined symbol unit; (b) generating a first detection signal which represents whether the carrier recovery is completed, in response to said DC estimation value; (c) generating a second detection signal which represents whether the carrier recovery is completed, in response to a difference between two consecutive DC estimation values; and (d) generating an operation control signal for controlling equalization and decoding of said demodulated signal, in response to said first and second detection signals generated in steps (b) and (c).

15. A circuit for detecting the completion of carrier recovery and symbol timing recovery, the circuit being substantially as herein described with reference to Figures 4 to 7 or 4 to 8.

16. An HDTV substantially as herein described with reference to Figures 4 to 7 or 4 to 8.

17. A method of detecting the completion of carrier recovery and symbol timing recovery, the method being substantially as herein described with reference to Figures 4 to 7 or 4 to 8.