GB2299230A

GB2299230A - Low voltage mixer, multiplier or modulator circuit

Info

Publication number: GB2299230A
Application number: GB9506026A
Authority: GB
Inventors: Gregory Weng Mun Yuen
Original assignee: Northern Telecom Ltd
Current assignee: Nortel Networks Ltd
Priority date: 1995-03-24
Filing date: 1995-03-24
Publication date: 1996-09-25
Also published as: GB9506026D0

Abstract

A Gilbert cell circuit is modified to provide operability at low supply voltages e.g. in mixer applications in a portable telephone instrument. The circuit includes first and second cross coupled long tailed transistor pairs Q1 to Q4 whose tail circuits are coupled to ground each via a respective further transistor Q5, Q6 provided with a resistive emitter load R31, R32.

Description

LOW VOLTAGE MIXER CIRCUIT This invention relates to circuits for mixer, multiplier or modulator applications, and in particular to an integrable circuit for use with low supply voltages.

The Gilbert cell has achieved wide use as a mixer, multiplier or modulator in a variety of integrated circuit applications. The circuit or cell comprises two transistor long tailed pairs, e.g. bipolar transistor pairs, whose tail circuits provide the respective collector loads of a further transistor long tailed pair. While the circuit is effective in operation, its adoption in battery powered portable equipment has been restricted by its inability to operate efficiently at low supply voltages.

This is a particular problem in a mobile communications terminal where size constraints limit the overall battery power that can be provided.

Also, due allowance must be made for the reduction in supply voltage that occurs towards the end of the battery lifetime cycle. Various workers have attempted modifications of the basic Gilbert cell circuit to address this problem, but the results of those attempts have not been entirely successful.

The object of the invention is to minimise or to overcome this disadvantage.

According to the invention there is provided a mixer, multiplier or modulator circuit adapted to operate at a reduced supply voltage, the circuit including first and second cross-coupled long tailed pairs of transistors whose current control terminals provide a first signal input, the tail circuit of each said pair being coupled to ground via a respective further transistor provided with a resistive load, and wherein the current control terminal of at least one said further transistor provides a second signal input.

According to the invention there is further provided a mixer, multiplier or modulator circuit adapted to operate at a reduced supply voltage, the circuit including first and second cross-coupled long tailed pairs of bipolar transistors whose base terminals provide a first signal input and whose collector terminals provide a circuit output, the tail circuit of each said pair being coupled to ground via a respective further bipolar transistor having a resistive emitter load, wherein a resistive coupling is provided between the emitters of the further transistors, and wherein the emitter terminals of said further transistors provide a second signal input.

According to the invention there is further provided a mixer circuit adapted to operate at a reduced supply voltage, the circuit including first and second cross-coupled long tailed pairs of bipolar transistors whose base terminals provide a signal input and whose collector terminals provide a circuit output, the tail circuit of each said pair being coupled to ground via a respective first and second further bipolar transistor having a resistive emitter load, and a third further bipolar transistor provided with a resistive emitter load and coupled between the circuit supply and ground, wherein a first resistive coupling is provided between the emitters of the first and second further transistors, wherein a second resistive coupling is provided between the emitters of the second and third further transistors, wherein the base terminals of the first and third transistors together provide a local oscillator input, and wherein the base terminal of said second further transistor provides an input for a direct voltage bias whereby to control the operating condition of the circuit.

Embodiments of the invention will now be described with reference to the accompanying drawings in which: Fig. 1 shows a conventional Gilbert cell circuit; Fig. 2 shows a modification of the circuit of Figure 1; Fig. 3 shows a modified Gilbert cell circuit according to one embodiment of the invention; and Fig. 4 shows a modified Gilbert cell circuit according to a further embodiment of the invention.

Referring to Figure 1 which is introduced for comparative and explanatory purposes, the conventional Gilbert cell comprises first and second cross-coupled long tailed transistor pairs, formed by bipolar transistors Q1 to Q4, whose respective tail circuits form the collector loads of a further long tailed transistor pair comprising transistors Q5 and Q6. A further transistor Q7 is provided in the tail circuit of the further long tailed pair. The circuit thus has three levels of stacked transistors.

In use, a first input signal is applied to the first and second long tailed pairs and a received input signal is applied to the further long tailed pair, a corresponding output signal being derived from the collector of transistor Q4. A direct voltage bias applied to the base of transistor Q7 sets the operating conditions of the circuit.

As can be seen, the circuit of Figure 1 has three levels of stacked transistors. To avoid saturation of any one or more transistors, a minimum supply voltage Vcc of about 3 volts is required to take into account the collector-emitter saturation voltages of transistors Q1 to Q7, the applied levels of voltage swing at the inputs and the required output voltage swing.

The minimum supply voltage requirement may be calculated from the expression Vat(07) + V2 + V5at(Q5/Q6) + V1 + V,,1(Q1/Q2/Q3/Q4) + IR Where V1 is the peak signal voltage at input 1 V2 is the peak signal voltage at input 2 I is the current in transistor Q7 and R is the value of the resistor loads of transistors Q1/Q3 and Q2/Q4 Substituting practical values in this expression gives the aforementioned minimum supply voltage of about 3 volts Referring now to Figure 2, which is also introduced for comparative and explanatory purposes, this shows a conventional modification of the basic Gilbert cell circuit of Fig. 1 to achieve a larger input voltage range.

In this circuit, resistor R21 provides emitter degeneration of transistors Q5 and Q6. Direct current bias is provided via first and second current sinks formed respectively by transistor Q21 and resistor R22 and by transistor Q22 and resistor R23. To minimise noise introduced by transistors Q21 and Q22, it is desirable that resistors R22 and R23 should have high values. However, if this is done, a higher input voltage range and a higher DC voltage drop across resistors R22 and R23 can be accommodated only by increasing the supply voltage to a value greater than the minimum value for the circuit of figure 1.

Figure 3 shows a modified Gilbert cell structure according to one embodiment of the invention. By coupling the emitters of transistors Q5 and Q6 to ground with resistors R31 and R32, one stacked level of transistors is avoided and the voltage headroom restrictions are thus eased. In addition, we have found that the noise contribution from resistors R31 and R32 is low. In this circuit, a first input signal, e.g. a local oscillator signal is applied to the base terminals of transistors 01 to Q4, and a second input signal is applied to the base terminal of transistor Q5, a corresponding output being taken from the collector terminal of transistor Q4. A direct current bias for the circuit is applied to the base terminal of transistor Q6.

A further embodiment is shown in Figure 4 wherein the circuit of figure 3 is modified to accommodate a single ended input at input 2. In this arrangement, a further transistor Q41 supplies signal current to transistor Q6 via a resistor R41 whose value is adjusted to balance the signal currents in transistors Q5 and Q6. Resistor R42 supplies direct current bias to transistor 041. In a mixer application where input 1 comprises a local oscillator signal (LO) and a radio frequency (RF) signal is applied to input 2, this has the effect of maximising RF rejection and conversion gain and of minimising noise. The base of transistor Q6 provides a DC bias input to the circuit whereby to control the currents through the first and second long tailed pairs and thus to control the operating condition of the circuit.

The circuits described above with reference to figures 3 and 4 are of particular application as mixers, multipliers or modulators in portable battery operated equipment such as mobile telephones.

It will be appreciated that although the circuits of figures 3 and 4 have been described with reference to npn bipolar transistors, the techniques embodied therein are applicable to the construction of equivalent circuits incorporating pnp bipolar transistors or field effect transistors.

Claims

CLAIMS:

1. A mixer, multiplier or modulator circuit adapted to operate at a reduced supply voltage, the circuit including first and second crosscoupled long tailed pairs of transistors whose current control terminals provide a first signal input, the tail circuit of each said pair being coupled to ground via a respective further transistor provided with a resistive load, and wherein the current control terminal of at least one said further transistor provides a second signal input.

2. A circuit as claimed in claim 1, wherein said first signal input comprises a differential input and said second signal input comprises a single ended input.

3. A circuit as claimed in claim 1, wherein the current control terminal of a said further transistor provides an input for a direct bias voltage.

4. A circuit as claimed in claim 1, 2 or 3, wherein said transistors are bipolar transistors.

5. A mixer, multiplier or modulator circuit adapted to operate at a reduced supply voltage, the circuit including first and second crosscoupled long tailed pairs of bipolar transistors whose base terminals provide a first signal input and whose collector terminals provide a circuit output, the tail circuit of each said pair being coupled to ground via a respective further bipolar transistor having a resistive emitter load, wherein a resistive coupling is provided between the emitters of the further transistors, and wherein the base terminals of said further transistors provide a second signal input.

6. A mixer circuit adapted to operate at a reduced supply voltage, the circuit including first and second cross-coupled long tailed pairs of bipolar transistors whose base terminals provide a signal input and whose collector terminals provide a circuit output, the tail circuit of each said pair being coupled to ground via a respective first and second further bipolar transistor having a resistive emitter load, and a third further bipolar transistor provided with a resistive emitter load and coupled between the circuit supply and ground, wherein a first resistive coupling is provided between the emitters of the first and second further transistors, wherein a second resistive coupling is provided between the emitters of the second and third further transistors, wherein the base terminals of the first and third transistors together provide a local oscillator input, and wherein the base terminal of said second further transistor provides an input for a direct voltage bias whereby to control the operating condition of the circuit.

7. A mixer, multiplier or modulator circuit substantially as described herein with reference to and as shown in figure 4 or figure 5 of the accompanying drawings.

8. A portable telephone instrument incorporating a mixer circuit as claimed in any one of claims 1 to 7.