GB2299189B - Carry lookaheader for full-adder circuit - Google Patents
Carry lookaheader for full-adder circuitInfo
- Publication number
- GB2299189B GB2299189B GB9606262A GB9606262A GB2299189B GB 2299189 B GB2299189 B GB 2299189B GB 9606262 A GB9606262 A GB 9606262A GB 9606262 A GB9606262 A GB 9606262A GB 2299189 B GB2299189 B GB 2299189B
- Authority
- GB
- United Kingdom
- Prior art keywords
- lookaheader
- full
- carry
- adder circuit
- adder
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Fee Related
Links
Classifications
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F7/00—Methods or arrangements for processing data by operating upon the order or content of the data handled
- G06F7/38—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation
- G06F7/40—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation using contact-making devices, e.g. electromagnetic relay
- G06F7/42—Adding; Subtracting
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F7/00—Methods or arrangements for processing data by operating upon the order or content of the data handled
- G06F7/38—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation
- G06F7/48—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation using non-contact-making devices, e.g. tube, solid state device; using unspecified devices
- G06F7/50—Adding; Subtracting
- G06F7/505—Adding; Subtracting in bit-parallel fashion, i.e. having a different digit-handling circuit for each denomination
- G06F7/506—Adding; Subtracting in bit-parallel fashion, i.e. having a different digit-handling circuit for each denomination with simultaneous carry generation for, or propagation over, two or more stages
- G06F7/508—Adding; Subtracting in bit-parallel fashion, i.e. having a different digit-handling circuit for each denomination with simultaneous carry generation for, or propagation over, two or more stages using carry look-ahead circuits
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
KR1019950006323A KR0166498B1 (en) | 1995-03-24 | 1995-03-24 | Full adder |
Publications (3)
Publication Number | Publication Date |
---|---|
GB9606262D0 GB9606262D0 (en) | 1996-05-29 |
GB2299189A GB2299189A (en) | 1996-09-25 |
GB2299189B true GB2299189B (en) | 1999-12-08 |
Family
ID=19410485
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
GB9606262A Expired - Fee Related GB2299189B (en) | 1995-03-24 | 1996-03-25 | Carry lookaheader for full-adder circuit |
Country Status (2)
Country | Link |
---|---|
KR (1) | KR0166498B1 (en) |
GB (1) | GB2299189B (en) |
Families Citing this family (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
TW359796B (en) * | 1996-10-29 | 1999-06-01 | Matsushita Electric Ind Co Ltd | Adder circuit and layout structure therefor |
Citations (5)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
GB2184579A (en) * | 1985-12-20 | 1987-06-24 | Texas Instruments Ltd | A multi-stage parallel binary adder |
EP0242600A2 (en) * | 1986-03-20 | 1987-10-28 | Kabushiki Kaisha Toshiba | Carry look-ahead calculating method and circuits therefor |
EP0320111A2 (en) * | 1987-12-11 | 1989-06-14 | AT&T Corp. | Multiple output field effect transistor logic |
US5357457A (en) * | 1992-07-30 | 1994-10-18 | Mitsubishi Denki Kabushiki Kaisha | Adder with carry look ahead circuit |
EP0626638A1 (en) * | 1993-05-03 | 1994-11-30 | Motorola, Inc. | A one's complement adder and method of operation |
-
1995
- 1995-03-24 KR KR1019950006323A patent/KR0166498B1/en not_active IP Right Cessation
-
1996
- 1996-03-25 GB GB9606262A patent/GB2299189B/en not_active Expired - Fee Related
Patent Citations (5)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
GB2184579A (en) * | 1985-12-20 | 1987-06-24 | Texas Instruments Ltd | A multi-stage parallel binary adder |
EP0242600A2 (en) * | 1986-03-20 | 1987-10-28 | Kabushiki Kaisha Toshiba | Carry look-ahead calculating method and circuits therefor |
EP0320111A2 (en) * | 1987-12-11 | 1989-06-14 | AT&T Corp. | Multiple output field effect transistor logic |
US5357457A (en) * | 1992-07-30 | 1994-10-18 | Mitsubishi Denki Kabushiki Kaisha | Adder with carry look ahead circuit |
EP0626638A1 (en) * | 1993-05-03 | 1994-11-30 | Motorola, Inc. | A one's complement adder and method of operation |
Also Published As
Publication number | Publication date |
---|---|
GB2299189A (en) | 1996-09-25 |
KR960035252A (en) | 1996-10-24 |
KR0166498B1 (en) | 1999-01-15 |
GB9606262D0 (en) | 1996-05-29 |
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Legal Events
Date | Code | Title | Description |
---|---|---|---|
732E | Amendments to the register in respect of changes of name or changes affecting rights (sect. 32/1977) | ||
PCNP | Patent ceased through non-payment of renewal fee |
Effective date: 20070325 |