GB2299189A

GB2299189A - Carry lookaheader for full-adder circuit

Info

Publication number: GB2299189A
Application number: GB9606262A
Authority: GB
Inventors: Huy Chan Jung
Original assignee: Hyundai Electronics Industries Co Ltd
Current assignee: SK Hynix Inc
Priority date: 1995-03-24
Filing date: 1996-03-25
Publication date: 1996-09-25
Anticipated expiration: 2016-03-25
Also published as: GB9606262D0; GB2299189B; KR960035252A; KR0166498B1

Abstract

A full-adder circuit for n -bit inputs comprises n full-adders (Fig 5) each adding bit values A i , B i of a respective significance i to generate output bits P i , and G i . The circuit also comprises a carry lookaheader implemented in one shared logic circuit to receive the output bits from each adder and a carry enable signal C o and to transfer generated carry-in bits C i to each next-higher-significance adder. The number of transistors Q used in the lookaheader is minimised by their being common to the generation of plural carry-in bits. Also, the maximum carry generation delay path is shortened, thereby enhancing data processing speed.

Description

CARRY WOKAHEADER FOR FULL-ADDER CIRCUIT BACKGROUND OF THE INVENTION Field of the Invention The present invention relates in general to carry lookaheaders for full-adder circuits as digital logic circuits, and more particularly to a carry lookaheader for a full-adder circuit in which the number of transistors used is minimized in a shared manner, thereby reducing the occupied area on the chip and enhancing the data processing speed.

Description of the Prior Art A carry lookaheader of the present invention is applicable to all digital logic circuits requiring an adder and a multiplier.

Generally, adders are arithmetic circuits for adding two or three input bits. More particularly among them, full-adders are adapted to input an addend, an augend and a carry from the lower-order part and to output the sum and a carry to the higher-order part. To this end, such a full-adder has three input terminals and two output terminals.

Referring to Fig. 1, there is shown a logic circuit diagram of a conventional full-adder. As shown in this drawing, the conventional full-adder is adapted to add three digits at a time. To this end, the conventional full-adder comprises two half-adders 11 and 12 and one OR gate OR1.

Each of the half-adders 11 and 12 is provided with one exclusive-OR gate and one AND gate. The output of the exclusive-OR gate is the sum of two bits and the output of the AND gate is a carry.

Assuming that the inputs A, Bj and Cm to the full-adder are 1, 1 and 0, respectively, the sum and carry of the first halfadder 11 are 0 and 1, respectively, and the sum and carry of the second half-adder 12 are both 0. As a result, the full-adder finally outputs the sum of 0 and the carry of 1.

Provided that the inputs A, B1 and C. to the full-adder are all 1, the full-adder will finally output the sum of 1 and the carry of 1.

Obtaining the final sum and carry of the full-adder with respect to various input states in the above manner, the following logical function table 1 can be made: TABLE 1 A B C CARRY SUM 0 0 0 0 0 0 0 1 0 1 0 1 0 0 1 0 1 1 1 0 1 0 0 0 1 1 0 1 1 0 1 1 0 1 0 1 1 1 1 1 The above-mentioned output of the full-adder can be expressed in the Boolean functions as follows: C2 = G1 + P1C1 ------------ (1-1) C3 = G2 + P2G1 + P2P1C1 ------------ (1-2) C4 = G3 + P3G2 + P3P2G1 + P3P2P1C1 ~~~~~~~----- (1-3) Cj+1 = G1 + PjCj ------------ (1-4) Referring to Fig. 2, there is shown a circuit diagram of a conventional 4-bit carry lookaheader.As shown in this drawing, the conventional 4-bit carry lookaheader is adapted to input the sum P1, carry G1 and carry enable signal C0 from the full-adder as shown in Fig. 1 and to generate a carry C4 of the fourth digit.

The carry C4 at the output terminal of the 4-bit carry lookaheader can be expressed in the Boolean function as follows: C4 = G3 + P3G2 + P3P2G1 + P3P2P1C1 where, C1 = Go + P0C0 Also, carries C2 and C3 can be expressed in the Boolean functions as follows: C2 = G1 + P1Cl C3 = G2 + P2Gl + P2P1C1 As seen, the above Boolean function expressions are the same as those in Fig. 1.

However, the above-mentioned conventional 4-bit carry lookaheader is adapted to generate only the carry C4 of the fourth of the four digits. For this reason, in order to obtain the carries C1, C2 and C3 of the remaining digits, there is required an equal amount of carry lookaheaders as there are remaining digits. Namely, a carry lookaheader is required to generate the carry C1 of the first digit at a second node N2.

Another carry lookaheader is required to generate the carry C2 of the second digit at a third node N3. A further carry lookaheader must be provided to generate the carry C3 of the third digit at a fourth node N4.

In other words, there is conventionally required the same number of carry lookaheaders as there are digits of bits to be added. Further, each of the conventional carry lookaheaders comprises logic transistors which are individually constructed as shown in Fig. 2, resulting in an increase in the occupied area on the chip and a reduction in the data processing speed.

SUMMARY OF THE INVENTION Therefore, the present invention has been made in view of the above problem, and it is an object of the present invention to provide a carry lookaheader for a full-adder circuit which is capable of reducing the occupied area on the chip and enhancing the data processing speed.

In accordance with the present invention, the above and other objects can be accomplished by a provision of a full-adder circuit for a logic unit comprising n full-adder means, each of the n full-adder means adding bit values of a corresponding one of n digits to generate a sum and a carry, wherein the improvement comprises carry lookaheader means implemented in one logic circuit to input the sum and carry from each of the n full-adder means and transfer the inputted carry to the subsequent higher-order full-adder means.

BRIEF DESCRIPTION OF THE DRAWINGS The above and other objects, features and advantages of the present invention will be more clearly understood from the following detailed description taken in conjunction with the accompanying drawings, in which: Fig. 1 is a logic circuit diagram of a conventional fulladder; Fig. 2 is a circuit diagram of a conventional 4-bit carry lookaheader; Fig. 3 is a circuit diagram of an n-bit carry lookaheader in accordance with an embodiment of the present invention; Fig. 4 is a circuit diagram of a 4-bit carry lookaheader in accordance with an alternative embodiment of the present invention; and Fig. 5 is a block diagram of a 4-bit full-adder circuit employing the 4-bit carry lookaheader in Fig. 4.

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Referring to Fig. 3, there is shown a circuit diagram of an n-bit carry lookaheader in accordance with an embodiment of the present invention. As shown in this drawing, the n-bit carry lookaheader comprises PMOS transistors Ql and Q2 connected in parallel between a source of a supply voltage Vcc and a sixth node N6, a PMOS transistor Q6 connected between the sixth node N6 and a seventh node N7, and a first inverter for inverting a signal at the seventh node N7 and outputting the inverted signal as a carry C1 of the first digit. The PMOS transistor Q1 has its gate terminal for inputting a carry enable signal C0 and the PMOS transistor Q2 has its gate terminal for inputting the sum P0.

The PMOS transistor Q6 has its gate terminal for inputting a carry G,.

The n-bit carry lookaheader further comprises a PMOS transistor Q3 connected between the supply voltage source Vcc and an eighth node N8, a PMOS transistor Q7 connected between the seventh node N7 and the eighth node N8, a PMOS transistor Q8 connected between the eighth node N8 and a ninth node N9, and a second inverter for inverting a signal at the ninth node N9 and outputting the inverted signal as a carry C2 of the second digit.

The PMOS transistor Q3 has its gate terminal for inputting the sum P1 and the PMOS transistor Q7 has its gate terminal for inputting the complement /P1 of the sum P. The PMOS transistor Q8 has its gate terminal for inputting a carry Gt.

The n-bit carry lookaheader further comprises a PMOS transistor Q4 connected between the supply voltage source Vcc and a tenth node N10, a PMOS transistor Q9 connected between the ninth node N9 and the tenth node N10, a PMOS transistor Q10 connected between the tenth node N10 and an eleventh node N11, and a third inverter for inverting a signal at the eleventh node N11 and outputting the inverted signal as a carry C.1 of the (n 1)th digit. The PMOS transistor Q4 has its gate terminal for inputting the sum P2 and the PMOS transistor Q9 has its gate terminal for inputting the complement /P2 of the sum P2. The PMOS transistor Q10 has its gate terminal for inputting a carry G2.

The n-bit carry lookaheader further comprises a PMOS transistor Q5 connected between the supply voltage source Vcc and a twelfth node N12, a PMOS transistor Qll connected between the eleventh node N11 and the twelfth node N12, a PMOS transistor Q12 connected between the twelfth node N12 and a thirteenth node N13, a PMOS transistor Q13 connected between the thirteenth node N13 and the eleventh node N11, and a fourth inverter for inverting a signal at the thirteenth node N13 and outputting the inverted signal as a carry Cn of the nth digit.

The PMOS transistor Q5 has its gate terminal for inputting the sum Pn and the PMOS transistor Qll has its gate terminal for inputting the complement /Pn of the sum Pn. The PMOS transistor Q12 has its gate terminal for'inputting a carry Gn and the PMOS transistor Q13 has its gate terminal for inputting the sum The n-bit carry lookaheader further comprises an NMOS transistor Q25 connected between the thirteenth node N13 and a source of a ground voltage Vss, a transfer gate of NMOS and PMOS transistors Q14 and Q15 connected between the eleventh node N11 and a fourteenth node N14, an NMOS transistor Q24 connected between the fourteenth node N14 and the ground voltage source Vss, a transfer gate of NMOS and PMOS transistors Q16 and Q17 connected between the fourteenth node N14 and the ninth node N9, an NMOS transistor Q23 connected between the ninth node N9 and the ground voltage source Vss, a transfer gate of NMOS and PMOS transistors Q18 and Q19 connected between the ninth node N9 and the seventh node N7, an NMOS transistor Q22 connected between the seventh node N7 and the ground voltage source Vss, an NMOS transistor Q20 connected between the seventh node N7 and a fifteenth node N15, and an NMOS transistor Q21 connected between the fifteenth node N15 and the ground voltage source Vss.The NMOS transistor Q25 has its gate terminal for inputting the carry Gn. The NMOS transistor Q14 has its gate terminal for inputting the sum P3 and the PMOS transistor Q15 has its gate terminal for inputting the complement /P3 of the sum P3. The NMOS transistor Q24 has its gate terminal for inputting the carry G2. The NMOS transistor Q16 has its gate terminal for inputting the sum P2 and the PMOS transistor Q17 has its gate terminal for inputting the complement /P2 of the sum P2. The NMOS transistor Q23 has its gate terminal for inputting the carry G1. The NMOS transistor Q18 has its gate terminal for inputting the sum P1 and the PMOS transistor Q19 has its gate terminal for inputting the complement /P1 of the sum P1.The NMOS transistor Q22 has its gate terminal for inputting the carry Go. The NMOS transistor Q20 has its gate terminal for inputting the sum P0 and the NMOS transistor Q21 has its gate terminal for inputting the carry enable signal C0.

As shown in Fig. 3, in accordance with the preferred embodiment of the present invention, the same transistors are used to implement the functions of C1, C2, C3, , Cn to generate the carries in one logic circuit. In other words, the transistors are used in a shared manner to generate the carries in one logic circuit.

In order to employ transistors used for the implementation of a given Boolean function again for the implementation of another function, redundant input variables must be employed in addition to input variables used for the implementation of the given Boolean function.

For the implementation of such a subordinate function, a dual PMOS/NMOS transistor network can be separated from the previously implemented static CMOS combination gates.

In this manner, various Boolean functions can be implemented in addition to the given Boolean function. Further, PMOS and NMOS parts previously used can be reused in a shared manner.

Such a shared manner reduces the number of both PMOS and NMOS transistors as compared with individual function implementation. Therefore, the use of such a shared manner has the effect of making an efficient CMOS layout possible.

Referring again to Fig. 3, the redundant inputs /P1, /P2, , /Pn are applied to the gate terminals of the PMOS transistors Q7, Q9, , Qll, respectively. The NMOS transistors Q14, Q16 and Ql8 have their drain and source terminals connected respectively to source and drain terminals of the associated PMOS transistors Q15, Q17 and Q19. Further, the redundant inputs /P1, /P2, , /Pn are applied to the gate terminals of the PMOS transistors Q19, Q17, Q15, respectively.

The use of additional redundant inputs allows the existing Boolean function to share the PMOS and NMOS parts with a new function.

Therefore, the signal at the common drain connection node N7 of the PMOS transistor Q6 which input the carry Go at its gate terminal and the NMOS transistor Q20 which inputs the sum P0 at its gate terminal is merely used as the input to the inverter gate to generate the carry C1.

The carry C1 can be expressed in the Boolean function as follows: C1 = Go + C0P0 As seen, the above Boolean function expression is the same as that in the conventional carry lookaheader.

Similarly, the carries C2, C3, , Cn can be defined in the previously mentioned Boolean function expressions 1-1, 1-2, , 1-4.

Referring to Fig. 4, there is shown a circuit diagram of a 4-bit carry lookaheader in accordance with an alternative embodiment of the present invention. The 4-bit carry lookaheader can be readily implemented on the basis of the n-bit carry lookaheader of the first embodiment to generate four carry signals C1, C2, C3 and C4 in one logic circuit at a time.

Differently from the conventional carry lookaheader in Fig. 2, the 4-bit carry lookaheader of the present invention comprises PMOS transistors Q32, Q34 and Q36 connected in series, which input the complements /Pl, /P2 and /P3 of the sums P1, P2 and P3 at their gate terminals, respectively. Also, PMOS transistors Q39, Q41 and Q43 which input the complements /P1, /P2 and /P3 of the sums Pl, P2 and P3 respectively at their gate terminals are connected in parallel to the associated NMOS transistors Q38, Q40 and Q42.

The carries C1, C2, C3 and C4 at the output terminals of the 4-bit carry lookaheader can be expressed in the Boolean functions as follows: Cl = Go + C0P0 C2 = G1 + P 1C1 C3 = G2 + P2Gl + P2P1C1 C4 = G3 + P3G2 + P3P2G1 + P3P2P1C1 It can be seen that the above Boolean function expressions are the same as the previously mentioned Boolean function expressions 1-1 to 1-4.

As a result, the number of transistors used to generate the four carry signals C1, C2, C3 and C4 is reduced from 56 to 32.

Also, the maximum carry generation delay path is changed from the conventional 5-PMOS transistor series connection path to the 2-PMOS/3-NMOS transistor series connection path, thereby enhancing the data processing speed. For example, in the case where the present invention is applied to a 32-bit carry lookaheader, the path change has the effect of increasing the data processing speed by 12.5%.

Referring to Fig. 5, there is shown a block diagram of a 4bit full-adder circuit employing the 4-bit carry lookaheader in Fig. 4. As shown in this drawing, the 4-bit full-adder circuit comprises a first full-adder 21 for adding bit values of the first digit (20) to generate the sum P0 and a carry Go, a second full-adder 22 for adding bit values of the second digit (21) to generate the sum P1 and a carry G1, a third full-adder 23 for adding bit values of the third digit (22) to generate the sum P2 and a carry G2, a fourth full-adder 24 for adding bit values of the fourth digit (23) to generate the sum P3 and a carry G3, and a 4-bit carry lookaheader 20 for inputting the sum P0, P1, P2 or P3 and the carry G,, G1, G2 or G3 from each of the first to fourth full-adders 21-24 and transferring the inputted carry Cn to the subsequent higher-order full-adder.

The operation of the 4-bit full-adder circuit with the above-mentioned construction in accordance with the present invention will hereinafter be described in detail with reference to the following example.

Assume that the binary values of 0101(2) and 0110(2) are applied to the first to fourth full-adders 21-24.

The input signals Ao and B0 to the first full-adder 21 are 1 and 0, respectively, the input signals A1 and B1 to the second full-adder 22 are 0 and 1, respectively, the input signals A2 and B2 to the third full-adder 23 are both 1 and the input signals A3 and B3 to the fourth full-adder 24 are both 0.

The carry C1 is 0 because the sum P0 and carry Go of the first full-adder 21 are 1 and 0, respectively. The carry C2 is 0 because the sum P1 and carry G1 of the second full-adder 22 are 1 and 0, respectively. The carry C3 is 1 because the sum P2 and carry G2 of the third full-adder 23 are 0 and 1, respectively.

The carry C4 is 0 because the sum P3 and carry G3 of the fourth full-adder 24 are 1 and 0, respectively. Namely, the fourth full-adder 24 generates the sum P3 of 1 and the carry G3 of 0 by adding the carry C3 from the third full-adder 23 to the input signals A3 and B3. As a result, the binary values of 1011(2) are outputted from output terminals So - S3 of the first to fourth full-adders 21-24.

With the carry lookaheader 20 embodied by the present invention, the 4-bit full-adder circuit provided with the four full-adders for calculating the four bit digits is improved in its occupied area and data processing speed.

As apparent from the above description, according to the present invention, the number of transistors used in the carry lookaheader are minimized by employing the shared manner. Also, the maximum carry generation delay path is shortened.

Therefore, in the case where the carry lookaheader of the present invention is applied to full-adders in a logic unit, the data processing speed is significantly enhanced. Further, in an ASIC design circuit, the layout area and data processing speed are significantly enhanced according to the frequency in the use thereof.

Although the preferred embodiments of the present invention have been disclosed for illustrative purposes, those skilled in the art will appreciate that various modifications, additions and substitutions are possible, without departing from the scope and spirit of the invention as disclosed in the accompanying claims.

Claims

CLAIHS:

1. A full-adder circuit for a logic unit comprising n fulladder means, each of said n full-adder means adding bit values of a corresponding one of n digits to generate a sum and a carry, wherein the improvement comprises carry lookaheader means implemented in one logic circuit to input the sum and carry from each of said n full-adder means and transfer the inputted carry to the subsequent higher-order full-adder means.

2. A full-adder circuit for a logic unit as set forth in Claim 1, wherein said carry lookaheader means is adapted to transfer the carry from each of said n full-adder means in response to the sum therefrom and a complement thereof.

3. A full-adder circuit for a logic unit as set forth in Claim 1 or 2, wherein said carry lookaheader means is constructed to satisfy the following Boolean function expressions: C1 = Go + C0P0 C2 = G1 + P1CI C3 = G2 + P2G1 + P2P1C1 C4 = G3 + P3G2 + P3P2G1 + P3PzPlC C1 = Gn + PnCn where, Cn is the carry from said carry lookaheader means, is is the sum of each of said n full-adder means, Gn is the carry of each of said n full-adder means and C0 is a carry enable signal.

4. A full-adder circuit for a logic unit substantially as hereinbefore described with respect to any one of Figures 3 to 5 of the accompanying drawings.