GB2296143A

GB2296143A - Active load using a programmable transistor

Info

Publication number: GB2296143A
Application number: GB9425131A
Authority: GB
Inventors: Gerard Francis Harkin
Original assignee: Philips Electronics UK Ltd
Current assignee: Philips Electronics UK Ltd
Priority date: 1994-12-13
Filing date: 1994-12-13
Publication date: 1996-06-19
Also published as: GB9425131D0

Abstract

The active load M2 in an inverting common-source amplifier circuit comprises a gate-source coupled programmable transistor, such as an MNOS or floating gate device, which is programmed by a programming voltage applied through MOS switch SW1. MOS switch SW2, which may also be programmable, is closed in normal operation. Cascode amplifiers, logic circuits, and differential amplifiers are disclosed; the latter may be used as sense amplifiers in non-volatile memories (figure 10) or imaging arrays. The circuit may be of thin-film construction (figures 11-14). <IMAGE>

Description

DESCRIPTION A CURRENT SOURCE This invention reiates to a current source and to a circuit, for example a circuit comprising an inverter, incorporating such a current source.

As described in a paper entitled "Digital MOS Integrated Circuits" edited by Mohammed Elmasry published in the IEEE press selected reprint series, a common way of forming a current source or active load in NMOS (n-channel insulated gate field effect transistor) technology is to use as the active load or current source an n-channel enhancement mode insulated gate field effect transistor (NMOS) having its control or gate electrode either coupled to its drain electrode or to a separate potential higher than that supplied to the drain electrode.Although the aforementioned paper is directed towards digital circuits, such current sources and circuits may also be used for analogue circuit applications, for example as inverter currents or amplifiers as described in a paper by Hosticka entitled "Improvements of the gain of MOS amplifiers" published in the IEEEjournal of Solid-State circuits Vol SC-14 No: 6 November 1979.

Figure 1 of the accompanying drawings shows an inverter 1 comprising first and second voltage supply lines 2 and 3, an input signal line I for receiving an input signal to be inverted and an output signal 0 for supplying an inverted output signal. The control or gate electrode g of an enhancement mode driver NMOS transistor Ml is coupled to the input signal line I. The first main electrodes of the driver transistor M1 is coupled to the first voltage supply line 2 while the second main electrode d of the driver transistor M1 is coupled to the output supply line 0 and, via the load, to the second voltage supply line 3.As shown in Figure 1 and as described in the aforementioned paper, the load comprises an n-channel enhancement mode insulated gate field effect transistor (NMOS) M2 having its first electrode s coupled to the second electrode d of the driver transistor M1 and its control and second main electrodes g and d coupled to the second voltage supply line 3.

The small signal gain Av of such an inverter 1 is given by the following equation:

Equation 1 where 9M1 and 9M2 are the mutual transconductances of the driver transistor M1 and the load transistor M2, respectively and W1 and W2 are the widths and L1 and L2 are the lengths of the conduction channels of the driver and load transistors M1 and M2 respectively.

Thus, the small signal dc or low frequency gain Av of the inverter circuit 1 shown in Figure 1 exhibits a square root geometry dependence and the driver transistor M1 needs to be considerably larger than the load transistor M2 to provide an appreciable gain. For example, assuming that the conduction channel lengths L1 and L2 of the two transistors M1 and M2 are the same, then the width W1 of the driver transistor M1 needs to be 100 times the width W2 of the load transistor M2 to provide a gain of 10.

Moreover, the gain of the inverter circuit 1 will be poor because the voltage on the output line 0 will modulate the gate source voltage VGS2 of the load transistor M2 so causing a transconductance current to flow which thus lowers the load impedance and so results in a low output impedance.

As described in the aforementioned paper and as shown in Figure 2 of the accompanying drawings, a circuit 1 a comprising, an inverter has previously been proposed in which a capacitor Cs is connected between the gate and source electrodes g and s of the load transistor M2. In operation of this inverter circuit 1 a, the capacitor Cs is charged from a voltage supply line V5 via a switch S1 to a certain value. The switch S1 is then opened and the capacitor Cs acts to maintain the gate-source voltage Vgs of the load transistor M2 constant so that the load transistor M2 simulates a constant current source because the load transistor M2 in its saturation region. Reference may be made to any suitable text book (see for example pages 438 to 441 of Physics of Semiconductors 2nd Edition by S.M.Sze published by John Wiley and Sons in 1 981) for a definition of the saturation and linear regions of an insulated gate field effect transistor. Ideally, the capacitor Cs behaves like a battery so that the voltage on the output line 0 no longer affects the gate source voltage Vgs of the load transistor M2. However, in practice, the voltage on the output line 0 couples a voltage onto the gate electrode of the load transistor M2 via the capacitance C5 and the parasitic capacitance Cp (where the parasitic capacitance Cp comprises the intrinsic gate-drain capacitance Cgd of the load transistor M2 and the gate-source capacitance Cgs of the switch where the switch is a transistor).This coupling of the voltage on the output line 0 onto the gate electrode of the load device M2 alters the voltage at the capacitor C5 and thus causes a transconductance current to flow in the load transistor M2. If we define the ratio between the capacitance of the capacitor C5 and the combined capacitances of the capacitor C5 and the parasitic capacitance Cp as being equal to x (C5/(C5 + Cp) = x), then the small signal dc or low frequency gain Av of the inverter circuit 1 a, shown in Figure 2 of the accompanying drawings, is given by:

It can be seen from equation 2 that the coupling factor Cs/(Cs+Cp) should be made equal to 1 in order to eliminate the transconductance current gm2.Figure 3 shows a graph of small signal gain Av against the coupling factor Cs/(Cs + Cp) for the case where gml =gm2 and equals 10 micro amperes per volt and -gdsi = gds2 = 1 OOx 1 89 Siemens.

It can be seen from Figure 3 of the accompanying drawings that the maximum possible gain is 50 and that the gain drops to 40 for a coupling factor of 0.995. Even with a coupling factor of 0.995, the capacitance of the capacitor Cs is 200 times that of the parasitic capacitance C . When an insulated gate field effect transistor is in its saturation region, the channel region is pinched off at the drain region and accordingly the gate-source capacitance Cgs will be simply the capacitance resulting from the overlap between the gate electrode and the drain region. This overlap can, however, be quite significant and very tight processing tolerances would be required to reduce it to a very small value. Accordingly, in practice for the inverter circuit la shown in Figure 2 to provide a reasonable gain, the capacitor C5 will need to have a relatively large value and therefore will occupy a large area in the eventual circuit.

It is an aim of the present invention to provide a current source suitable for use as a load within an inverter circuit which overcomes or at least mitigates the above-mentioned problems.

According to one aspect of the present invention, there is provided a circuit having a current source comprising a gate-source coupled programmed memory transistor.

As used herein, the term "memory transistor" means a transistor capable of storing charge so as to alter its conductance properties and the term "programmed memory transistor" means such a memory transistor within which charge has been stored to alter its conductance properties so that, with an appropriate voltage applied between the drain and source electrodes of the programmed memory transistor, the memory transistor conducts with a gate-source voltage of zero. Such a programmed memory transistor when operated in its saturation region provides a current source which is effectively constant without having to resort to the provision of additional components such as the capacitor C5 used in the circuit shown in Figure 2 to provide a good current source. Thus the extra area required by the capacitor Cs is not required.Furthermore, because the memory transistor is programmed after it has been formed, the actual degree of programming, that is the amount of charge stored at the memory transistor may be adjusted to meet a particular requirement to adjust the conductance of the gatesource coupled programmed memory transistors. This ability to adjust the degree of programming may be particularly advantageous for analogue applications because adjusting the stored change will adjust the effective gate-source voltage Vgs so enabling characteristics ranging from a device having a large Vgs, and therefore a large current, but small gain, and a large bandwidth to a device having a low Vgs, and therefore small current but high gain, and a small or reduced bandwidth, to be selected depending upon the intended application.

Moreover, it should generally only be necessary to programme the memory transistor once. In contrast, the capacitor C5 of the inverter circuit to 1 a shown in Figure 2 of the accompanying drawings may have to be recharged periodically.

In a second aspect the present invention provides a circuit having a current source comprising a memory transistor having a first memory state and a second memory state in which the memory transistor is programmed and stores charge, a first switch for coupling the control electrode of the transistor to a voltage supply line for changing the memory state of the transistor from the first to the second state and a second switch for coupling the control electrode and one of the first and second main electrodes of the transistor together when the memory device is in the second state to form the current source.

A circuit in accordance with the second aspect provides a relatively simple way of programming the memory transistor and should allow, if necessary, for the programming of the memory transistor to be refreshed after a number of years of operational use should this prove necessary. Typically, the programming should be retained for a similar length of time as an equivalent memory transistor of an electrically programmable read only memory. As another possibility, such as a circuit should enable the memory transistor to be reprogrammed using the switches to adjust the programming to a user's requirements.

In a third aspect the present invention provides a circuit comprising an inverter, the circuit comprising first and second voltage supply lines, an input signal line for receiving an input signal to be inverted and an output signal line for supplying an inverted output signal, a transistor having first and second main electrodes and a control electrode with the first main electrode coupled to the first voltage supply line, the control electrode being coupled to the input signal line and the second main electrode being coupled to the output signal line and a load device coupling the second main electrode of the transistor to the second voltage supply line, the load device comprising a gate-source coupled programmed memory transistor.

Such a circuit has a load device providing a relatively constant current source which facilitates a high output impedance for the inverter circuit. Indeed, a small signal gain equivalent to that of a complementary MOS inverter circuit can be achieved without the need for having to use both n-channel and p-channel MOS transistors.This should, of course, be of particular advantage for those forms of integrated circuits where it is technologically difficult to provide both nchannel and p-channel enhancement mode MOStransistors; for example integrated circuits formed by thin film technology techniques by the deposition of amorphous or polycrystalline semiconductor materials onto insulating substrates such as glass or plastics where the p-channel enhancement mode thin film transistors may have an unacceptably high threshold voltages in addition to very poor carrier mobility characteristics or in the area of smart power or power integrated circuit technology where the constraints of having to integrate control or logic circuitry into the same substrate as a vertical power semiconductor device may make it very difficult to form usable p-channel enhancement mode MOS transistors.

In a fourth aspect the present invention provides a circuit comprising an inverter, the circuit comprising first and second voltage supply lines, an input signal line for receiving an input signal to be inverted and an output signal line for supplying an inverted output signal, a transistor having first and second main electrodes and a control electrode with the first main electrode coupled to the first voltage supply line, the control electrode being coupled to the input signal line and the second main electrode being coupled to the output signal line and a load device coupling the second main electrode of the transistor to the second voltage supply line, the load device comprising a memory transistor having a first memory state and a second memory state in which the memory transistor is programmed and stores charge, a first switch for coupling the control electrode of the transistor to a voltage supply line for changing the memory state of the transistor from the first to the second state and a second switch for coupling the control electrode and one of the first and second main electrodes of the transistor together when the memory device is in the second state to form the load device.

Such a circuit should facilitate relative simple programming of the memory transistor and may allow for the programming of the memory transistor to be adjusted relatively easily without having to alter the manufacturing process so that, for example, different operational requirements for different analogue circuit uses of the inverter circuit may be obtained without having to adjust the manufacturing process.

Of course, where the circuit is intended for analogue use, then the required programming voltage will generally be smaller than that required for digital applications.

The memory transistor may comprise any suitable transistor having conduction characteristics which are dependent upon whether the transistor is in a first state or in a second state in which the transistor stores charge. For example, the memory transistor may comprises an MIOS transistor such as an MNOS transistor, where the term "MIOS" means an insulated gate transistor in which the gate insulating layer comprises first and second sequential different insulating layers which define a region capable of trapping charge and the term "MNOS" means such a memory transistor in which the first and second different insulating layers comprise an oxide and a nitride respectively, generally silicon oxide and silicon nitride in the case of a transistor formed of silicon.

Generally, it should be relatively easy to modify the process used to form an n-channel enhancement mode MOS transistor to form an MIOS transistor and accordingly a current source or inverter circuit in accordance with the invention may be relatively easily integrated into an n-channel enhancement mode MOS transistor circuit.

As another possibility, the memory transistor may comprise a floating gate transistor in which charge is trapped at the electrically isolated floating gate. Such a floating gate memory transistor may be programmed relatively rapidly using a lower programming voltage and relying upon hot carrier injection resulting from a voltage applied between the source and drain of the transistor to effect the programming.

The first and second switches may comprise insulated gate field effect transistors, generally n-channel enhancement mode MOS transistors.

Generally, the circuit will be an integrated circuit possibly incorporating one or more additional components or circuit arrangements. Although a circuit in accordance with the invention could be formed using bulk technology, that is the circuit components may be formed within a semiconductor body or substrate, in one preferred example the circuit is formed using thin film technology.

The present invention also provides a device comprising a two dimensional array of storage elements arranged in rows and columns, row and column conductors for accessing individual ones of the storage elements and control circuitry for controlling access of the storage elements by the row and column conductors, the control circuitry comprising at least one circuit in accordance with any one of the first to fourth aspects.

In such a device, the storage elements may themselves be memory transistors and may have the same construction as the gatesource coupled memory transistor forming the current source so that no change to the manufacturing process, other than to modify the mask designs to incorporate additional memory transistors, should be necessary.

In another aspect, the present invention provides a method of forming a current source, which method comprises providing a memory transistor having a first memory state and a second memory state in which the memory transistor stores charge, coupling the control electrode of the transistor to a voltage supply line so changing the memory state of the transistor from the first to the second state and then disconnecting the coupling to the voltage supply line and coupling the control electrode and one of the first and second main electrodes of the transistor together to form the current source.

Embodiments of the present invention will now be described, by way of example, with reference to the accompanying drawings, in which: Figure 1 is a circuit diagram of a previously proposed inverter circuit; Figure 2 is a circuit diagram of another previously proposed inverter circuit; Figure 3 is a graph of the small signal dc or low frequency gain Av against coupling factor Cs for the load transistor of the circuit shown in Figure 2; Figure 4 is a simplified circuit diagram showing circuit comprising an inverter in accordance with the invention; Figure 5 shows a timing diagram for signals applied to the circuit shown in Figure 4; Figure 6 shows the drain current Id versus gate-source voltage Vgs characterising for an MNOS transistor before and after programming; Figure 7 is a more detailed circuit diagram showing one example of a circuit in accordance with the invention;; Figure 8 shows a timing diagram for signals applied to the circuit shown in Figure 7; Figures 9a and 9b show examples of circuits having a current source in accordance with the invention; Figure 10 shows part of a two-dimensional array incorporating an circuit in accordance with the invention; and Figures 11 to 14 show steps in one possible method for forming an enhancement mode NMOS and a MNOS transistor using thin film technology.

It should of course be understood that the drawings are not to scale and that like reference numerals are used throughout text to refer to like parts.

Referring now to Figures 4 to 14 of the drawings1 there are illustrated circuits which have a current source comprising a gate-source coupled programmed memory transistor.

As used herein, the term "memory transistor" means a transistor capable of storing charge so as to alter its conductance properties and the term "programmed memory transistor" means such a memory transistor within which charge has been stored to alter its conductance properties so that, with an appropriate voltage applied between the drain and source electrodes of the programmed memory transistor, the memory transistor conducts with a gate-source voltage of zero. Such a programmed memory transistor thus provides a current source which is effectively constant when operated in its saturation region without having to resort to the provision of additional components such as the capacitor C5 used in the circuit shown in Figure 2 to provide a good current source. Thus the extra area required by the capacitor Cs is not required.Furthermore, because the memory transistor is programmed after it has been formed, the actual degree of programming, that is the amount of charge stored at the memory transistor may be adjusted to meet a particular requirement to adjust the conductance of the gatesource coupled programmed memory transistors. This ability to adjust the degree of programming may be particularly advantageous for analogue applications because adjusting the stored change will adjust the effective gate-source voltage Vgs so enabling, characteristics ranging from a device having a large Vgs, and therefore a large current, but small gain, and a large bandwidth to a device having a low Vgs, and therefore small current but high gain, and a small or reduced bandwidth, to be selected depending upon the intended application.

Moreover, it should generally only be necessary to programme the memory transistor once, with the retention of the programming being similar to the retention of the programming of a memory transistor of a conventional electrically programmable read only memory. In contrast, the capacitor C5 of the inverter circuit to 1 a shown in Figure 2 of the accompanying drawings may have to be recharged periodically.

Figures 4 and 7 show inverter circuits 1 b and 1 c comprising first and second voltage supply lines 2 and 3, an input signal line I for receiving an input signal Vin to be inverted and an output signal line 0 for supplying an inverted output signal Vout, a transistor M1 having first and second main electrodes s and d and a control electrode g with the first main electrode s being coupled to the first voltage supply line 2, the control electrode g being coupled to the input signal line I and the second main electrode d being coupled to the output signal line 0 and a load device coupling the second main electrode d of the transistor M1 to the second voltage supply line 3, the load device comprising a gate-source coupled programmed memory transistor M2.

Referring now specifically to Figure 4, in this example the load transistor M2 comprises an MIOS transistor, that is an MOS transistor in which the gate insulating layer comprises first and second sequential different insulating layers defining a region capable of trapping charge.

In the case of a transistor formed using silicon technology, the first and second different insulating layers will generally comprise a silicon oxide and a silicon nitride layer, respectively, with the silicon oxide layer being adjacent the conduction channel area of the transistor (a so-called MNOS transistor). In this example, the transistor M1, that is the driver transistor of the inverter circuit 1 b, comprises an n-channel enhancement mode insulated gate field effect transistor (NMOS transistor). An example of the manufacture of the NMOS transistor M1 and the MNOS transistor M2 using thin film technology will be described hereinafter with reference to Figures 11 to 1 4.

In the example shown in Figure 4, the control or gate electrode g of the MNOS transistor M2 is coupled to a programming voltage supply line 5 via a first switch SW1 and to the source electrode of the MNOS transistor M2 via a second switch SW2. Any suitable form of device may be used for forming the switches SW1 and SW2.

Figure 5 shows a timing diagram for illustrating the manner in which the MNOS memory transistor M2 is programmed and the subsequent operation of the circuit 1 b. Figure 5a shows the voltage applied to the second voltage supply line 3 which provides a clocking signal for controlling operation of the circuit ib. Figures 5b and Sc show the status Stl and St2 of the switches SW1 and SW2, respectively. Figure 5d shows the programming voltage V applied to the gate electrode g of the MNOS transistor M2. The first voltage supply line 2 is held at an appropriate reference voltage, generally earth, (zero volts).

In order to programme the MNOS memory transistor M2, the second or clocking voltage supply line 3 is held at the same potential as the first voltage supply line 2, generally zero volts, and the switch SW2 is open while the switch SW1 is closed so that the voltage Vpp of the voltage supply line 5 is applied to the gate or control electrodes g of the MNOS transistor M2 as shown by Figure 5d so that the MNOS transistor M2 is in its linear region. In this example, a negative voltage is applied to the gate electrode of the MNOS transistor M2.The electric field thus generated between the drain and gate electrodes of the MNOS transistor M2 causes charge carriers (in this case holes, because of the polarity of the applied electric field) to be injected into the gate insulating layer where they are trapped at or near the interface between the first and second different insulating layers. At a time t1, the switch SW1 is opened so removing the voltage Vpp from the gate or control electrode g of the MNOS memory transistor M2. At the same time, the switch SW2 is closed so coupling the gate and source electrodes of the MNOS transistor M2 and the voltage on the second or clocking voltage supply line 3 is raised to Vdd to enable the MNOS transistor M2 to act as a current source.

Figure 6 shows by way of the curve B the drain current Id versus gate source voltage Vgs characteristic of the MNOS transistor M2 before programming, that is when no charge is stored within the gate insulating layer and by way of the curve A the drain current versus gate-source voltage for a fully programmed MNOS transistor M2. As will be appreciated programming has been carried out by the application of a negative voltage to the control or gets electrode of the MNOS transistor so causing the characteristic to move towards the right in Figure 6 giving a higher Ids at Vgs=O then for an unprogrammed transistor.As can be seen from Figure 6, when the MNOS memory transistor M2 has been programmed as described above with reference to Figure 5, then in the inverter mode, that is with the appropriate positive voltage applied to the second voltage supply line 3, a current flows. The magnitude of the current will of course depend on the width to length W/L ratio of the transistor conduction channel and on the gate-source and drain-source voltages Vgs and Vds. In the example shown, a current greater than 1 x10 6 amperes flows through the MNOS memory transistor M2. In contrast, the current through an unprogrammed gate-source coupled MNOS transistor M2 is of the order of just greater than 1x10-1l amperes, which is effectively simply a leakage current.

Accordingly, by programming the MNOS device, the Id versus Vgs characteristic has been altered so that an appreciable current flows when the gate source voltage Vgs is zero. The fact that the gate and source of the MNOS memory device M2 are coupled together means that the gate-source voltage of the memory transistor is held constant and accordingly the memory transistor M2 acts as an effectively constant current source when operated in its saturation region. The constancy of the current source is dependent on the channel length modulation factor A which is the slope of the drain-source current Ids versus drain-source voltage Vds curve in the saturation region. This enables the inverter circuit to have a high output impedance because the voltage on the output line 0 does not modulate the operation of the MNOS memory transistor M2.Thus, a high output impedance inverter circuit can be provided which avoids the use of complimentary MOS technology and also avoids the use of additional components such as capacitors which would significantly increase the area occupied by the inverter circuit. Furthermore, the MNOS memory transistor M2 is programmed after manufacture and its characteristics are thus not entirely determined by the manufacturing process. Indeed, it should be possible for analogue applications to adjust the programming of the MNOS transistor M2 and thus adjust the conductance of the transistor M2 to meet specific circuit requirements.

Figure 7 shows in greater detail one example of a circuit ic in accordance with the invention. In the example shown in Figure 7, the driver transistor M1 and the load transistor M2 have the same form as shown in Figure 4. However, in the example shown in Figure 7, each of the switches SW1 and SW2 is in the form of an n-channel enhancement mode MOS transistor similar to the driver transistor M1 but possibly having longer channel lengths because higher voltages will generally be applied across SW1 and SW2. Thus, the NMOS transistors forming the switches SW1 and SW2 have their first and second main electrodes s and d coupled between the voltage supply line 5 and the gate electrode g of the MNOS transistor M2 and between the gate and source of the MNOS transistor M2, respectively. The gate or control electrode of the NMOS transistor SW1 is coupled to a voltage supply line 6 while the gate of the NMOS transistor SW2 is coupled to a voltage supply line 7.

Figure 8 shows timing diagrams for the inverter circuit 1 c shown in Figure 7.

Figure 8a shows the change with time of the voltage applied to the second voltage supply line 3 while Figure 8b shows the voltage 01 applied to the voltage supply line 6, Figure 7c shows the voltage Vx applied to the voltage supply line 5 and Figure 7d shows the voltage 02 applied to the voltage supply line 7. The voltage supply line 2 is held at a reference potential, zero volts in this example.

In order to programme the MNOS memory transistor M2, the second voltage supply line 3 is held at the same potential as the first voltage supply line 2, namely zero volts. In this example, the voltage supply line 6 is similarly held at zero volts. It is necessary to ensure that the switch SW2 is rendered non-conducting and this is done by applying an appropriately negative voltage Vgl to the voltage supply line 7, that is to the control electrode g of the NMOS transistor SW2. At the same time, an appropriate negative programming voltage Vpp is applied to the voltage supply line 5 which is coupled to the drain electrode of the NMOS switch SW1. This programming voltage may be any suitable negative voltage in this example, provided that the MNOS transistor M2 remains in its linear region.The negative voltage Vgl applied to the voltage supply line 7 may be any negative voltage sufficient to ensure that the NMOS transistor, SW2 remains nonconducting. The programming voltage Vpp is thus applied via the switch SW1 to the gate or control electrode of the MNOS memory transistor M2 so that the resulting electric field between the drain and gate electrodes of the memory transistor M2 results in charge injection into the gate insulating layer so as to change the memory transistor from its first unprogrammed state to its second programmed state in which charge is stored at the gate insulating layer and the MNOS memory transistor M2 has a characteristic similar to curve A in Figure 6, that is so that, when an appropriate voltage is applied between the gate and source electrodes of the memory transistor M2, an appreciable current flows through the transistor M2 with the gate and source of the memory transistor M2 coupled together.

Of course, the amount of charge stored by the memory transistor M2 will depend upon the memory transistor's precise characteristics and geometry, the programming voltage Vpp and the duration of the programming voltage Vpp. In principle, for analogue applications, it should be possible to adjust the degree of programming so that the actual Ids versus Vgs characteristic lies anywhere between the fully programmed curve A and the unprogrammed curve B shown in Figure 6, provided that the memory transistor M2 can be in its linear region for programming and its saturation region (to enable an essentially constant current to be provided) during subsequent operation. As will be appreciated from Figure 6, the larger (more negative) the programming voltage the higher the current Ids, provided all other variables remain unchanged.Generally speaking, for analogue applications, the programming will be such that the Ids at Vgs = 0 lies somewhere around the midpoint between the curves A and B. Of course, for digital applications a larger programming voltage Vpp will be used so that the Ids versus Vds curve approaches curve A. Typically, a programming voltage Vpp of -30 volts for 1 millisecond may be used to achieve the curve A for a thin film transistor having a structure such as that described hereafter with reference to Figures 11 to 14, although the actual programming will depend upon the precise physical characteristics of the memory transistor M2 being programmed.

Once the memory transistor M2 has been programmed, the voltage Vx on the voltage supply line 5 is raised at time tx in Figure 8 to a positive voltage VH sufficient to render the switch SW1 nonconducting (its gate is, as indicated by Figure 8b, still grounded). At the same time, the voltage < 02 on the voltage supply line 7 is raised to a positive value Vg2 to render the switch SW2 conducting so as to couple together the gate and source electrodes of the MNOS memory transistor M2.The MNOS memory transistor M2 is now in its programmed state ready to function as the load device of the inverter of the circuit ic. In order for the memory transistor M2 to operate as a current source, the voltage on the second voltage supply line 3 is raised at a time ty after time tx, to a positive voltage Vdd so enabling a current to flow through the memory transistor M2 which, by virtue of its gate-source coupling, acts as an effectively constant current source provided that the memory transistor M2 is operating in its saturation region. The degree of constancy of the current source will of course depend upon the channel length modulation factor of the memory transistor M2. Thus, when an input voltage Vin is applied to the input voltage supply line I, an inverted output signal Vout will be supplied on the output voltage supply line 0.

Of course, other methods for programming the MNOS memory transistor M2 may be used. Thus, for example, the voltage 01 on the voltage supply line 6 may be lowered at the time t=tx so as to ensure that the switch SW1 is rendered non-conducting, that is the switch SW1 may be coupled to a clocking waveform. The important point is that the voltages applied to the various voltage supply lines must ensure that the switch SW1 is conducting and the switch SW2 is nonconducting during the programming of the MNOS memory transistor M2 and that the switch SW1 is non-conducting and the switch SW2 is rendered conducting for operation of the circuit as an inverter.

Once the memory transistor M2 has been programmed it may be possible to burn in the programming of the MNOS transistor M2 so that the switch SW1 is rendered permanently open circuit, while the switch SW2 is short circuited or rendered permanently conducting. For example, the switch SW1 could be fused or the coupling of the switch SW1 to the control electrode of the MNOS memory transistor M2 laser scribed or otherwise cut. The switch SW2 may be rendered permanently conducting if, for example, it itself is an MNOS transistor and a sufficiently large voltage pulse is applied to the voltage supply line 7.

It may, however, be of advantage to have the switches SW1 and SW2 remaining in the circuit so as to enable, if necessary, reprogramming of the memory transistor M2 so as, for example, to adjust the current that flows through the memory transistor M2 during operation of the circuit. The voltages supplied to the voltage supply lines 2, 3, 5, 6 and 7 may be controlled in any appropriate conventional manner. Thus, these voltage supply lines may be connected to appropriate voltage sources by appropriate switches, for example nchannel enhancement mode MOS transistors, controlled by shift registers or other suitable logic circuitry in a manner similar to that used for addressing the pixels of an active matrix addressed liquid crystal display device or a two dimensional memory array. Where it is desired to reprogram the memory transistor M2, then it may be necessary (for example if a smaller degree of programming is required) to erase the charge already stored at the memory transistor M2 before reprogramming. This may possibly be done optically, for example by using an ultra-violet light source, depending upon the actual nature of the memory transistor M2, or may be done by applying a high positive voltage from the voltage supply line 5 to the gate electrode of the memory transistor M2 via the switch SW1 while holding the switch SW2 non-conducting (for example by grounding its gate electrode).

The inverter circuit 1 b shown in Figure 4 or the inverter circuit 1 c shown in Figure 7 may, of course, form part of a larger circuit. Indeed, an inverter circuit in accordance with the invention may be used in any suitable situation where a conventional inverter circuit may have been used. Furthermore, a gate-source coupled programme memory transistor such as the transistor M2 shown in Figures 4 and 7 may be used in any circumstances where an active as an effectively constant current source may be required. Examples of possible digital circuits where such current sources or inverter circuits may be used are described in the aforementioned paper by Mohammed Elmasry.For example, a gate-source coupled programmed memory transistor in accordance with the invention may be used as the load in an NMOS NAND gate logic circuit, an MNOS NOR gate logic circuit or other logic circuits formed of combinations of those two previously mentioned circuit and in other logic circuit components such as flip flops and the like.

Figures 9a and 9b show examples of analogue circuits incorporating an inverter circuit in accordance with the invention.

Figure 9a shows an analogue cascode amplifier 9 in which a further NMOS transistor M3 is coupled in series with the driver transistor M1.

A bias voltage Vbias is applied to the gate electrode of the transistor M3. The transistor M3 acts to increase the output resistance and reduces the effect of the Miller capacitance on the input of the amplifier 9. Such an amplifier may be used in any circumstances where a single input operational amplifier is required, for example in a switched capacitor voltage amplifier.

Figure 9b shows an example of a differential amplifier 10 in which each arm comprises an inverter circuit ib or ic each having transistors M1 and M2 and M1' and M2' coupled to the first voltage supply line 2 via a current source CS such as an NMOS transistor operated in its saturation region. In this example, as is conventional, the inputs Vinl and Vin2 to the differential amplifier are supplied to the respective control gates of the two transistors M1 and Mi'. The output line OA of the differential amplifier 10 is coupled to the source electrode s of the MNOS transistor M2'.

One example of an application where a current source or circuit in accordance with the invention may be particularly advantageous is in a programmable read only memory array such as an electrically erasable programmable read only memory (EEPROM) because such a circuit will, of course, already include memory transistors so that no additional processing steps should be required to incorporate the gate-source coupled programmed memory transistors apart from a number of minor masked specifications.

Figure 10 shows very schematically one example of memory device 30 having a 2-dimensional array 31 of storage elements M5 in the form of MNOS memory transistors. The memory transistors M5 are arranged in rows and columns with one of the first and second main electrodes of each memory transistor M5 in a column being coupled to an associated first column conductor 11 and the other of the first and second main electrodes of each memory transistor M5 being coupled to a respective associated switching element M6 in the form of, in this example, an NMOS transistor.The gate electrodes of each of the switching transistors M6 in a row of storage elements M5 are coupled to a first row conductor 1 2 while the other of the first and second main electrodes of each switching element M6 in a column of storage elements are coupled to an associated second column conductor 1 3.

The gate electrodes of each memory transistor M5 in a given row are coupled to an associated second row conductor 14.

The first row conductors 12 are all coupled to appropriate conventional row decoder circuitry 1 5 which may include a shift register or the like logic circuity controlling the operation of switching elements to enable the appropriate voltages to be supplied to the row conductors at the appropriate time. Similarly, the second row conductors 14 are coupled to decoder circuitry 1 6 which may be of a similar nature to the row addressing circuitry 15.

Each second column conductor 13 is coupled to one main electrode of an associated first data-in transistor (generally an NMOS transistor) M7 having its gate electrode coupled to the gate electrode of an associated second data-in transistor M8. The other main electrodes of all of the first and second data-in transistors M7 and M8 are coupled to conventional data in control circuitry 1 7. The coupled gates of the first and second data-in transistors M7 and M8 are coupled via respective single input inverters/not gates 1 8 to column decoder circuitry 1 9 and to the gates of associated first and second read-out transistors M9 and M10.Each first read-out transistor M9 has one main electrode coupled to the associated column conductor 1 3 and the other main electrode coupled to an output line 20 which is coupled to earth (ground) via a read/write control transistor M11 having a control input Cl. Each second read-out transistor M10 has one main electrode coupled to the associated column conductor 11 and the other main electrode coupled to ground.

The decoder/addressing circuitry 15, 1 6 and 1 9 are coupled to three different voltage supply lines, generally + 15, 0 and + 15 volts.

The voltage supply lines are shown simply as input lines in Figure 10 and the conventional control and addressing inputs shown simply as input arrows in Figure 1 0. The data-in control 1 7 is similarly coupled to the three voltage supply lines and to a control input of conventional type. The output line 20 is coupled to the control or gate electrode of the transistor Mi' of a differential amplifier which may have the structure described above with reference to Figure 9b or may, as shown in Figure 10, be an asymmetric differential amplifier 10a in which the load M2 is omitted from the arm containing the transistor M1'. Such an asymmetric differential amplifier 1 Oa may have twice the gain of the amplifier 10 shown in Figure 9b.The other input to the differential amplifier, that is the input to the control or gate electrode of the transistor M1, is a reference voltage Vref. The output voltage on the output voltage supply line OA of the differential amplifier may be supplied to any suitable reader such as a computer or the like.

Although Figure 10 shows only a 2x2 array 31 of memory or storage elements M5, it will, of course, be appreciated by those skilled in the art that the array of storage elements will generally be much larger.

In operation of the device shown in Figure 10, each of the memory transistors M5 will be in either a first memory state in which no charge is stored at the memory transistor so that the transistor has a characteristic similar to the curve B shown in Figure 6 or a second memory state in which charge is stored at the memory transistor M5 and so the transistor has a characteristic similar to curve A in Figure 6.

Generally a memory transistor in the first memory state will represent a logical or binary zero while a transistor in the second state will represent a logical or binary one. However, it will, of course, be appreciated that the situation could be reversed. Thus, the array stores data as a two dimensional array of logical zeros and ones with each memory transistor M5 representing either a logical zero or a logical one.

Briefly, a storage element of the array 30 is programmed by applying a negative voltage (generally -15 volts) to the row conductor 14 associated with the memory transistor M5 and a positive voltage (generally + 15 volts) to the row conductor 1 2 associated with the switching transistor M 6. The column decoder circuity 1 9 renders conducting the associated data-in transistors M7 and M8 and the datain control circuitry 1 7 supplies a positive (generally + 15 volts) voltage to the column conductors 1 3 and 11. Thus, the switching transistor M6 of the selected pixel is rendered conducting and programming voltages are applied across the memory transistor M5 of that pixel to program that memory transistor.

To erase data stored at a pixel, then the associated row conductor 14 is supplied with +15 volts, the other associated row conductor 1 2 is supplied with 0 or -15 volts, and the data-in transistors M7 and M8 of the column conductors 1 3 and 11 are rendered conducting to supply -15 volts to the associated column conductors 1 3 and 11 (all the rest of the column conductors 1 3 and 11 are at zero watts) In order to read data stored at a particular pixel, the row decoder circuitry 1 5 renders the appropriate switching transistor M6 conducting by supplying a positive (generally + 15 volts) signal to its gate (and the gates of all the switching transistors M6 is the same row). The gates of all the switching transistors M6 of all the other rows are grounded.

The column decoder circuitry 1 9 renders conducting the read-out transistors M9 and M10 of the requisite column conductors 11 and 13 and turns on the data-in transistors M7 and M8 of all the other columns.

The data-in control circuitry 1 7 supplies a zero volt signal so that all the column conductors except those associated with the selected column conductors 11 and 1 3 are grounded and isolated from the read-out amplifier 10a. Of course, when the read-out transistors M9 and M10 are turned on, the source electrode of the selected MNOS transistor M5 is grounded. A large current Ir is supplied to the readout amplifier 1 Oa when the selected memory transistor M5 is programmed whereas no current will be supplied if the transistor M5 is unprogrammed. The read out amplifier 10a can thus detect whether the memory transistor represents a logical one or a logical zero.

Of course, the storage elements M5 need not necessarily be memory transistors but could be other devices. Thus, for example, the two-dimensional array device may be an image sensor with the storage element of the two dimensional array being photosensitive devices such as photodiodes. In such a case, a differential amplifier or amplifiers 10 or 1 0a may be used to determine when light above a given threshold is detected.

Of course, circuits in accordance with the invention may be used, as indicated above, in any suitable instance where a conventional current comprising an inverter may be used and are of particular advantage where only one conductivity type, generally n conductivity type, of transistor is available for technological or other reasons, for example where the current source or inverter forms part of logic circuitry integrated with a power semiconductor device to form a so called intelligent power switch or other circumstances where p-channel devices with appropriate characteristics cannot be formed.

Although, as indicated above, the present invention may be used in circumstances where the current source or inverter is to be formed using bulk technology, that is where the current source or circuit is integrated within a semiconductor body or substrate, it is particularly intended that the present invention be used in circuits formed using thin film technology where it may be difficult to form p-channel MOS transistors with the required characteristics.

Figures 11 to 14 illustrate one way of forming an NMOS transistor and an MNOS transistor, for example the transistors M1 and M2 shown in Figure 4, at the same time on an insulating substrate using thin film technology. In the example to be described, the MOS thin film transistors are coplanar transistors, that is the gate, drain and source electrodes are formed on the same surface. However, the present invention may, of course, also be applied where the thin film transistors have a staggered or inverted structure.

As shown in Figure 11, in this example, an intrinsic (that is notintentionally doped) layer of amorphous or polycrystalline material such as silicon is first deposited onto an insulative substrate 19, for example, a glass or plastic substrate capable of withstanding the processing temperatures. Subsequently a layer of the same material but doped so as to be n-conductivity type is deposited and the two layers are patterned to define the conduction channel region 20 of the transistors M1 and M2 and source and drain doped contact regions 21 and 22. As is known in the art, the doped contact regions 21 and 22 facilitate electrical contact between the subsequent source and drain electrodes and the conduction channel region 20 and may, in some circumstances, be omitted.

After definition of the contact regions 21 and 22, a relatively thin (for example 100 micrometres layer 23 of an insulating material, for example silicon dioxide, is deposited over the structure (which may include more transistors and other components than are actually shown in Figure 11). An etch stop layer 24, in this example, a layer of amorphous silicon having a thickness of about 100 micrometres, is then deposited over the silicon dioxide layer 23.

A suitable mask 28 is then provided over the etch stop layer 24 and patterned to define a window over the areas where the MNOS transistor M2 is to be formed to produce the structure shown in Figure ii. The portions of the etch stop layer 24 and silicon dioxide side layer 23 exposed through the window 28a are then etched away to leave the structure shown in Figure 1 2.

Sequential thin layers 25 and 26 of first and second insulating materials for forming the gate insulating layer of the MNOS transistor are then deposited over the etch stop layer 24. Typically, the layer 25 is a layer of silicon dioxide having a thickness of 2.5 to 5 nanometres while the layer 26 a layer of silicon nitride with a thickness of about 100 micrometres.

A further mask 29 is then provided as shown in Figure 1 3 to protect the areas where the MNOS transistors are to be formed. The exposed regions 26a and 25a of the thin layers 26 and 25 over the area where the NMOS transistor is to be formed are then etched away using the amorphous silicon layer 24 as an etch stop layer. An etchant which selectively etches amorphous silicon with respect to silicon dioxide is then used to remove the remaining portion of the etch stop layer 24.

Contact holes over the source and drain contact regions 21 and 22 are then formed using an appropriate mask and finally metallisation is deposited and patterned to define the source, drain and gate electrodes s, d and g of the NMOS and MNOS transistors M1 and M2 as shown in Figure 14.

Although in the examples described above the memory transistor comprises an MIOS transistor, other suitable forms of memory transistor may be used. Thus, for example, the memory transistor M2 may be a floating gate memory transistor where the charge storage layer 4 shown in Figure 1 comprises a conductive plane, for example a metal or doped semiconductor layer, encapsulated in insulating material. Such a memory transistor is programmed in a similar way to the MIOS transistor described above with the charge injected into the gate insulating region being stored at the conductive plane. In addition, although the above-described examples discuss electrical programming of the memory transistor M2, other suitable programming methods, for example ionizing radiation, may be used.Furthermore, although the above examples relate to n conductivity type circuits, that is circuits where the majority charge carriers are electrons, the present invention could also be supplied to p conductivity type circuits, that is circuits where the majority charge carriers are holes, with appropriate modification of the circuit and voltage polarities. Given this, the term current source as used herein should be understood to mean a current source for n conductivity type circuits (for example where the memory transistor is an n channel MNOS transistor) and a current sink for p conductivity type circuits (for example where the memory transistor is a p channel MNOS transistor).

From reading the present disclosure, other modifications and variations will be apparent to persons skilled in the art. Such modifications and variations may involve other features which are already known in the art and which may be used instead of or in addition to features already described herein. Although claims have been formulated in this application to particular combinations of features, it should be understood that the scope of the disclosure of the present application also includes any novel feature or combination of features disclosed herein either explicitly or implicitly, whether or not relating to the same invention as presently claimed in any claim and whether or not it mitigates any or all of the same technical problems as does the presently claimed invention. The applicants hereby give notice that new claims may be formulated to such features and/or combinations of such features during prosecution of the present application or of any further application derived therefrom.

Claims

1. A circuit having a current source comprising a gate-source coupled programmed memory transistor.

2. A circuit having a current source comprising a memory transistor having a first memory state and a second memory state in which the memory transistor is programmed and stores charge, a first switch for coupling the control electrode of the transistor to a voltage supply line for changing the memory state of the transistor from the first to the second state and a second switch for coupling the control electrode and one of the first and second main electrodes of the transistor together when the memory device is in the second state to form the current source.

3. A circuit comprising an inverter, the circuit comprising first and second voltage supply lines, an input signal line for receiving an input signal to be inverted and an output signal line for supplying an inverted output signal, a transistor having first and second main electrodes and a control electrode with the first main electrode coupled to the first voltage supply line, the control electrode being coupled to the input signal line and the second main electrode being coupled to the output signal line and a load device coupling the second main electrode of the transistor to the second voltage supply line, the load device comprising a gate-source coupled programmed memory transistor.

4. A circuit comprising an inverter, the circuit comprising first and second voltage supply lines, an input signal line for receiving an input signal to be inverted and an output signal line for supplying an inverted output signal, a transistor having first and second main electrodes and a control electrode with the first main electrode coupled to the first voltage supply line, the control electrode being coupled to the input signal line and the second main electrode being coupled to the output signal line and a load device coupling the second main electrode of the transistor to the second voltage supply line, the load device comprising a memory transistor having a first memory state and a second memory state in which the memory transistor is programmed and stores charge, a first switch for coupling the control electrode of the transistor to a voltage supply line for changing the memory state of the transistor from the first to the second state and a second switch for coupling the control electrode and one of the first and second main electrodes of the transistor together when the memory device is in the second state to form the load device.

5. A circuit according to claim 3 or 4, wherein the transistor and the memory transistor are the same conductivity type.

6. A circuit according to claim 2, 4 or 5, wherein the first and second switches comprise insulated gate field effect transistors.

7. A circuit according to any one of the preceding claims, wherein the memory transistor comprises an MIOS transistor.

8. A circuit according to any one of the preceding claims, wherein the memory transistor comprises a floating gate transistor.

9. A circuit according to any one of the preceding claims, formed using thin film technology.

10. A device comprising a two dimensional array of storage elements arranged in rows and columns, row and column conductors for accessing individual ones of the storage elements and control circuitry for controlling access of the storage elements by the row and column conductors, the control circuitry comprising at least one circuit in accordance with any one of Claims 1 to 8.

11. A method of forming a current source, which method comprises providing a memory transistor having a first memory state and a second memory state in which the memory transistor stores charge, coupling the control electrode of the transistor to a voltage supply line so changing the memory state of the transistor from the first to the second state and then disconnecting the coupling to the voltage supply line and coupling the control electrode and one of the first and second main electrodes of the transistor together to form the current source.