GB2291316A - Combined equalization and error detection - Google Patents

Combined equalization and error detection Download PDF

Info

Publication number
GB2291316A
GB2291316A GB9513612A GB9513612A GB2291316A GB 2291316 A GB2291316 A GB 2291316A GB 9513612 A GB9513612 A GB 9513612A GB 9513612 A GB9513612 A GB 9513612A GB 2291316 A GB2291316 A GB 2291316A
Authority
GB
United Kingdom
Prior art keywords
symbol
symbols
branches
dfu
controller
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
GB9513612A
Other versions
GB9513612D0 (en
GB2291316B (en
Inventor
Daniel Yellin
Ofer Amrani
Leon Bruckman
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Tadiran Israel Electronics Industries Ltd
Original Assignee
Tadiran Israel Electronics Industries Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Tadiran Israel Electronics Industries Ltd filed Critical Tadiran Israel Electronics Industries Ltd
Publication of GB9513612D0 publication Critical patent/GB9513612D0/en
Publication of GB2291316A publication Critical patent/GB2291316A/en
Application granted granted Critical
Publication of GB2291316B publication Critical patent/GB2291316B/en
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H04ELECTRIC COMMUNICATION TECHNIQUE
    • H04LTRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L1/00Arrangements for detecting or preventing errors in the information received
    • H04L1/004Arrangements for detecting or preventing errors in the information received by using forward error control
    • H04L1/0056Systems characterized by the type of code used
    • H04L1/0061Error detection codes
    • HELECTRICITY
    • H04ELECTRIC COMMUNICATION TECHNIQUE
    • H04LTRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L1/00Arrangements for detecting or preventing errors in the information received
    • H04L1/004Arrangements for detecting or preventing errors in the information received by using forward error control
    • H04L1/0045Arrangements at the receiver end
    • H04L1/0047Decoding adapted to other signal detection operation
    • HELECTRICITY
    • H04ELECTRIC COMMUNICATION TECHNIQUE
    • H04LTRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L25/00Baseband systems
    • H04L25/02Details ; arrangements for supplying electrical power along data transmission lines
    • H04L25/03Shaping networks in transmitter or receiver, e.g. adaptive shaping networks
    • H04L25/03006Arrangements for removing intersymbol interference
    • H04L25/03012Arrangements for removing intersymbol interference operating in the time domain
    • H04L25/03019Arrangements for removing intersymbol interference operating in the time domain adaptive, i.e. capable of adjustment during data reception
    • H04L25/03057Arrangements for removing intersymbol interference operating in the time domain adaptive, i.e. capable of adjustment during data reception with a recursive structure

Abstract

A signal processor is provided for high-rate digital communications over band-limited noisy channels. There is a combined system comprising a single feed-forward filter 40, a plurality of decision devices and feedback filters 42, 43 and an, error detection decoder means, which operate on a serial sequence of received channel symbols. Cyclic redundancy check coding is used. The decision devices select the closest and next closest symbols, and corresponding metrics, and the controller/decoder checks the paths and selects the most reliable output. <IMAGE>

Description

FIELD OF THE INVENTION: There is provided an improved system and method of combined equalization and error detection for attaining a more reliable high-rate digital communication.
STATE OF THE PRIOR ART: High-rate, or equivalently wide-band, digital signaling over band-limited channels often results with severe intersymbol interference, where a symbol interferes with some past and future transmitted symbols. Classical techniques to mitigate this problem include, linear equalization; decision feedback equalization (DFE) and maximum likelihood sequence estimation (MLSE). Independently, the problem of additive noise was also well researched, error correcting codes and coded modulation schemes can effectively reduce its undesirable effect.
For channels suffering from both intersymbol interference and noise, the best known receiver is the maximum likelihood sequence estimator, efficiently implemented using the Viterbi decoder. However, this receiver is complex and hardware consuming especially when the channel memory is long. In many cases DFE attains about the same performance as the Viterbi decoder in a much simple way, its drawback is error propagation that may result when the feedback part of the DFE contains a decision error. A straight-forward approach, i.e. cascading of DFE and decoding, is hardly the optimal solution since the decoded symbols which are the most reliable data, are not fed back to the equalizer, and thus do not take part in providing predictive corrections to future received symbols.
The undesirable effects of intersymbol interference and noise are obviously interrelated on such channels, consequently a combined equalization and decoding approach can outperform the cascading approach.
One such combined technique, utilized Tomlinson precoding, where a part of the equalizer is located at the transmitter. This technique is limited primarily because the receiver must update the transmitter with the channel parameters as they change. A few variations of this technique are also used.
Another combined technique is a subject of US Patent No. 4,821,288 by Robert E. Peile, entitled "Parallel Channel Equalizer Architecture". In this technique n individual DFE's process a sequence of helically interleaved nsymbol codewords such that the n individual equalizers simultaneously furnish an n-symbol vector (corresponding to a codeword) to an error correction decoder. The decoded symbols are then fed to the decision feedback filter as a more reliable data for future received symbols. Note that the decoder is placed in the feedback path, and that helical interleaving is employed to overcome the undesirable delay introduced by the decoder.
The approach taken in the present invention is far simpler both conceptually and practically. The present invention is applicable to all channels suffering from intersymbol interference and additive noise such as in HDSL, ADSL, ATM, ISDN, PC-modems.
SUMMARY OF THE INVENTION: The invention relates to a combined system, comprising a single feedforward filter, a plurality of decision feedback filters, error detection decoder means and a controller means operating on a sequence of received channel symbols. A sequence of N symbols, corresponding to an N-symbol codeword, is transmitted over a channel perturbed by additive noise and intersymbol-interference. In the receiver, an equalizer initially detects the incoming channel symbol-samples. A controller dynamically allocates the B most unreliable symbol detections in the received sequence, and assigns an alternative continuing DFE path (branch), originating at these suspected locations. The value of the integer B is determined by the characteristics of the channel and the requested performance.Finally, a decoder is utilized to select one out of the N-symbol paths, preferably the most likely path, according to a predefined set of rules.
Thus, the invention relates to a signal processor for a serial sequence of received symbols, grouped as N-symbols codewords, with B independent concurrent branches, said processor comprising: means for providing all said B branches with a sequence of received symbol samples, modified by a feedforward filter in such a manner as each symbol is interfered by previously modified symbols only; means associated with each of said B branches for performing feedback filtering and present symbol estimation; means associated with each of said B branches for determining the closest and the next closest symbol to the present symbol; error detection means for checking if an N-symbol path via said branches belongs to the code.
Such signal processor of may further comprise control means associated with each of said B branches for selecting the symbol to be fed back to the feedback filter, and there may be provided control means which govern all DFU assignments for the B branches, one DFU being always assigned to the standard path, said controll means sets encoding priority for N-symbol paths.
The invention further relates to a method comprising receiving a serial sequence of symbols, grouped as N-symbols codewords, constructed by encoding K symbols of source information; filtering the received sequence with a singly feedforward filter, common to all DFU-s, in such a manner as to remove the part of intersymbol interference from the present estimate caused by symbols that were transmitted after the symbol presently being estimated; in each DFU filtering the symbols, previously decided upon, by the feedback filter in such a manner as to form a replica of that part of intersymbol interference caused by previously decided symbols; in each DFU, reducing the output of the feedback filter from the output of the feedforward filter to obtain an equalized estimate of the present symbol; in each DFU, computing the metric of the present estimate and deciding which is a reliable decision; opening an alternative branch for unreliable decisions, which are suspected DFE errors, in such a manner that there are B branches originating from the B most unreliable symbol decisions; decoding N-symbols paths, that correspond to codewords, in an order set by the controller in a manner that reflects the probability of the error events along the N-symbol path; selecting the first N-symbol path that belongs to the code as the ultimate output.
DESCRIPTION OF THE DRAWINGS: Figure 1. is a simplified block diagram of the transmitter.
Figure 2. illustrates a channel with intersymbol interference and additive noise.
Figure 3. is a simplified schematic scheme of a conventional decision feedback equalizer.
Figure 4. illustrates a combined receiver of the invention.
DETAILED DESCRIPTION Mathematical preliminaries Let a sequence of symbols {an}; where n = 0,1 and an are drawn from a finite alphabet, be transmitted over a discrete causal channel with additive noise. The output of such channel is given by
where h0 h1 , hM denotes the impulse response coefficients of the channel, M is a positive integer and vn are the noise samples. Without loss of generality let ho = 1. The channel output sequence (yin} in 1, may be observed at the output of the Feedforward filter 30 of the decision feedback equalizer depicted in Figure 3.
Referring to Figure 3, the equalizer estimate, Z,?, of the n-th symbol, an, may be expressed as
where a" is the n-th detected symbol at the output of the Decision device 31.
The symbol sequence an, will henceforth be referred to as the "standard path" For the sake of mathematical simplicity, assume that the modulator 11 of Figure 1 employs Pulse Amplitude Modulation for signaling over the channel of Figure 2. In that case, the symbols an are drawn from the set A = L+1, +3, ..+A) where A is an odd integer.
A channel errors is said to have happened if the noise sample V > 1 and a, + Vn # A.
A detection error is said to have happened if an # an.
The following property is important. Assuming that there were no previous detection errors, meaning = = ak for all k satisfying k < n, then the noise added to the n-th symbol is obtained from 2: Us = z7 all (3) Hence, the estimated value of the added noise vn = zn - an may provide a measure of confidence in the n-th decision. This measure will henceforth be referred to as the metric of the n-th symbol. The bigger V,, the more likely it is that a decision error had occurred in an, in other words, the decision on the n-th symbol is less reliable as Vn grows.
DESCRIPTION OF A PREFERRED EMBODIMENT: In the transmitter of Figure 1, K source information symbols enter the encoder 10 and a coded sequence {an}, corresponding to an N-symbol codeword is obtained at the encoder output. A systematic Cyclic Redundancy Check (CRC) code is employed for the following reasons, appearing in order of significance: 1. CRC codes have good error-burst detection capabilities, which is exactly the case when a singly decision error results in error propagation in a decision feedback equalizer system.
2. CRC codes possess a considerable amount of structure which enables encoding and decoding be very easily implemented using linear feedback shift registers.
3. A systematic code is used for receiver efficiency reasons.
Reason 3 requires some explanation. Error-detection capability, rather than error-correction capability, of the CRC code is to be exercised by the receiver of the present invention. In order to fully exploit the error detection capability of the code, it is enough to check if a detected N-symbol sequence, {an}, belongs to the code. Recalling that the first K symbols of a systematic codeword are the source information symbols while the last (N-K) symbols are the redundancy check symbols, this task may be performed simply by reencoding the first K detected symbols and then comparing the rest of the (N K) detected symbols with the redundancy. check symbols at the output of the re-encoder. If the last (N-K) symbols match, then the sequence (a,,) is a valid codeword.
A coded sequence (an) from the encoder 10 is modulated 11 and transmitted over the channel of Figure 2. The encoder 10 and modulator 11 need not be separate, combined encoder/modulator schemes such as trellis-coded modulation and lattice codes may be used.
The channel of Figure 2, introduces intersymbol interference 20 and additive noise, it has a discrete transfer function H(z) which is not necessarily casual.
In fact, most practical channels suffer from intersymbol interference introduced by both past and future transmitted symbols, it is due to the fading and dispersive characteristics of these channels.
The novel system is illustrated in Figure 4. Received symbol samples are first presented to the feedforward filter 40. The feedforward filter aims to remove the non-casual part of intersymbol interference, i.e. the part caused by symbols that were transmitted after the symbol currently being estimated.
This is different from the prior art in that a single feedforward filter is common to all feedback filters. There is no need for multiple feedforward filters since its content is independent of the decisions made by any decision device 42; (unlike the feedback filter 43i where the decisions made by decision device 42j are fed back to it). The feedforward filter is hardware consuming since it operates on 'real' values, rather than integer values. In the present invention a single feedforward filter is required, thus resulting with a most efficient hardware implementation.
The output Yn of the feedforward filter 40, which is a modified symbol sample, is simultaneously fed to all B independent continuing branches. Each branch employs a Decision and Feedback Unit (DFU).
in the DFU of index, a feedback filter 43 utilizes the previous decisions of decision device 42i to form a replica of that part of intersymbol interference caused by previously received symbols. This replica is subtracted 41 from the modified symbol sample Y,,. The result ani is the estimate of the present symbol an The decision device 42 selects, from the symbol set A, the closest symbol to z,,1 denoted aunt, accompanied by the corresponding metricivnil (the estimate of the noise value). The decision device also selects the next closest symbol to z,,,. What happens next is exclusively governed by the controller. The following events are possible: I.If the metric I < |vni| < I, where 0 < n < 1 is a preset threshold to be determined in accordance with the channels noise variance, a,i is considered to be a reliable decision and is thus fed back to the feedback filter 43i. No additional branch need to be "opened" so that no additional DFU is assigned.
II. If the metric T < lvn4 < 1, then â"iis not a reliable decision. Hence it is reasonable to assume that the next closest symbol to z,,1was in fact transmitted. The controller 'opens' an alternative branch, in effect it assigns an available DFU say of index k for this branch, the next closest symbol is considered as a reliable decision for that branch and is thus fed back to the feedback filter 43k. If none of the B DFU-s is available, the controller discards the leasf unreliable branch among the B independent branches and reassigns the corresponding DFU for the alternative branch. Obviously, the metricivA,nJ of the present symbol must be higher than the initial metric of the discarded branch.
In this manner, the controller dynamically enables at any time instance B branches originating for the B most unreliable symbol detections in the received sequence. DFUo is dedicated to the standard path, i.e. it consists of closest symbol decisions only.
The following two observations are important for practical reasons: 1. A new branch, erroneously opened, is most likely to result in error propagation. Such branches are normally characterized by consistently high metric of the symbols immediately following the branching point. The controller recognized these events and acts to discard such branches.
2. Nesting of branches, i.e. a branch originating from a branch, is permitted, since it is statistically possible for a second channel-error to occur while the error propagation caused by the first channel-error still lasts.
Knowing the channel characteristics, the nesting level may be upper-bounded by the controller.
Both observations enable resources, namely the B DFU-s, to be assigned to more probable events. Thus B should not be too big, the value of B may be determined as a compromise between hardware complexity and performance.
After a sequence of N symbols, corresponding to a transmitted codeword, is received and processed as described above, there are some N-symbol paths out of which one must be selected as the ultimate output. There are more than B N-symbol paths although there are only B DFU-s since most branches re-merge with the standard path after some symbols. The number of symbols in a branch, until re-merging with the standard path, is closely related to the average error-propogation length or the amount of memory in the channel.
The controller checks, in a predefined order, if an N-symbol path belongs to the code. The first path that belongs to the code is selected as the ultimate output. If none of the paths belongs to the code, the standard path is selected. The first K symbols of the selected path are the required source information data.
The order of path checking is such that more likely paths are given higher priority, and are thus checked first, as listed below: The standard path is checked first.
ii. Paths with smaller number of branches are prior.
iii. Among paths with same number of branches, those with smaller metric are prior.
Note all the paths in ii. are checked. The paths with number of branches greater than the expected number of channel errors are less likely, and thus not necessarily checked. On channels with high signal to noise ratios, the number of expected channel errors is very small even for long symbol sequences. Since CRC codes are easy to encode the receiver can encode all paths on the fly, and there is no need to wait until all N symbols are received and processed.
In yet another embodiment, the controller replaces some symbols in the standard path, with those of the most likely branches, in accordance with the expected number of channel errors. It then performs maximum likelihood decoding of the modified standard path, using the corresponding metrics.
Although the invention has been referring to the preferred embodiment in detail, other codes and equalization means may also be employed, with some variations, without departing from the spirit of the invention.

Claims (7)

CLAIMS:
1. A signal processor for a serial sequence of received symbols, grouped as N-symbols codewords, with B independent concurrent branches, said processor comprising: means for providing all said B branches with a sequence of received symbol samples, modified by a feedforward filter in such a manner as each symbol is interfered by previously modified symbols only; means associated with each of said B branches for performing feedback filtering and present symbol estimation; means associated with each of said B branches for determining the closest and the next closest symbol to the present symbol; error detection means for checking if an N-symbol path via said branches belongs to the code.
2. The signal processor of claim 1 further comprising controller means associated with each of said B branches for selecting the symbol to be fed back to the feedback filter.
3. The controller of claim 2 which governs all DFU assignments for the B branches, one DFU being always assigned to the standard path.
4. The controller of claim 2 sets encoding priority for N-symbol paths.
5. A combined receiver system for processing a serial sequence of received symbols, grouped as N-symbol codewords, in B independent concurrently DFU-s, said system comprising means to: a single feedforward register to receive a. serial sequence of received symbol sample and modify each symbol in such a manner as to form a replica of each symbol interfered by previously modified symbols only; a plurality of B independent decision devices for determining the closest and the next closest symbol to the present symbol estimation, and for computing the metric of the present symbol; a single controller to select one of said closest symbols from each said B decision devices, to determine which is the appropriate feedback filter to direct said selected symbol to, and to refresh its content if necessary; a plurality of B independent, identical feedback filters to receive a sequence of symbols, previously decided upon by said controller, and form a replica of interference caused by these symbols; error detection means for re-encoding the first K symbols of an N-symbol path and compare the resulting (N-K) symbols with same symbols of said path.
6. The controller of claim 5 further comprising means for determining the encoding priority of the N-symbol paths, and consequently the ultimate output.
7. A process comprising: receiving a serial sequence of symbols, grouped as N-symbols codewords, constructed by encoding K symbols of source information; filtering the received sequence with a singly feedforward filter, common to all DFU-s, in such a manner as to remove the part of intersymbol interference from the present estimate caused by symbols that were transmitted after the symbol presently being estimated; in each DFU, filtering the symbols, previously decided upon, by the feedback filter in such a manner as to form a replica of that part of intersymbol interference caused by previously decided symbols; in each DFU, reducing the output of the feedback filter from the output of the feedforward filter to obtain an equalized estimate of the present symbol; in each DFU, computing the metric of the present estimate and deciding which is a reliable decision; opening an alternative branch for unreliable decisions, which are suspected DFE errors, in such a manner that there are B branches originating from the B most unreliable symbol decisions; decoding N-symbols paths, that correspond to codewords, in an order set by the controller in a manner that reflects the probability of the error events along the N-symbol path; selecting the first N-symbol path that belongs to the code as the ultimate output.
GB9513612A 1994-07-04 1995-07-04 Equalization and error detection apparatus Expired - Fee Related GB2291316B (en)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
IL110202A IL110202A (en) 1994-07-04 1994-07-04 Equalization and error detection apparatus for high rate digital communications

Publications (3)

Publication Number Publication Date
GB9513612D0 GB9513612D0 (en) 1995-09-06
GB2291316A true GB2291316A (en) 1996-01-17
GB2291316B GB2291316B (en) 1999-05-19

Family

ID=11066302

Family Applications (1)

Application Number Title Priority Date Filing Date
GB9513612A Expired - Fee Related GB2291316B (en) 1994-07-04 1995-07-04 Equalization and error detection apparatus

Country Status (3)

Country Link
FR (1) FR2722046B1 (en)
GB (1) GB2291316B (en)
IL (1) IL110202A (en)

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6314102B1 (en) 1997-07-10 2001-11-06 Alcatel Telecommunications system for providing both narrowband and broadband services to subscribers
US7079586B1 (en) 2000-03-16 2006-07-18 Koninklijke Philips Electronics N.V. Systems and methods for optimal distribution of symbols in a fixed size data packet to improve receiver performance
CN109873777A (en) * 2017-12-01 2019-06-11 华为技术有限公司 A kind of error correction method and error correction device

Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0277393A1 (en) * 1987-01-20 1988-08-10 Koninklijke Philips Electronics N.V. Arrangement for cancelling intersymbol interference and noise
EP0294897A1 (en) * 1987-06-09 1988-12-14 Koninklijke Philips Electronics N.V. Data transmission system comprising a decision feedback equalizer and using partial-response techniques
US4821288A (en) * 1987-12-21 1989-04-11 Cyclotomics, Inc. Parallel channel equalizer architecture
US4833693A (en) * 1985-11-21 1989-05-23 Codex Corporation Coded modulation system using interleaving for decision-feedback equalization
GB2235112A (en) * 1989-06-09 1991-02-20 American Telephone & Telegraph Communications system incorporating error correction coding and decision feedback equalisers

Family Cites Families (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2683665B2 (en) * 1991-11-27 1997-12-03 日本電気株式会社 Maximum likelihood sequence estimator
CA2083304C (en) * 1991-12-31 1999-01-26 Stephen R. Huszar Equalization and decoding for digital communication channel
WO1993026106A1 (en) * 1992-06-18 1993-12-23 Oki Electric Industry Co., Ltd. Maximum likelihood sequence estimating device and method therefor

Patent Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4833693A (en) * 1985-11-21 1989-05-23 Codex Corporation Coded modulation system using interleaving for decision-feedback equalization
EP0277393A1 (en) * 1987-01-20 1988-08-10 Koninklijke Philips Electronics N.V. Arrangement for cancelling intersymbol interference and noise
EP0294897A1 (en) * 1987-06-09 1988-12-14 Koninklijke Philips Electronics N.V. Data transmission system comprising a decision feedback equalizer and using partial-response techniques
US4821288A (en) * 1987-12-21 1989-04-11 Cyclotomics, Inc. Parallel channel equalizer architecture
GB2235112A (en) * 1989-06-09 1991-02-20 American Telephone & Telegraph Communications system incorporating error correction coding and decision feedback equalisers

Cited By (12)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6314102B1 (en) 1997-07-10 2001-11-06 Alcatel Telecommunications system for providing both narrowband and broadband services to subscribers
US6940859B2 (en) 1997-07-10 2005-09-06 Alcatel Line termination equipment
US7023875B2 (en) 1997-07-10 2006-04-04 Alcatel Telecommunications system and subscriber equipment therefor
US7039065B2 (en) 1997-07-10 2006-05-02 Alcatel Telecommunications rack including shelves with nonredundant backplanes used redundantly
US7042900B2 (en) 1997-07-10 2006-05-09 Alcatel Housing for connection to both broadband and narrowband networks as a shelf in a telecommunications rack
US7092394B2 (en) 1997-07-10 2006-08-15 Alcatel Line termination equipment
US7099313B2 (en) 1997-07-10 2006-08-29 Alcatel Replaceable printed board assembly (PBA)
US7079586B1 (en) 2000-03-16 2006-07-18 Koninklijke Philips Electronics N.V. Systems and methods for optimal distribution of symbols in a fixed size data packet to improve receiver performance
CN109873777A (en) * 2017-12-01 2019-06-11 华为技术有限公司 A kind of error correction method and error correction device
EP3713167A4 (en) * 2017-12-01 2021-01-06 Huawei Technologies Co., Ltd. Error correction method and error correction apparatus
CN109873777B (en) * 2017-12-01 2021-12-17 华为技术有限公司 Error correction method and error correction device
US11218246B2 (en) 2017-12-01 2022-01-04 Huawei Technologies Co., Ltd. Error correction method and error correction apparatus

Also Published As

Publication number Publication date
FR2722046B1 (en) 1997-12-12
GB9513612D0 (en) 1995-09-06
IL110202A (en) 1997-07-13
FR2722046A1 (en) 1996-01-05
IL110202A0 (en) 1994-10-21
GB2291316B (en) 1999-05-19

Similar Documents

Publication Publication Date Title
US6178209B1 (en) Method of estimating trellis encoded symbols utilizing simplified trellis decoding
EP0573621B1 (en) Device and method for precoding
US5052000A (en) Technique for improving the operation of decision feedback equalizers in communications systems utilizing error correction
US4833693A (en) Coded modulation system using interleaving for decision-feedback equalization
US5243627A (en) Signal point interleaving technique
KR100785410B1 (en) Method and apparatus for shortening the critical path of reduced complexity sequence estimation techniques
JP5180319B2 (en) A method for decoding transmitted messages using multiple hypotheses
US6956872B1 (en) System and method for encoding DSL information streams having differing latencies
KR100988225B1 (en) Apparatus for and method of providing trellis decoded data, and equalizer/trellis decoder system
US5963598A (en) Symbol decoder
Anand et al. Continuous error detection (CED) for reliable communication
WO2009088533A1 (en) Decoding scheme using a-priori information about transmitted messages
JP3683501B2 (en) End of coded or uncoded modulation by path-oriented decoder
Yellia et al. Joint equalization and coding for intersymbol interference channels
US20050141629A1 (en) Hdtv trellis decoder architecture
US10177876B2 (en) Sequence detector
GB2291316A (en) Combined equalization and error detection
JP4443634B2 (en) Frequency selective digital transmission channel equalization and decoding device
WO2021243607A1 (en) Equalisation method and apparatus
US20030112885A1 (en) Method and apparatus for joint equalization and decoding of multilevel codes
Visoz et al. Joint equalization and decoding of trellis-encoded signals using the generalized Viterbi algorithm
SHOHON et al. Multilevel coding with adaptive equalization and interleaving for fading channel
Peile et al. A co‐designed coding, modulation and equalization scheme for the transmission of 155‐52 Mbit/s data over a 72 MHz intelsat transponder. Part 2: Equalization
Belzile et al. Decision feedback equalization and channel coding for multilevel modulation
Bauer et al. Performance of sequential detection schemes for trellis-encoded data signals distorted by intersymbol interference

Legal Events

Date Code Title Description
732E Amendments to the register in respect of changes of name or changes affecting rights (sect. 32/1977)
732E Amendments to the register in respect of changes of name or changes affecting rights (sect. 32/1977)
PCNP Patent ceased through non-payment of renewal fee

Effective date: 20100704